105 lines
2.1 KiB
Verilog
105 lines
2.1 KiB
Verilog
// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74LS175.sch - Thu May 24 17:45:09 2018
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`timescale 1ns / 1ps
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module chip74LS175_chip74LS175_sch_tb();
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// Inputs
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reg D0;
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reg D1;
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reg D2;
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reg D3;
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reg CP;
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reg CLRn;
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// Output
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wire Q0;
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wire Q0n;
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wire Q3;
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wire Q2;
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wire Q1;
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wire Q1n;
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wire Q2n;
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wire Q3n;
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wire [3:0] Qbus = {Q3,Q2,Q1,Q0};
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wire [3:0] Qbusn = {Q3n,Q2n,Q1n,Q0n};
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// TB
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integer i;
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integer errcnt;
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// Bidirs
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// Instantiate the UUT
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chip74LS175 UUT (
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.Q0(Q0),
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.Q0n(Q0n),
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.Q3(Q3),
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.Q2(Q2),
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.Q1(Q1),
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.Q1n(Q1n),
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.Q2n(Q2n),
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.Q3n(Q3n),
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.D0(D0),
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.D1(D1),
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.D2(D2),
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.D3(D3),
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.CP(CP),
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.CLRn(CLRn)
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);
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// Initialize Inputs
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// `ifndef auto_init
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initial begin
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$display("auto_init not set");
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#100;
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D0 = 0;
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D1 = 0;
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D2 = 0;
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D3 = 0;
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CP = 0;
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CLRn = 0;
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errcnt = 0;
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#5;
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CLRn = 1;
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#5;
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for (i=0; i<16; i=i+1) begin
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CLRn = 1;
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{D3,D2,D1,D0} = i[3:0];
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CP = 0; #5; CP = 1; #5;
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if ( Qbus != i[3:0] ) begin
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$display("Wrong answer i=%d Qbus=%d", i[3:0], Qbus);
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errcnt = errcnt + 1;
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end
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if ( Qbusn != ~i[3:0] ) begin
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$display("Wrong answer i=%d ~Qbus=%d", i[3:0], ~Qbus);
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errcnt = errcnt + 1;
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end
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//CP = 0; #5; CP = 1; #5;
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//if ( Qbus != (i[3:0]+1) ) begin
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// $display("Wrong answer i=%d Qbus=%d", i[3:0]+1, Qbus);
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//end
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CLRn = 0; CP = 0; #5; CP = 1; #5;
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if ( Qbus != 0 ) begin
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$display("Wrong answer i=%d CLRn=0 Qbus=%d should be zero", i[3:0]+1, Qbus);
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errcnt = errcnt + 1;
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end
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if ( Qbusn != 4'hf ) begin
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$display("Wrong answer i=%d CLRn=0 Qbusn=%d should be 15. ~0", i[3:0]+1, Qbusn);
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errcnt = errcnt + 1;
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end
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end
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if ( errcnt == 0 ) begin
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$display("**** PASSED **** errcnt=0");
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end else begin
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$display("!!!! FAILED !!!! errcnt=%d", errcnt);
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end
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end
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// `else begin
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// initial begin
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// $display("SET auto_init");
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// end
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// end
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// `endif
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endmodule
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