105 lines
2.4 KiB
Verilog
105 lines
2.4 KiB
Verilog
// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74LS257.sch - Wed Jun 06 16:37:03 2018
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`timescale 1ns / 1ps
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module chip74LS257_chip74LS257_sch_tb();
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// Inputs
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reg En_15;
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reg S_1;
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reg i0a_2;
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reg i1a_3;
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reg i0b_5;
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reg i1b_6;
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reg i0c_11;
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reg i1c_10;
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reg i0d_14;
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reg i1d_13;
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// Output
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wire Za_4;
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wire Zb_7;
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wire Zc_9;
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wire Zd_12;
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// Bidirs
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wire expectedA, expectedB, expectedC, expectedD;
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// Instantiate the UUT
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chip74LS257 UUT (
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.En_15(En_15),
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.S_1(S_1),
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.i0a_2(i0a_2),
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.i1a_3(i1a_3),
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.i0b_5(i0b_5),
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.i1b_6(i1b_6),
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.i0c_11(i0c_11),
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.i1c_10(i1c_10),
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.i0d_14(i0d_14),
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.i1d_13(i1d_13),
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.Za_4(Za_4),
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.Zb_7(Zb_7),
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.Zc_9(Zc_9),
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.Zd_12(Zd_12)
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);
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// Test Sim
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integer i, errct;
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assign expectedA = En_15 ? 1'bx : (S_1 ? i1a_3 : i0a_2 );
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assign expectedB = En_15 ? 1'bx : (S_1 ? i1b_6 : i0b_5 );
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assign expectedC = En_15 ? 1'bx : (S_1 ? i1c_10 : i0c_11);
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assign expectedD = En_15 ? 1'bx : (S_1 ? i1d_13 : i0d_14);
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// Initialize Inputs
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`ifdef auto_init
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initial begin
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$display("auto_init defined");
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end
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`else
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initial begin
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$display("auto_init not defined");
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end
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`endif
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initial begin
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En_15 = 0;
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S_1 = 0;
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i0a_2 = 0;
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i1a_3 = 0;
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i0b_5 = 0;
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i1b_6 = 0;
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i0c_11 = 0;
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i1c_10 = 0;
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i0d_14 = 0;
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i1d_13 = 0;
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errct = 0;
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#100;
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for (i=0; i<1024; i=i+1) begin
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{En_15, S_1, i1d_13,i1c_10,i1b_6,i1a_3, i0d_14,i0c_11,i0b_5,i0a_2} = i;
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#9;
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if ( Za_4 != expectedA ) begin
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$display("i:%d Za_4=%b expectedA=%b", i, Za_4, expectedA);
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errct = errct + 1;
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end
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if ( Zb_7 != expectedB ) begin
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$display("i:%d Zb_7=%b expectedB=%b", i, Zb_7, expectedB);
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errct = errct + 1;
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end
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if ( Zc_9 != expectedC ) begin
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$display("i:%d Zc_9=%b expectedA=%b", i, Zc_9, expectedC);
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errct = errct + 1;
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end
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if ( Zd_12 != expectedD ) begin
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$display("i:%d Zd_12=%b expectedD=%b", i, Zd_12, expectedD);
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errct = errct + 1;
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end
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#1;
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end
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if ( errct==0 ) begin
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$display("PASSED");
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end else begin
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$display("FAILED errct=%d", errct);
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end
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$finish;
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end
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endmodule
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