109 lines
2.1 KiB
Verilog
109 lines
2.1 KiB
Verilog
// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74S195.sch - Wed May 30 20:53:58 2018
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`timescale 1ns / 1ps
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module chip74S195_chip74S195_sch_tb();
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// Inputs
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reg CLRn_1;
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reg CP_10;
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reg SH_LDn;
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reg J_2;
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reg K_3;
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reg P0_4;
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reg P1_5;
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reg P2_6;
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reg P3_7;
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// Output
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wire Q0_15;
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wire Q1_14;
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wire Q2_13;
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wire Q3_12;
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wire Q3n_11;
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// Bidirs
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// simulation vars
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integer i, errct;
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wire [4:0] qbus = {Q3n_11,Q3_12,Q2_13,Q1_14,Q0_15};
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wire [4:0] pbus = {~P3_7,P3_7,P2_6,P1_5,P0_4};
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// Instantiate the UUT
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chip74S195 UUT (
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.CLRn_1(CLRn_1),
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.CP_10(CP_10),
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.SH_LDn(SH_LDn),
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.J_2(J_2),
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.K_3(K_3),
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.P0_4(P0_4),
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.P1_5(P1_5),
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.P2_6(P2_6),
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.P3_7(P3_7),
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.Q0_15(Q0_15),
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.Q1_14(Q1_14),
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.Q2_13(Q2_13),
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.Q3_12(Q3_12),
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.Q3n_11(Q3n_11)
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);
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// Initialize Inputs
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`ifdef auto_init
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initial begin
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$display("auto_init defined");
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end
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`else
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initial begin
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$display("not defined auto_init");
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end
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`endif
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initial begin
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CLRn_1 = 0;
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CP_10 = 0;
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SH_LDn = 0;
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J_2 = 0;
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K_3 = 0;
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P0_4 = 0;
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P1_5 = 0;
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P2_6 = 0;
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P3_7 = 0;
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errct = 0;
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#105
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CLRn_1 = 1;
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#5
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for (i=0; i<16; i=i+1) begin
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{P3_7,P2_6,P1_5,P0_4} = i[3:0];
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CP_10 = 0;
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#5
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CP_10 = 1;
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#5;
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if ( qbus!= pbus ) begin
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errct = errct + 1;
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$display("ERROR: qbus=%b != pbus=%b", qbus, pbus);
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end
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end
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#5;
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SH_LDn = 1;
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K_3 = 1;
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#5;
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// Test shifting in bits. Not used in APPLE II.
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for (i=0; i<16; i=i+1) begin
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if ( i[1:0]==0 ) begin
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J_2 = 0; K_3 = 1;
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end else begin
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J_2 = 1; K_3 = 0;
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end
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CP_10 = 0;
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#5
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CP_10 = 1;
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#5;
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end
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#10;
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if (errct == 0) begin
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$display("PASSED");
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end else begin
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$display("FAILED errct=%d", errct);
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end
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$finish;
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end
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endmodule
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