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AppleIISd
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freitz85 2017-05-06 17:31:51 +02:00
parent b69c5f194a
commit 125f6d91e1
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# Object files
*.o
*.ko
*.obj
#Gitignore for files generated by Xilinx ISE
*.log
*.svf
*.scr
*.cmd
*.bak
*.lso
*.elf
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.ace
*~
*#
*.swp
*.ini
*.html
*.vhi
*.wdb
*.stx
*.xmsgs
*.xreport
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
*.cmd_log
*_beh.prj
*.ncd
isim
db
incremental_db
work
*.cr.mti
vsim.wlf
transcript
webtalk.log
webtalk_impact.xml
pepExtractor.prj
impact.xsl
impact_impact.xwbt
# Debug files
*.dSYM/
*.su
spi6502b_html*/
__projnav*/
#ignore OS noise
Thumbs.db
.DS_Store

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SPI6502B.cel Normal file
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# begin LFP file C:\sources\spi65\SPI6502B.lfp
designfile spi6502b.ngd
IO_GROUP "spi_Nsel" ;
IO_GROUP "spi_miso" ;
IO_GROUP "spi_int" ;
IO_GROUP "cpu_d" ;
IO_GROUP "cpu_a" ;
NET "spi_sclk" COLOR=6 ;
NET "spi_Nsel<3>" COLOR=6 IO_GROUP="spi_Nsel" ;
NET "spi_Nsel<2>" COLOR=6 IO_GROUP="spi_Nsel" ;
NET "spi_Nsel<1>" COLOR=6 IO_GROUP="spi_Nsel" ;
NET "spi_Nsel<0>" COLOR=6 IO_GROUP="spi_Nsel" ;
NET "spi_mosi" COLOR=6 ;
NET "spi_miso<3>" COLOR=6 IO_GROUP="spi_miso" ;
NET "spi_miso<2>" COLOR=6 IO_GROUP="spi_miso" ;
NET "spi_miso<1>" COLOR=6 IO_GROUP="spi_miso" ;
NET "spi_miso<0>" COLOR=6 IO_GROUP="spi_miso" ;
NET "spi_int<3>" COLOR=6 IO_GROUP="spi_int" ;
NET "spi_int<2>" COLOR=6 IO_GROUP="spi_int" ;
NET "spi_int<1>" COLOR=6 IO_GROUP="spi_int" ;
NET "spi_int<0>" COLOR=6 IO_GROUP="spi_int" ;
NET "Ncs2" COLOR=6 ;
NET "extclk" COLOR=6 ;
NET "diag" COLOR=6 ;
NET "cpu_rnw" COLOR=6 ;
NET "cpu_Nres" COLOR=6 ;
NET "cpu_Nphi2" COLOR=6 ;
NET "cpu_Nirq" COLOR=6 ;
NET "cpu_d<7>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<6>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<5>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<4>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<3>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<2>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<1>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<0>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_a<1>" COLOR=6 IO_GROUP="cpu_a" ;
NET "cpu_a<0>" COLOR=6 IO_GROUP="cpu_a" ;
INST "spi_mosi_OBUFE" COLOR=7 ;
INST "cpu_Nirq_OBUFE" COLOR=8 ;

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#net "diag" loc="P29";
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "cpu_a<0>" LOC = "P22" ;
NET "cpu_a<1>" LOC = "P24" ;
NET "cpu_d<0>" LOC = "P2" ;
NET "cpu_d<1>" LOC = "P3" ;
NET "cpu_d<2>" LOC = "P4" ;
NET "cpu_d<3>" LOC = "P8" ;
NET "cpu_d<4>" LOC = "P9" ;
NET "cpu_d<5>" LOC = "P11" ;
NET "cpu_d<6>" LOC = "P12" ;
NET "cpu_d<7>" LOC = "P13" ;
NET "cpu_Nirq" LOC = "P14" ;
NET "cpu_Nphi2" LOC = "P5" ;
NET "cpu_Nres" LOC = "P19" ;
NET "cpu_rnw" LOC = "P7" ;
NET "cs1" LOC = "P20" ;
NET "diag" LOC = "P29" ;
NET "extclk" LOC = "P6" ;
NET "Ncs2" LOC = "P18" ;
NET "spi_int<0>" LOC = "P42" ;
NET "spi_int<1>" LOC = "P40" ;
NET "spi_int<2>" LOC = "P39" ;
NET "spi_int<3>" LOC = "P1" ;
NET "spi_miso<0>" LOC = "P44" ;
NET "spi_miso<1>" LOC = "P43" ;
NET "spi_miso<2>" LOC = "P38" ;
NET "spi_miso<3>" LOC = "P37" ;
NET "spi_mosi" LOC = "P35" ;
NET "spi_Nsel<0>" LOC = "P28" ;
NET "spi_Nsel<1>" LOC = "P27" ;
NET "spi_Nsel<2>" LOC = "P26" ;
NET "spi_Nsel<3>" LOC = "P25" ;
NET "spi_sclk" LOC = "P34" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

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----------------------------------------------------------------------------------
-- Company: n/a
-- Engineer: A. Fachat
--
-- Create Date: 12:37:11 05/07/2011
-- Design Name: SPI65B
-- Module Name: SPI6502B - Behavioral
-- Project Name: CS/A NETUSB 2.0
-- Target Devices: CS/A NETUSB 2.0
-- Tool versions:
-- Description: An SPI interface for 6502-based computers (or compatible).
-- modelled after the SPI65 interface by Daryl Rictor
-- (see http://sbc.rictor.org/io/65spi.html )
-- This implementation here, however, is a complete reimplementation
-- as the ABEL language of the original implementation is not supported
-- by ISE anymore.
-- Also I added the interrupt input handling, replacing four of the
-- original SPI select outputs with four interrupt inputs
-- Also folded out the single MISO input into one input for each of the
-- four supported devices, reducing external parts count again by one.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - removed spiclk and replaced with clksrc and clkcnt_is_zero combination,
-- to drive up SPI clock to half of input clock (and not one fourth only as before)
-- unfortunately that costed one divisor bit to fit into the CPLD
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SPI6502B is
Port ( cpu_d : inout STD_LOGIC_VECTOR (7 downto 0);
cpu_rnw : in STD_LOGIC;
cpu_Nirq : out STD_LOGIC;
cpu_Nres : in STD_LOGIC;
cpu_a : in STD_LOGIC_VECTOR (1 downto 0);
cpu_Nphi2 : in STD_LOGIC;
cs1 : in STD_LOGIC;
Ncs2 : in STD_LOGIC;
extclk : in STD_LOGIC;
spi_miso: in std_logic_vector (3 downto 0);
spi_mosi : out STD_LOGIC;
spi_sclk : out STD_LOGIC;
spi_Nsel : out STD_LOGIC_VECTOR (3 downto 0);
spi_int : in STD_LOGIC_VECTOR (3 downto 0);
diag : out std_logic
);
constant DIV_WIDTH : integer := 3;
end SPI6502B;
architecture Behavioral of SPI6502B is
-- interface signals
signal selected: std_logic;
signal reset: std_logic;
signal int_out: std_logic;
signal is_read: std_logic;
signal int_din: std_logic_vector (7 downto 0);
signal int_dout: std_logic_vector (7 downto 0);
signal int_mosi: std_logic;
signal int_miso: std_logic;
signal int_sclk: std_logic;
--------------------------
-- internal state
signal spidatain: std_logic_vector (7 downto 0);
signal spidataout: std_logic_vector (7 downto 0);
signal spiint: std_logic; -- spi interrupt state
-- spi register flags
signal tc: std_logic; -- transmission complete; cleared on spi data read
signal ier: std_logic; -- enable general SPI interrupts
signal bsy: std_logic; -- SPI busy
signal frx: std_logic; -- fast receive mode
signal tmo: std_logic; -- tri-state mosi
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
signal cpol: std_logic; -- shift clock polarity; 0=rising edge, 1=falling edge
signal cpha: std_logic; -- shift clock phase; 0=leading edge, 1=rising edge
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
signal slavesel: std_logic_vector(3 downto 0); -- slave select output (0=selected)
signal slaveinten: std_logic_vector(3 downto 0); -- slave interrupt enable (1=enabled)
signal slaveint: std_logic_vector (3 downto 0); -- slave interrupt inputs
--------------------------
-- helper signals
-- shift engine
signal start_shifting: std_logic; -- shifting data
signal shifting2: std_logic; -- shifting data
signal shiftdone: std_logic; -- shifting data done
signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)
-- spi clock
signal clksrc: std_logic; -- clock source (phi2 or extclk)
signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
signal shiftclk : std_logic;
begin
diag <= not (bsy or not slavesel(0)); --'0'; --shifting2; --shiftdone; --shiftcnt(2);
--------------------------
bsy <= start_shifting or shifting2;
process(start_shifting, shiftdone, shiftclk)
begin
if (rising_edge(shiftclk)) then
if (shiftdone = '1') then
shifting2 <= '0';
else
shifting2 <= start_shifting;
end if;
end if;
end process;
process(shiftcnt, reset, shiftclk)
begin
if (reset = '1') then
shiftdone <= '0';
elsif (rising_edge(shiftclk)) then
if (shiftcnt = "1111") then
shiftdone <= '1';
else
shiftdone <= '0';
end if;
end if;
end process;
process(reset, shifting2, shiftcnt, shiftclk)
begin
if (reset='1') then
shiftcnt <= (others => '0');
elsif (rising_edge(shiftclk)) then
if (shifting2 = '1') then
-- count phase
shiftcnt <= shiftcnt + 1;
else
shiftcnt <= (others => '0');
end if;
end if;
end process;
inproc: process(reset, shifting2,
shiftcnt, shiftclk, spidatain, int_miso)
begin
if (reset='1') then
spidatain <= (others => '0');
elsif (rising_edge(shiftclk)) then
if (shifting2 = '1' and shiftcnt(0) = '1') then
-- shift in to input register
spidatain (7 downto 1) <= spidatain (6 downto 0);
spidatain (0) <= int_miso;
end if;
end if;
end process;
outproc: process(reset, shifting2, spidataout, cpol, cpha,
shiftcnt, shiftclk)
begin
if (reset='1') then
int_mosi <= '1';
int_sclk <= cpol;
else
-- clock is sync'd
if (rising_edge(shiftclk)) then
if (shifting2='0' or shiftdone = '1') then
int_mosi <= '1';
int_sclk <= cpol;
else
-- output data directly from output register
case shiftcnt(3 downto 1) is
when "000" => int_mosi <= spidataout(7);
when "001" => int_mosi <= spidataout(6);
when "010" => int_mosi <= spidataout(5);
when "011" => int_mosi <= spidataout(4);
when "100" => int_mosi <= spidataout(3);
when "101" => int_mosi <= spidataout(2);
when "110" => int_mosi <= spidataout(1);
when "111" => int_mosi <= spidataout(0);
when others => int_mosi <= '1';
end case;
int_sclk <= cpol xor cpha xor shiftcnt(0);
end if;
end if;
end if;
end process;
-- shift operation enable
shiften: process(reset, selected, cpu_rnw, cpu_a, frx, shiftdone)
begin
-- start shifting
if (reset='1' or shiftdone='1') then
start_shifting <= '0';
elsif (falling_edge(selected) and cpu_a="00" and (frx='1' or cpu_rnw='0')) then
-- access to register 00, either write (cpu_rnw=0) or fast receive bit set (frx)
-- then both types of access (write but also read)
start_shifting <= '1';
end if;
end process;
--------------------------
-- spiclk - spi clock generation
-- spiclk is still 2 times the freq. than sclk
clksrc <= cpu_Nphi2 when (ece = '0') else extclk;
-- is a pulse signal to allow for divisor==0
--shiftclk <= clksrc when divcnt = "000000" else '0';
shiftclk <= clksrc when bsy = '1' else '0';
clkgen: process(reset, divisor, clksrc)
begin
if (reset='1') then
divcnt <= divisor;
--spiclk <= '0';
elsif (falling_edge(clksrc)) then
if (shiftclk = '1') then
divcnt <= divisor;
--spiclk <= not(spiclk);
else
divcnt <= divcnt - 1;
end if;
end if;
end process;
--------------------------
-- interrupt generation
int_out <= spiint
or (slaveint(0) and slaveinten(0))
or (slaveint(1) and slaveinten(1))
or (slaveint(2) and slaveinten(2))
or (slaveint(3) and slaveinten(3));
--------------------------
-- interface section
-- inputs
reset <= not (cpu_Nres);
selected <= cs1 and not(Ncs2); -- and cpu_phi2;
is_read <= selected and cpu_Nphi2 and cpu_rnw;
int_din <= cpu_d;
slaveint <= not(spi_int); -- active low interrupt inputs
int_miso <=
(spi_miso(0) and not(slavesel(0)))
or (spi_miso(1) and not(slavesel(1)))
or (spi_miso(2) and not(slavesel(2)))
or (spi_miso(3) and not(slavesel(3)));
-- outputs
cpu_d <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate
cpu_Nirq <= '0' when (int_out='1') else 'Z'; -- wired-or
spi_sclk <= int_sclk;
spi_mosi <= int_mosi when tmo='0' else 'Z'; -- mosi tri-state
spi_Nsel <= slavesel;
tc_proc: process (selected, shiftdone)
begin
if (shiftdone = '1') then
tc <= '1';
elsif (falling_edge(selected) and cpu_a="00"
--elsif (falling_edge(cpu_phi2) and selected='1' and cpu_a="00"
--and cpu_rnw='1' -- both reads _and_ writes clear the interrupt
) then
tc <= '0';
end if;
end process;
spiint <= tc and ier;
--------------------------
-- cpu register section
-- cpu read
cpu_read: process (is_read, cpu_a,
spidatain, tc, ier, bsy, frx, tmo, ece, cpol, cpha, divisor,
slavesel, slaveint, slaveinten)
begin
if (is_read = '1') then
case cpu_a is
when "00" => -- read SPI data in
int_dout <= spidatain;
when "01" => -- read status register
int_dout(0) <= cpha;
int_dout(1) <= cpol;
int_dout(2) <= ece;
int_dout(3) <= tmo;
int_dout(4) <= frx;
int_dout(5) <= bsy;
int_dout(6) <= ier;
int_dout(7) <= tc;
when "10" => -- read sclk divisor
int_dout(DIV_WIDTH-1 downto 0) <= divisor;
int_dout(3) <= '0';
int_dout(7 downto 4) <= slaveint;
when "11" => -- read slave select / slave interrupt state
int_dout(3 downto 0) <= slavesel;
int_dout(7 downto 4) <= slaveinten;
when others =>
int_dout <= (others => '0');
end case;
else
int_dout <= (others => '0');
end if;
end process;
-- cpu write
cpu_write: process(reset, selected, cpu_rnw, cpu_a, int_din)
begin
if (reset = '1') then
cpha <= '0';
cpol <= '0';
ece <= '0';
tmo <= '0';
frx <= '0';
ier <= '0';
slavesel <= (others => '1');
slaveinten <= (others => '0');
divisor <= (others => '0');
elsif (falling_edge(selected) and cpu_rnw = '0') then
--elsif (falling_edge(cpu_phi2) and selected='1' and cpu_rnw='0') then
case cpu_a is
when "00" => -- write SPI data out (see other process above)
spidataout <= int_din;
when "01" => -- write status register
cpha <= int_din(0);
cpol <= int_din(1);
ece <= int_din(2);
tmo <= int_din(3);
frx <= int_din(4);
-- no bit 5
ier <= int_din(6);
-- no bit 7;
when "10" => -- write divisor
divisor <= int_din(DIV_WIDTH-1 downto 0);
when "11" => -- write slave select / slave interrupt enable
slavesel <= int_din(3 downto 0);
slaveinten <= int_din(7 downto 4);
when others =>
end case;
end if;
end process;
end Behavioral;

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C:\sources\AppleIISd\spi6502b.ngc 1494084468
OK

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NET "cpu_Nphi2" loc="P5";
NET "extclk" loc="P6";
NET "cpu_rnw" loc="P7";
#net "diag" loc="P29";
NET "cpu_d<0>" loc="P2";
NET "cpu_d<1>" loc="P3";
NET "cpu_d<2>" loc="P4";
NET "cpu_d<3>" loc="P8";
NET "cpu_d<4>" loc="P9";
NET "cpu_d<5>" loc="P11";
NET "cpu_d<6>" loc="P12";
NET "cpu_d<7>" loc="P13";
NET "cpu_Nirq" loc="P14";
NET "Ncs2" loc="P18";
NET "cs1" loc="P20";
NET "cpu_Nres" loc="P19";
NET "cpu_a<0>" loc="P22";
NET "cpu_a<1>" loc="P24";
NET "spi_int<0>" loc="P42";
NET "spi_int<1>" loc="P40";
NET "spi_int<2>" loc="P39";
NET "spi_int<3>" loc="P1";
NET "spi_Nsel<0>" loc="P28";
NET "spi_Nsel<1>" loc="P27";
NET "spi_Nsel<2>" loc="P26";
NET "spi_Nsel<3>" loc="P25";
NET "spi_sclk" loc="P34";
NET "spi_mosi" loc="P35";
NET "spi_miso<0>" loc="P44";
NET "spi_miso<1>" loc="P43";
NET "spi_miso<2>" loc="P38";
NET "spi_miso<3>" loc="P37";

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JedecChain;
FileRevision(JESDxxA);
/* NoviceMode */
/* Active Mode BS */
/* Mode BS */
/* Cable PlatformCableUSB usb21 6000000 */
P ActionCode(Cfg)
Device
PartName(xc9572xl)
File("C:\sources\spi65\spi6502b.jed")
;
/* Mode SS */
/* Mode SM */
/* Mode BSFILE */
/* Mode HW140 */
ChainEnd;

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XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.2e
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spi65.npl Normal file
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JDF G
// Created by Project Navigator ver 1.0
PROJECT spi65
DESIGN spi65
DEVFAM xc9500xl
DEVFAMTIME 0
DEVICE xc9572xl
DEVICETIME 1468568184
DEVPKG PC44
DEVPKGTIME 1475334247
DEVSPEED -10
DEVSPEEDTIME 1469967516
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE SPI6502B1.1.vhd
DEPASSOC spi6502b SPI6502B.ucf
[STATUS-ALL]
spi6502b.ngcFile=WARNINGS,1494084467
[STRATEGY-LIST]
Normal=True

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spi6502b._hrpt Normal file
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Up-to-date

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spi6502b.bld Normal file
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Release - ngdbuild G.38
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -dd _ngo -uc SPI6502B.ucf -p xc9500xl spi6502b.ngc
spi6502b.ngd
Reading NGO file "C:/sources/AppleIISd/spi6502b.ngc" ...
Reading component libraries for design expansion...
Annotating constraints to design from file "SPI6502B.ucf" ...
Checking timing specifications ...
Checking expanded design ...
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 58840 kilobytes
Writing NGD file "spi6502b.ngd" ...
Writing NGDBUILD log file "spi6502b.bld"...

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spi6502b.gyd Normal file
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Pin Freeze File: version G.38
9572XL44PC XC9572XL-10-PC44
Ncs2 S:PIN18
cpu_Nphi2 S:PIN5
cpu_Nres S:PIN19
cpu_a<0> S:PIN22
cpu_a<1> S:PIN24
cpu_rnw S:PIN7
cs1 S:PIN20
extclk S:PIN6
spi_int<0> S:PIN42
spi_int<1> S:PIN40
spi_int<2> S:PIN39
spi_int<3> S:PIN1
spi_miso<0> S:PIN44
spi_miso<1> S:PIN43
spi_miso<2> S:PIN38
spi_miso<3> S:PIN37
cpu_Nirq S:PIN14
diag S:PIN29
cpu_d<0> S:PIN2
cpu_d<1> S:PIN3
cpu_d<2> S:PIN4
cpu_d<3> S:PIN8
cpu_d<4> S:PIN9
cpu_d<5> S:PIN11
cpu_d<6> S:PIN12
cpu_d<7> S:PIN13
spi_mosi S:PIN35
spi_sclk S:PIN34
spi_Nsel<0> S:PIN28
spi_Nsel<1> S:PIN27
spi_Nsel<2> S:PIN26
spi_Nsel<3> S:PIN25
;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.
PARTITION FB1_1 spidataout<3> spidataout<2> spidataout<1> spidataout<0>
int_dout<0> int_dout<1> tmo int_dout<2>
slaveinten<0> frx ece divisor<2>
divisor<1> divisor<0> int_dout<3> cpol
int_dout<4> cpha
PARTITION FB2_1 start_shifting/start_shifting_RSTF__$INT int_mosi EXP6_
PARTITION FB3_1 shifting2 int_dout<5> shiftdone $OpTx$INV$22__$INT
int_dout<6> start_shifting spidatain<7> int_dout<7>
cpu_Nirq_OBUFE spidatain<6> spidatain<5> spidatain<4>
spidatain<3> spidatain<2> spidatain<1> shiftcnt<3>
shiftcnt<2> cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
PARTITION FB4_1 tc slavesel<3> shiftcnt<0> spidataout<7>
slavesel<2> spidataout<6> spidataout<5> slavesel<1>
spidataout<4> shiftcnt<1> slavesel<0> slaveinten<3>
slaveinten<2> diag_OBUF slaveinten<1> ier
int_sclk spidatain<0>

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Up-to-date

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spi6502b.jed Normal file
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MDF Database: version 1.0
MDF_INFO | spi6502b | XC9572XL-10-PC44
MACROCELL | 1 | 1 | int_mosi
ATTRIBUTES | 8652706 | 0
INPUTS | 12 | shiftcnt<3> | shiftcnt<2> | shiftcnt<1> | shiftdone | spidataout<5> | shifting2 | spidataout<1> | start_shifting/start_shifting_RSTF__$INT.EXP | EXP6_.EXP | $OpTx$INV$22__$INT | cpu_Nres | tmo
INPUTMC | 11 | 2 | 15 | 2 | 16 | 3 | 9 | 2 | 2 | 3 | 6 | 2 | 0 | 0 | 2 | 1 | 0 | 1 | 2 | 2 | 3 | 0 | 6
INPUTP | 1 | 49
IMPORTS | 2 | 1 | 0 | 1 | 2
EQ | 21 |
!spi_mosi.D = shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<1> & shifting2
# !shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<5> & shifting2
;Imported pterms FB2_1
# shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<3> & shifting2
# !shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<7> & shifting2
;Imported pterms FB2_3
# shiftcnt<3> & shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<0> & shifting2
# shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<2> & shifting2
# !shiftcnt<3> & shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<4> & shifting2
# !shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<6> & shifting2;
spi_mosi.CLK = !$OpTx$INV$22__$INT;
spi_mosi.AP = !cpu_Nres;
spi_mosi.OE = !tmo;
MACROCELL | 3 | 10 | slavesel<0>
ATTRIBUTES | 4588514 | 0
OUTPUTMC | 4 | 3 | 10 | 3 | 0 | 0 | 4 | 3 | 13
INPUTS | 8 | spi_Nsel<0> | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 10
INPUTP | 7 | 59 | 52 | 12 | 50 | 46 | 49 | 24
EQ | 7 |
spi_Nsel<0>.T = spi_Nsel<0> & cpu_a<1> & cpu_a<0> &
!cpu_d<0>.PIN
# !spi_Nsel<0> & cpu_a<1> & cpu_a<0> &
cpu_d<0>.PIN;
!spi_Nsel<0>.CLK = cs1 & !Ncs2;
spi_Nsel<0>.AP = !cpu_Nres;
spi_Nsel<0>.CE = !cpu_rnw;
MACROCELL | 3 | 7 | slavesel<1>
ATTRIBUTES | 4588514 | 0
OUTPUTMC | 3 | 3 | 7 | 3 | 0 | 0 | 5
INPUTS | 8 | spi_Nsel<1> | cpu_a<1> | cpu_a<0> | cpu_d<1>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 7
INPUTP | 7 | 59 | 52 | 13 | 50 | 46 | 49 | 24
EQ | 7 |
spi_Nsel<1>.T = spi_Nsel<1> & cpu_a<1> & cpu_a<0> &
!cpu_d<1>.PIN
# !spi_Nsel<1> & cpu_a<1> & cpu_a<0> &
cpu_d<1>.PIN;
!spi_Nsel<1>.CLK = cs1 & !Ncs2;
spi_Nsel<1>.AP = !cpu_Nres;
spi_Nsel<1>.CE = !cpu_rnw;
MACROCELL | 3 | 4 | slavesel<2>
ATTRIBUTES | 4588514 | 0
OUTPUTMC | 3 | 3 | 4 | 3 | 17 | 0 | 7
INPUTS | 8 | spi_Nsel<2> | cpu_a<1> | cpu_a<0> | cpu_d<2>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 4
INPUTP | 7 | 59 | 52 | 15 | 50 | 46 | 49 | 24
EQ | 7 |
spi_Nsel<2>.T = spi_Nsel<2> & cpu_a<1> & cpu_a<0> &
!cpu_d<2>.PIN
# !spi_Nsel<2> & cpu_a<1> & cpu_a<0> &
cpu_d<2>.PIN;
!spi_Nsel<2>.CLK = cs1 & !Ncs2;
spi_Nsel<2>.AP = !cpu_Nres;
spi_Nsel<2>.CE = !cpu_rnw;
MACROCELL | 3 | 1 | slavesel<3>
ATTRIBUTES | 4588514 | 0
OUTPUTMC | 3 | 3 | 1 | 3 | 17 | 0 | 14
INPUTS | 8 | spi_Nsel<3> | cpu_a<1> | cpu_a<0> | cpu_d<3>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 1
INPUTP | 7 | 59 | 52 | 26 | 50 | 46 | 49 | 24
EQ | 7 |
spi_Nsel<3>.T = spi_Nsel<3> & cpu_a<1> & cpu_a<0> &
!cpu_d<3>.PIN
# !spi_Nsel<3> & cpu_a<1> & cpu_a<0> &
cpu_d<3>.PIN;
!spi_Nsel<3>.CLK = cs1 & !Ncs2;
spi_Nsel<3>.AP = !cpu_Nres;
spi_Nsel<3>.CE = !cpu_rnw;
MACROCELL | 0 | 15 | cpol
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 0 | 15 | 3 | 16 | 0 | 5
INPUTS | 8 | cpol | cpu_a<1> | cpu_a<0> | cpu_d<1>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 15
INPUTP | 7 | 59 | 52 | 13 | 50 | 46 | 49 | 24
EQ | 5 |
cpol.T = cpol & !cpu_a<1> & cpu_a<0> & !cpu_d<1>.PIN
# !cpol & !cpu_a<1> & cpu_a<0> & cpu_d<1>.PIN;
!cpol.CLK = cs1 & !Ncs2;
cpol.AR = !cpu_Nres;
cpol.CE = !cpu_rnw;
MACROCELL | 0 | 10 | ece
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 0 | 10 | 0 | 7 | 2 | 3
INPUTS | 8 | ece | cpu_a<1> | cpu_a<0> | cpu_d<2>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 10
INPUTP | 7 | 59 | 52 | 15 | 50 | 46 | 49 | 24
EQ | 5 |
ece.T = ece & !cpu_a<1> & cpu_a<0> & !cpu_d<2>.PIN
# !ece & !cpu_a<1> & cpu_a<0> & cpu_d<2>.PIN;
!ece.CLK = cs1 & !Ncs2;
ece.AR = !cpu_Nres;
ece.CE = !cpu_rnw;
MACROCELL | 0 | 17 | cpha
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 4 | 0 | 17 | 3 | 16 | 0 | 4 | 3 | 15
INPUTS | 8 | cpha | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 17
INPUTP | 7 | 59 | 52 | 12 | 50 | 46 | 49 | 24
EQ | 5 |
cpha.T = cpha & !cpu_a<1> & cpu_a<0> & !cpu_d<0>.PIN
# !cpha & !cpu_a<1> & cpu_a<0> & cpu_d<0>.PIN;
!cpha.CLK = cs1 & !Ncs2;
cpha.AR = !cpu_Nres;
cpha.CE = !cpu_rnw;
MACROCELL | 0 | 9 | frx
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 0 | 9 | 2 | 5 | 0 | 16
INPUTS | 8 | frx | cpu_a<1> | cpu_a<0> | cpu_d<4>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 9
INPUTP | 7 | 59 | 52 | 27 | 50 | 46 | 49 | 24
EQ | 5 |
frx.T = frx & !cpu_a<1> & cpu_a<0> & !cpu_d<4>.PIN
# !frx & !cpu_a<1> & cpu_a<0> & cpu_d<4>.PIN;
!frx.CLK = cs1 & !Ncs2;
frx.AR = !cpu_Nres;
frx.CE = !cpu_rnw;
MACROCELL | 3 | 15 | ier
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 5 | 3 | 15 | 2 | 4 | 2 | 17 | 3 | 14 | 3 | 16
INPUTS | 13 | ier | cpu_a<1> | cpu_a<0> | cpu_d<6>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw | cpha | shiftcnt<0> | shiftdone | shifting2 | slaveinten<1>.EXP
INPUTMC | 6 | 3 | 15 | 0 | 17 | 3 | 2 | 2 | 2 | 2 | 0 | 3 | 14
INPUTP | 7 | 59 | 52 | 31 | 50 | 46 | 49 | 24
EXPORTS | 1 | 3 | 16
IMPORTS | 1 | 3 | 14
EQ | 8 |
ier.T = !ier & !cpu_a<1> & cpu_a<0> & cpu_d<6>.PIN
;Imported pterms FB4_15
# ier & !cpu_a<1> & cpu_a<0> & !cpu_d<6>.PIN;
!ier.CLK = cs1 & !Ncs2;
ier.AR = !cpu_Nres;
ier.CE = !cpu_rnw;
ier.EXP = cpu_Nres & cpha & !shiftcnt<0> & !shiftdone &
shifting2
MACROCELL | 0 | 8 | slaveinten<0>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 0 | 8 | 0 | 16 | 2 | 17
INPUTS | 8 | slaveinten<0> | cpu_a<1> | cpu_a<0> | cpu_d<4>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 8
INPUTP | 7 | 59 | 52 | 27 | 50 | 46 | 49 | 24
EQ | 7 |
slaveinten<0>.T = slaveinten<0> & cpu_a<1> & cpu_a<0> &
!cpu_d<4>.PIN
# !slaveinten<0> & cpu_a<1> & cpu_a<0> &
cpu_d<4>.PIN;
!slaveinten<0>.CLK = cs1 & !Ncs2;
slaveinten<0>.AR = !cpu_Nres;
slaveinten<0>.CE = !cpu_rnw;
MACROCELL | 3 | 14 | slaveinten<1>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 5 | 3 | 14 | 2 | 1 | 2 | 17 | 3 | 13 | 3 | 15
INPUTS | 11 | slaveinten<1> | cpu_a<1> | cpu_a<0> | cpu_d<5>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw | ier | cpu_d<6>.PIN | diag_OBUF.EXP
INPUTMC | 3 | 3 | 14 | 3 | 15 | 3 | 13
INPUTP | 8 | 59 | 52 | 29 | 50 | 46 | 49 | 24 | 31
EXPORTS | 1 | 3 | 15
IMPORTS | 1 | 3 | 13
EQ | 9 |
slaveinten<1>.T = !slaveinten<1> & cpu_a<1> & cpu_a<0> &
cpu_d<5>.PIN
;Imported pterms FB4_14
# slaveinten<1> & cpu_a<1> & cpu_a<0> &
!cpu_d<5>.PIN;
!slaveinten<1>.CLK = cs1 & !Ncs2;
slaveinten<1>.AR = !cpu_Nres;
slaveinten<1>.CE = !cpu_rnw;
slaveinten<1>.EXP = ier & !cpu_a<1> & cpu_a<0> & !cpu_d<6>.PIN
MACROCELL | 3 | 12 | slaveinten<2>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 3 | 12 | 2 | 4 | 2 | 17
INPUTS | 8 | slaveinten<2> | cpu_a<1> | cpu_a<0> | cpu_d<6>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 12
INPUTP | 7 | 59 | 52 | 31 | 50 | 46 | 49 | 24
EQ | 7 |
slaveinten<2>.T = slaveinten<2> & cpu_a<1> & cpu_a<0> &
!cpu_d<6>.PIN
# !slaveinten<2> & cpu_a<1> & cpu_a<0> &
cpu_d<6>.PIN;
!slaveinten<2>.CLK = cs1 & !Ncs2;
slaveinten<2>.AR = !cpu_Nres;
slaveinten<2>.CE = !cpu_rnw;
MACROCELL | 3 | 11 | slaveinten<3>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 3 | 11 | 2 | 7 | 2 | 17
INPUTS | 8 | slaveinten<3> | cpu_a<1> | cpu_a<0> | cpu_d<7>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 11
INPUTP | 7 | 59 | 52 | 33 | 50 | 46 | 49 | 24
EQ | 7 |
slaveinten<3>.T = slaveinten<3> & cpu_a<1> & cpu_a<0> &
!cpu_d<7>.PIN
# !slaveinten<3> & cpu_a<1> & cpu_a<0> &
cpu_d<7>.PIN;
!slaveinten<3>.CLK = cs1 & !Ncs2;
slaveinten<3>.AR = !cpu_Nres;
slaveinten<3>.CE = !cpu_rnw;
MACROCELL | 0 | 6 | tmo
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 1 | 1 | 0 | 6 | 0 | 14
INPUTS | 8 | tmo | cpu_a<1> | cpu_a<0> | cpu_d<3>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 6
INPUTP | 7 | 59 | 52 | 26 | 50 | 46 | 49 | 24
EQ | 5 |
tmo.T = tmo & !cpu_a<1> & cpu_a<0> & !cpu_d<3>.PIN
# !tmo & !cpu_a<1> & cpu_a<0> & cpu_d<3>.PIN;
!tmo.CLK = cs1 & !Ncs2;
tmo.AR = !cpu_Nres;
tmo.CE = !cpu_rnw;
MACROCELL | 0 | 13 | divisor<0>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 2 | 0 | 13 | 0 | 4
INPUTS | 8 | divisor<0> | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 13
INPUTP | 7 | 59 | 52 | 12 | 50 | 46 | 49 | 24
EQ | 5 |
divisor<0>.T = divisor<0> & cpu_a<1> & !cpu_a<0> & !cpu_d<0>.PIN
# !divisor<0> & cpu_a<1> & !cpu_a<0> & cpu_d<0>.PIN;
!divisor<0>.CLK = cs1 & !Ncs2;
divisor<0>.AR = !cpu_Nres;
divisor<0>.CE = !cpu_rnw;
MACROCELL | 0 | 12 | divisor<1>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 2 | 0 | 12 | 0 | 5
INPUTS | 8 | divisor<1> | cpu_a<1> | cpu_a<0> | cpu_d<1>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 12
INPUTP | 7 | 59 | 52 | 13 | 50 | 46 | 49 | 24
EQ | 5 |
divisor<1>.T = divisor<1> & cpu_a<1> & !cpu_a<0> & !cpu_d<1>.PIN
# !divisor<1> & cpu_a<1> & !cpu_a<0> & cpu_d<1>.PIN;
!divisor<1>.CLK = cs1 & !Ncs2;
divisor<1>.AR = !cpu_Nres;
divisor<1>.CE = !cpu_rnw;
MACROCELL | 0 | 11 | divisor<2>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 2 | 0 | 11 | 0 | 7
INPUTS | 8 | divisor<2> | cpu_a<1> | cpu_a<0> | cpu_d<2>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 11
INPUTP | 7 | 59 | 52 | 15 | 50 | 46 | 49 | 24
EQ | 5 |
divisor<2>.T = divisor<2> & cpu_a<1> & !cpu_a<0> & !cpu_d<2>.PIN
# !divisor<2> & cpu_a<1> & !cpu_a<0> & cpu_d<2>.PIN;
!divisor<2>.CLK = cs1 & !Ncs2;
divisor<2>.AR = !cpu_Nres;
divisor<2>.CE = !cpu_rnw;
MACROCELL | 3 | 17 | spidatain<0>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 2 | 14 | 0 | 4
INPUTS | 9 | spi_Nsel<3> | spi_miso<3> | spi_Nsel<2> | spi_miso<2> | tc.EXP | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 6 | 3 | 1 | 3 | 4 | 3 | 0 | 2 | 3 | 3 | 2 | 2 | 0
INPUTP | 3 | 89 | 90 | 49
IMPORTS | 1 | 3 | 0
EQ | 8 |
spidatain<0>.D = !spi_Nsel<2> & spi_miso<2>
# !spi_Nsel<3> & spi_miso<3>
;Imported pterms FB4_1
# !spi_Nsel<0> & spi_miso<0>
# !spi_Nsel<1> & spi_miso<1>;
spidatain<0>.CLK = !$OpTx$INV$22__$INT;
spidatain<0>.AR = !cpu_Nres;
spidatain<0>.CE = shiftcnt<0> & shifting2;
MACROCELL | 2 | 14 | spidatain<1>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 2 | 13 | 0 | 5
INPUTS | 5 | spidatain<0> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 3 | 17 | 2 | 3 | 3 | 2 | 2 | 0
INPUTP | 1 | 49
EQ | 4 |
spidatain<1>.D = spidatain<0>;
spidatain<1>.CLK = !$OpTx$INV$22__$INT;
spidatain<1>.AR = !cpu_Nres;
spidatain<1>.CE = shiftcnt<0> & shifting2;
MACROCELL | 2 | 13 | spidatain<2>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 2 | 12 | 0 | 7
INPUTS | 5 | spidatain<1> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 2 | 14 | 2 | 3 | 3 | 2 | 2 | 0
INPUTP | 1 | 49
EQ | 4 |
spidatain<2>.D = spidatain<1>;
spidatain<2>.CLK = !$OpTx$INV$22__$INT;
spidatain<2>.AR = !cpu_Nres;
spidatain<2>.CE = shiftcnt<0> & shifting2;
MACROCELL | 2 | 12 | spidatain<3>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 2 | 11 | 0 | 14
INPUTS | 5 | spidatain<2> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 2 | 13 | 2 | 3 | 3 | 2 | 2 | 0
INPUTP | 1 | 49
EQ | 4 |
spidatain<3>.D = spidatain<2>;
spidatain<3>.CLK = !$OpTx$INV$22__$INT;
spidatain<3>.AR = !cpu_Nres;
spidatain<3>.CE = shiftcnt<0> & shifting2;
MACROCELL | 2 | 11 | spidatain<4>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 2 | 10 | 0 | 16
INPUTS | 5 | spidatain<3> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 2 | 12 | 2 | 3 | 3 | 2 | 2 | 0
INPUTP | 1 | 49
EQ | 4 |
spidatain<4>.D = spidatain<3>;
spidatain<4>.CLK = !$OpTx$INV$22__$INT;
spidatain<4>.AR = !cpu_Nres;
spidatain<4>.CE = shiftcnt<0> & shifting2;
MACROCELL | 2 | 10 | spidatain<5>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 2 | 9 | 2 | 1
INPUTS | 5 | spidatain<4> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 2 | 11 | 2 | 3 | 3 | 2 | 2 | 0
INPUTP | 1 | 49
EQ | 4 |
spidatain<5>.D = spidatain<4>;
spidatain<5>.CLK = !$OpTx$INV$22__$INT;
spidatain<5>.AR = !cpu_Nres;
spidatain<5>.CE = shiftcnt<0> & shifting2;
MACROCELL | 2 | 9 | spidatain<6>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 2 | 6 | 2 | 4
INPUTS | 5 | spidatain<5> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 2 | 10 | 2 | 3 | 3 | 2 | 2 | 0
INPUTP | 1 | 49
EQ | 4 |
spidatain<6>.D = spidatain<5>;
spidatain<6>.CLK = !$OpTx$INV$22__$INT;
spidatain<6>.AR = !cpu_Nres;
spidatain<6>.CE = shiftcnt<0> & shifting2;
MACROCELL | 2 | 6 | spidatain<7>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 1 | 2 | 7
INPUTS | 5 | spidatain<6> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 2 | 9 | 2 | 3 | 3 | 2 | 2 | 0
INPUTP | 1 | 49
EQ | 4 |
spidatain<7>.D = spidatain<6>;
spidatain<7>.CLK = !$OpTx$INV$22__$INT;
spidatain<7>.AR = !cpu_Nres;
spidatain<7>.CE = shiftcnt<0> & shifting2;
MACROCELL | 3 | 16 | int_sclk
ATTRIBUTES | 8651698 | 0
INPUTS | 8 | cpol | cpu_Nres | cpha | shiftcnt<0> | shiftdone | shifting2 | $OpTx$INV$22__$INT | ier.EXP
INPUTMC | 7 | 0 | 15 | 0 | 17 | 3 | 2 | 2 | 2 | 2 | 0 | 2 | 3 | 3 | 15
INPUTP | 1 | 49
IMPORTS | 1 | 3 | 15
EQ | 9 |
spi_sclk.D = cpol
$ cpu_Nres & !cpha & shiftcnt<0> & !shiftdone &
shifting2
;Imported pterms FB4_16
# cpu_Nres & cpha & !shiftcnt<0> & !shiftdone &
shifting2;
spi_sclk.CLK = !$OpTx$INV$22__$INT;
spi_sclk.AP = !cpu_Nres & cpol;
spi_sclk.AR = !cpu_Nres & !cpol;
MACROCELL | 2 | 15 | shiftcnt<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 5 | 1 | 1 | 2 | 15 | 2 | 2 | 1 | 0 | 1 | 2
INPUTS | 7 | shiftcnt<2> | shiftcnt<0> | shiftcnt<1> | shifting2 | shiftcnt<3> | $OpTx$INV$22__$INT | cpu_Nres
INPUTMC | 6 | 2 | 16 | 3 | 2 | 3 | 9 | 2 | 0 | 2 | 15 | 2 | 3
INPUTP | 1 | 49
EQ | 5 |
shiftcnt<3>.T = shiftcnt<3> & !shifting2
# shiftcnt<2> & shiftcnt<0> & shiftcnt<1> &
shifting2;
shiftcnt<3>.CLK = !$OpTx$INV$22__$INT;
shiftcnt<3>.AR = !cpu_Nres;
MACROCELL | 2 | 16 | shiftcnt<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 6 | 1 | 1 | 2 | 15 | 2 | 16 | 2 | 2 | 1 | 0 | 1 | 2
INPUTS | 6 | shiftcnt<0> | shiftcnt<1> | shifting2 | shiftcnt<2> | $OpTx$INV$22__$INT | cpu_Nres
INPUTMC | 5 | 3 | 2 | 3 | 9 | 2 | 0 | 2 | 16 | 2 | 3
INPUTP | 1 | 49
EQ | 4 |
shiftcnt<2>.T = shiftcnt<2> & !shifting2
# shiftcnt<0> & shiftcnt<1> & shifting2;
shiftcnt<2>.CLK = !$OpTx$INV$22__$INT;
shiftcnt<2>.AR = !cpu_Nres;
MACROCELL | 3 | 2 | shiftcnt<0>
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 15 | 3 | 17 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 2 | 9 | 2 | 6 | 3 | 16 | 2 | 15 | 2 | 16 | 3 | 2 | 3 | 9 | 2 | 2 | 3 | 15
INPUTS | 4 | shiftcnt<0> | shifting2 | $OpTx$INV$22__$INT | cpu_Nres
INPUTMC | 3 | 3 | 2 | 2 | 0 | 2 | 3
INPUTP | 1 | 49
EQ | 3 |
shiftcnt<0>.D = !shiftcnt<0> & shifting2;
shiftcnt<0>.CLK = !$OpTx$INV$22__$INT;
shiftcnt<0>.AR = !cpu_Nres;
MACROCELL | 3 | 9 | shiftcnt<1>
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 7 | 1 | 1 | 2 | 15 | 2 | 16 | 3 | 9 | 2 | 2 | 1 | 0 | 1 | 2
INPUTS | 5 | shiftcnt<0> | shiftcnt<1> | shifting2 | $OpTx$INV$22__$INT | cpu_Nres
INPUTMC | 4 | 3 | 2 | 3 | 9 | 2 | 0 | 2 | 3
INPUTP | 1 | 49
EQ | 4 |
shiftcnt<1>.D = shiftcnt<0> & !shiftcnt<1> & shifting2
# !shiftcnt<0> & shiftcnt<1> & shifting2;
shiftcnt<1>.CLK = !$OpTx$INV$22__$INT;
shiftcnt<1>.AR = !cpu_Nres;
MACROCELL | 2 | 2 | shiftdone
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 7 | 1 | 1 | 3 | 16 | 3 | 0 | 2 | 0 | 1 | 0 | 1 | 2 | 3 | 15
INPUTS | 6 | shiftcnt<3> | shiftcnt<2> | shiftcnt<0> | shiftcnt<1> | $OpTx$INV$22__$INT | cpu_Nres
INPUTMC | 5 | 2 | 15 | 2 | 16 | 3 | 2 | 3 | 9 | 2 | 3
INPUTP | 1 | 49
EQ | 4 |
shiftdone.D = shiftcnt<3> & shiftcnt<2> & shiftcnt<0> &
shiftcnt<1>;
shiftdone.CLK = !$OpTx$INV$22__$INT;
shiftdone.AR = !cpu_Nres;
MACROCELL | 2 | 5 | start_shifting
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 5 | 2 | 5 | 2 | 1 | 2 | 0 | 3 | 13 | 2 | 3
INPUTS | 8 | frx | start_shifting | cpu_a<1> | cpu_a<0> | cpu_rnw | cs1 | Ncs2 | start_shifting/start_shifting_RSTF__$INT
INPUTMC | 3 | 0 | 9 | 2 | 5 | 1 | 0
INPUTP | 5 | 59 | 52 | 24 | 50 | 46
EQ | 4 |
start_shifting.T = !cpu_rnw & !start_shifting & !cpu_a<1> & !cpu_a<0>
# frx & !start_shifting & !cpu_a<1> & !cpu_a<0>;
!start_shifting.CLK = cs1 & !Ncs2;
start_shifting.AR = !start_shifting/start_shifting_RSTF__$INT;
MACROCELL | 3 | 0 | tc
ATTRIBUTES | 8520672 | 0
OUTPUTMC | 3 | 2 | 7 | 2 | 17 | 3 | 17
INPUTS | 9 | cs1 | Ncs2 | shiftdone | cpu_a<1> | cpu_a<0> | spi_Nsel<0> | spi_miso<0> | spi_Nsel<1> | spi_miso<1>
INPUTMC | 3 | 2 | 2 | 3 | 10 | 3 | 7
INPUTP | 6 | 50 | 46 | 59 | 52 | 10 | 9
EXPORTS | 1 | 3 | 17
EQ | 6 |
tc.D = Gnd;
!tc.CLK = cs1 & !Ncs2;
tc.AP = shiftdone;
tc.CE = !cpu_a<1> & !cpu_a<0>;
tc.EXP = !spi_Nsel<0> & spi_miso<0>
# !spi_Nsel<1> & spi_miso<1>
MACROCELL | 0 | 3 | spidataout<0>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 0 | 3 | 1 | 2
INPUTS | 8 | spidataout<0> | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 3
INPUTP | 7 | 59 | 52 | 12 | 50 | 46 | 49 | 24
EQ | 6 |
spidataout<0>.T = spidataout<0> & !cpu_a<1> & !cpu_a<0> &
!cpu_d<0>.PIN
# !spidataout<0> & !cpu_a<1> & !cpu_a<0> &
cpu_d<0>.PIN;
!spidataout<0>.CLK = cs1 & !Ncs2;
spidataout<0>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 0 | 2 | spidataout<1>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 1 | 1 | 0 | 2
INPUTS | 8 | spidataout<1> | cpu_a<1> | cpu_a<0> | cpu_d<1>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 2
INPUTP | 7 | 59 | 52 | 13 | 50 | 46 | 49 | 24
EQ | 6 |
spidataout<1>.T = spidataout<1> & !cpu_a<1> & !cpu_a<0> &
!cpu_d<1>.PIN
# !spidataout<1> & !cpu_a<1> & !cpu_a<0> &
cpu_d<1>.PIN;
!spidataout<1>.CLK = cs1 & !Ncs2;
spidataout<1>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 0 | 1 | spidataout<2>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 0 | 1 | 1 | 2
INPUTS | 8 | spidataout<2> | cpu_a<1> | cpu_a<0> | cpu_d<2>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 1
INPUTP | 7 | 59 | 52 | 15 | 50 | 46 | 49 | 24
EQ | 6 |
spidataout<2>.T = spidataout<2> & !cpu_a<1> & !cpu_a<0> &
!cpu_d<2>.PIN
# !spidataout<2> & !cpu_a<1> & !cpu_a<0> &
cpu_d<2>.PIN;
!spidataout<2>.CLK = cs1 & !Ncs2;
spidataout<2>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 0 | 0 | spidataout<3>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 1 | 0 | 0 | 0
INPUTS | 8 | spidataout<3> | cpu_a<1> | cpu_a<0> | cpu_d<3>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 0
INPUTP | 7 | 59 | 52 | 26 | 50 | 46 | 49 | 24
EQ | 6 |
spidataout<3>.T = spidataout<3> & !cpu_a<1> & !cpu_a<0> &
!cpu_d<3>.PIN
# !spidataout<3> & !cpu_a<1> & !cpu_a<0> &
cpu_d<3>.PIN;
!spidataout<3>.CLK = cs1 & !Ncs2;
spidataout<3>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 3 | 8 | spidataout<4>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 3 | 8 | 1 | 2
INPUTS | 8 | spidataout<4> | cpu_a<1> | cpu_a<0> | cpu_d<4>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 8
INPUTP | 7 | 59 | 52 | 27 | 50 | 46 | 49 | 24
EQ | 6 |
spidataout<4>.T = spidataout<4> & !cpu_a<1> & !cpu_a<0> &
!cpu_d<4>.PIN
# !spidataout<4> & !cpu_a<1> & !cpu_a<0> &
cpu_d<4>.PIN;
!spidataout<4>.CLK = cs1 & !Ncs2;
spidataout<4>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 3 | 6 | spidataout<5>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 1 | 1 | 3 | 6
INPUTS | 8 | spidataout<5> | cpu_a<1> | cpu_a<0> | cpu_d<5>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 6
INPUTP | 7 | 59 | 52 | 29 | 50 | 46 | 49 | 24
EQ | 6 |
spidataout<5>.T = spidataout<5> & !cpu_a<1> & !cpu_a<0> &
!cpu_d<5>.PIN
# !spidataout<5> & !cpu_a<1> & !cpu_a<0> &
cpu_d<5>.PIN;
!spidataout<5>.CLK = cs1 & !Ncs2;
spidataout<5>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 3 | 5 | spidataout<6>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 3 | 5 | 1 | 2
INPUTS | 8 | spidataout<6> | cpu_a<1> | cpu_a<0> | cpu_d<6>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 5
INPUTP | 7 | 59 | 52 | 31 | 50 | 46 | 49 | 24
EQ | 6 |
spidataout<6>.T = spidataout<6> & !cpu_a<1> & !cpu_a<0> &
!cpu_d<6>.PIN
# !spidataout<6> & !cpu_a<1> & !cpu_a<0> &
cpu_d<6>.PIN;
!spidataout<6>.CLK = cs1 & !Ncs2;
spidataout<6>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 3 | 3 | spidataout<7>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 1 | 0 | 3 | 3
INPUTS | 8 | spidataout<7> | cpu_a<1> | cpu_a<0> | cpu_d<7>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 3
INPUTP | 7 | 59 | 52 | 33 | 50 | 46 | 49 | 24
EQ | 6 |
spidataout<7>.T = spidataout<7> & !cpu_a<1> & !cpu_a<0> &
!cpu_d<7>.PIN
# !spidataout<7> & !cpu_a<1> & !cpu_a<0> &
cpu_d<7>.PIN;
!spidataout<7>.CLK = cs1 & !Ncs2;
spidataout<7>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 0 | 4 | int_dout<0>
ATTRIBUTES | 265986 | 0
INPUTS | 10 | cpu_rnw | spidatain<0> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | divisor<0> | cpha | spi_Nsel<0>
INPUTMC | 4 | 3 | 17 | 0 | 13 | 0 | 17 | 3 | 10
INPUTP | 6 | 24 | 59 | 52 | 50 | 46 | 20
EQ | 9 |
cpu_d<0> = cpu_rnw & spi_Nsel<0> & cpu_a<1> & cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & cpha & !cpu_a<1> & cpu_a<0> & cs1 &
!Ncs2 & cpu_Nphi2
# cpu_rnw & divisor<0> & cpu_a<1> & !cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & spidatain<0> & !cpu_a<1> & !cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2;
cpu_d<0>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
MACROCELL | 0 | 5 | int_dout<1>
ATTRIBUTES | 265986 | 0
INPUTS | 10 | cpu_rnw | spidatain<1> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | divisor<1> | cpol | spi_Nsel<1>
INPUTMC | 4 | 2 | 14 | 0 | 12 | 0 | 15 | 3 | 7
INPUTP | 6 | 24 | 59 | 52 | 50 | 46 | 20
EQ | 9 |
cpu_d<1> = cpu_rnw & spi_Nsel<1> & cpu_a<1> & cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & cpol & !cpu_a<1> & cpu_a<0> & cs1 &
!Ncs2 & cpu_Nphi2
# cpu_rnw & divisor<1> & cpu_a<1> & !cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & spidatain<1> & !cpu_a<1> & !cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2;
cpu_d<1>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
MACROCELL | 0 | 7 | int_dout<2>
ATTRIBUTES | 265986 | 0
INPUTS | 10 | cpu_rnw | spidatain<2> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | divisor<2> | ece | spi_Nsel<2>
INPUTMC | 4 | 2 | 13 | 0 | 11 | 0 | 10 | 3 | 4
INPUTP | 6 | 24 | 59 | 52 | 50 | 46 | 20
EQ | 9 |
cpu_d<2> = cpu_rnw & spi_Nsel<2> & cpu_a<1> & cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & ece & !cpu_a<1> & cpu_a<0> & cs1 &
!Ncs2 & cpu_Nphi2
# cpu_rnw & divisor<2> & cpu_a<1> & !cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & spidatain<2> & !cpu_a<1> & !cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2;
cpu_d<2>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
MACROCELL | 0 | 14 | int_dout<3>
ATTRIBUTES | 265986 | 0
INPUTS | 9 | cpu_rnw | spidatain<3> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | tmo | spi_Nsel<3>
INPUTMC | 3 | 2 | 12 | 0 | 6 | 3 | 1
INPUTP | 6 | 24 | 59 | 52 | 50 | 46 | 20
EQ | 7 |
cpu_d<3> = cpu_rnw & spi_Nsel<3> & cpu_a<1> & cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & tmo & !cpu_a<1> & cpu_a<0> & cs1 &
!Ncs2 & cpu_Nphi2
# cpu_rnw & spidatain<3> & !cpu_a<1> & !cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2;
cpu_d<3>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
MACROCELL | 0 | 16 | int_dout<4>
ATTRIBUTES | 265986 | 0
INPUTS | 10 | cpu_rnw | spidatain<4> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | spi_int<0> | frx | slaveinten<0>
INPUTMC | 3 | 2 | 11 | 0 | 9 | 0 | 8
INPUTP | 7 | 24 | 59 | 52 | 50 | 46 | 20 | 7
EQ | 9 |
cpu_d<4> = cpu_rnw & frx & !cpu_a<1> & cpu_a<0> & cs1 &
!Ncs2 & cpu_Nphi2
# cpu_rnw & slaveinten<0> & cpu_a<1> & cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & spidatain<4> & !cpu_a<1> & !cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & cpu_a<1> & !cpu_a<0> & cs1 & !Ncs2 &
!spi_int<0> & cpu_Nphi2;
cpu_d<4>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
MACROCELL | 2 | 1 | int_dout<5>
ATTRIBUTES | 265986 | 0
INPUTS | 11 | cpu_rnw | start_shifting | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | shifting2 | slaveinten<1> | spidatain<5> | shifting2.EXP
INPUTMC | 5 | 2 | 5 | 2 | 0 | 3 | 14 | 2 | 10 | 2 | 0
INPUTP | 6 | 24 | 59 | 52 | 50 | 46 | 20
IMPORTS | 1 | 2 | 0
EQ | 12 |
cpu_d<5> = cpu_rnw & slaveinten<1> & cpu_a<1> & cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & spidatain<5> & !cpu_a<1> & !cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & start_shifting & !cpu_a<1> & cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & !cpu_a<1> & cpu_a<0> & cs1 & !Ncs2 &
shifting2 & cpu_Nphi2
;Imported pterms FB3_1
# cpu_rnw & cpu_a<1> & !cpu_a<0> & cs1 & !Ncs2 &
!spi_int<1> & cpu_Nphi2;
cpu_d<5>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
MACROCELL | 2 | 4 | int_dout<6>
ATTRIBUTES | 265986 | 0
INPUTS | 10 | cpu_rnw | spidatain<6> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | spi_int<2> | ier | slaveinten<2>
INPUTMC | 3 | 2 | 9 | 3 | 15 | 3 | 12
INPUTP | 7 | 24 | 59 | 52 | 50 | 46 | 20 | 92
EQ | 9 |
cpu_d<6> = cpu_rnw & ier & !cpu_a<1> & cpu_a<0> & cs1 &
!Ncs2 & cpu_Nphi2
# cpu_rnw & slaveinten<2> & cpu_a<1> & cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & spidatain<6> & !cpu_a<1> & !cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & cpu_a<1> & !cpu_a<0> & cs1 & !Ncs2 &
!spi_int<2> & cpu_Nphi2;
cpu_d<6>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
MACROCELL | 2 | 7 | int_dout<7>
ATTRIBUTES | 265986 | 0
INPUTS | 10 | cpu_rnw | spidatain<7> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | spi_int<3> | tc | slaveinten<3>
INPUTMC | 3 | 2 | 6 | 3 | 0 | 3 | 11
INPUTP | 7 | 24 | 59 | 52 | 50 | 46 | 20 | 11
EQ | 9 |
cpu_d<7> = cpu_rnw & slaveinten<3> & cpu_a<1> & cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & spidatain<7> & !cpu_a<1> & !cpu_a<0> &
cs1 & !Ncs2 & cpu_Nphi2
# cpu_rnw & tc & !cpu_a<1> & cpu_a<0> & cs1 &
!Ncs2 & cpu_Nphi2
# cpu_rnw & cpu_a<1> & !cpu_a<0> & cs1 & !Ncs2 &
!spi_int<3> & cpu_Nphi2;
cpu_d<7>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2;
MACROCELL | 2 | 0 | shifting2
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 20 | 1 | 1 | 3 | 17 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 2 | 9 | 2 | 6 | 3 | 16 | 2 | 15 | 2 | 16 | 3 | 2 | 3 | 9 | 2 | 1 | 3 | 13 | 2 | 3 | 1 | 0 | 1 | 2 | 3 | 15
INPUTS | 10 | shiftdone | start_shifting | $OpTx$INV$22__$INT | cpu_rnw | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | spi_int<1> | cpu_Nphi2
INPUTMC | 3 | 2 | 2 | 2 | 5 | 2 | 3
INPUTP | 7 | 24 | 59 | 52 | 50 | 46 | 3 | 20
EXPORTS | 1 | 2 | 1
EQ | 4 |
shifting2.D = !shiftdone & start_shifting;
shifting2.CLK = !$OpTx$INV$22__$INT;
shifting2.EXP = cpu_rnw & cpu_a<1> & !cpu_a<0> & cs1 & !Ncs2 &
!spi_int<1> & cpu_Nphi2
MACROCELL | 3 | 13 | diag_OBUF
ATTRIBUTES | 264962 | 0
OUTPUTMC | 1 | 3 | 14
INPUTS | 7 | spi_Nsel<0> | start_shifting | shifting2 | slaveinten<1> | cpu_a<1> | cpu_a<0> | cpu_d<5>.PIN
INPUTMC | 4 | 3 | 10 | 2 | 5 | 2 | 0 | 3 | 14
INPUTP | 3 | 59 | 52 | 29
EXPORTS | 1 | 3 | 14
EQ | 3 |
diag = spi_Nsel<0> & !start_shifting & !shifting2;
diag_OBUF.EXP = slaveinten<1> & cpu_a<1> & cpu_a<0> &
!cpu_d<5>.PIN
MACROCELL | 2 | 8 | cpu_Nirq_OBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 1 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
INPUTMC | 1 | 2 | 17
EQ | 2 |
cpu_Nirq = Gnd;
cpu_Nirq.OE = cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST;
MACROCELL | 2 | 3 | $OpTx$INV$22__$INT
ATTRIBUTES | 133888 | 0
OUTPUTMC | 16 | 1 | 1 | 3 | 17 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 2 | 9 | 2 | 6 | 3 | 16 | 2 | 15 | 2 | 16 | 3 | 2 | 3 | 9 | 2 | 2 | 2 | 0
INPUTS | 5 | ece | cpu_Nphi2 | extclk | start_shifting | shifting2
INPUTMC | 3 | 0 | 10 | 2 | 5 | 2 | 0
INPUTP | 2 | 20 | 21
EQ | 3 |
$OpTx$INV$22__$INT = ece & !extclk
# !ece & !cpu_Nphi2
# !start_shifting & !shifting2;
MACROCELL | 1 | 0 | start_shifting/start_shifting_RSTF__$INT
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 2 | 5 | 1 | 1
INPUTS | 8 | cpu_Nres | shiftdone | shiftcnt<3> | shiftcnt<2> | shiftcnt<1> | spidataout<3> | shifting2 | spidataout<7>
INPUTMC | 7 | 2 | 2 | 2 | 15 | 2 | 16 | 3 | 9 | 0 | 0 | 2 | 0 | 3 | 3
INPUTP | 1 | 49
EXPORTS | 1 | 1 | 1
EQ | 5 |
start_shifting/start_shifting_RSTF__$INT = cpu_Nres & !shiftdone;
start_shifting/start_shifting_RSTF__$INT.EXP = shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<3> & shifting2
# !shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<7> & shifting2
MACROCELL | 2 | 17 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 2 | 8
INPUTS | 10 | ier | tc | slaveinten<3> | spi_int<3> | slaveinten<2> | spi_int<2> | slaveinten<0> | spi_int<0> | slaveinten<1> | spi_int<1>
INPUTMC | 6 | 3 | 15 | 3 | 0 | 3 | 11 | 3 | 12 | 0 | 8 | 3 | 14
INPUTP | 4 | 11 | 92 | 7 | 3
EQ | 5 |
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST = ier & tc
# slaveinten<0> & !spi_int<0>
# slaveinten<1> & !spi_int<1>
# slaveinten<2> & !spi_int<2>
# slaveinten<3> & !spi_int<3>;
MACROCELL | 1 | 2 | EXP6_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 1 | 1
INPUTS | 9 | shiftcnt<3> | shiftcnt<2> | shiftcnt<1> | shiftdone | spidataout<0> | shifting2 | spidataout<2> | spidataout<4> | spidataout<6>
INPUTMC | 9 | 2 | 15 | 2 | 16 | 3 | 9 | 2 | 2 | 0 | 3 | 2 | 0 | 0 | 1 | 3 | 8 | 3 | 5
EXPORTS | 1 | 1 | 1
EQ | 8 |
EXP6_.EXP = shiftcnt<3> & shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<0> & shifting2
# shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<2> & shifting2
# !shiftcnt<3> & shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<4> & shifting2
# !shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<6> & shifting2
PIN | cpu_Nres | 64 | 0 | N/A | 49 | 41 | 1 | 1 | 3 | 10 | 3 | 7 | 3 | 4 | 3 | 1 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 15 | 0 | 8 | 3 | 14 | 3 | 12 | 3 | 11 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 3 | 17 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 2 | 9 | 2 | 6 | 3 | 16 | 2 | 15 | 2 | 16 | 3 | 2 | 3 | 9 | 2 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 1 | 0
PIN | cpu_rnw | 64 | 0 | N/A | 24 | 35 | 3 | 10 | 3 | 7 | 3 | 4 | 3 | 1 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 15 | 0 | 8 | 3 | 14 | 3 | 12 | 3 | 11 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 2 | 5 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 14 | 0 | 16 | 2 | 1 | 2 | 4 | 2 | 7 | 2 | 0
PIN | Ncs2 | 64 | 0 | N/A | 46 | 36 | 3 | 10 | 3 | 7 | 3 | 4 | 3 | 1 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 15 | 0 | 8 | 3 | 14 | 3 | 12 | 3 | 11 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 2 | 5 | 3 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 14 | 0 | 16 | 2 | 1 | 2 | 4 | 2 | 7 | 2 | 0
PIN | cs1 | 64 | 0 | N/A | 50 | 36 | 3 | 10 | 3 | 7 | 3 | 4 | 3 | 1 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 15 | 0 | 8 | 3 | 14 | 3 | 12 | 3 | 11 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 2 | 5 | 3 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 14 | 0 | 16 | 2 | 1 | 2 | 4 | 2 | 7 | 2 | 0
PIN | cpu_a<1> | 64 | 0 | N/A | 59 | 37 | 3 | 10 | 3 | 7 | 3 | 4 | 3 | 1 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 15 | 0 | 8 | 3 | 14 | 3 | 12 | 3 | 11 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 2 | 5 | 3 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 14 | 0 | 16 | 2 | 1 | 2 | 4 | 2 | 7 | 2 | 0 | 3 | 13
PIN | cpu_a<0> | 64 | 0 | N/A | 52 | 37 | 3 | 10 | 3 | 7 | 3 | 4 | 3 | 1 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 15 | 0 | 8 | 3 | 14 | 3 | 12 | 3 | 11 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 2 | 5 | 3 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 14 | 0 | 16 | 2 | 1 | 2 | 4 | 2 | 7 | 2 | 0 | 3 | 13
PIN | spi_miso<3> | 64 | 0 | N/A | 89 | 1 | 3 | 17
PIN | spi_miso<2> | 64 | 0 | N/A | 90 | 1 | 3 | 17
PIN | spi_miso<1> | 64 | 0 | N/A | 9 | 1 | 3 | 0
PIN | spi_miso<0> | 64 | 0 | N/A | 10 | 1 | 3 | 0
PIN | cpu_Nphi2 | 64 | 0 | N/A | 20 | 10 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 14 | 0 | 16 | 2 | 1 | 2 | 4 | 2 | 7 | 2 | 3 | 2 | 0
PIN | spi_int<0> | 64 | 0 | N/A | 7 | 2 | 0 | 16 | 2 | 17
PIN | spi_int<1> | 64 | 0 | N/A | 3 | 2 | 2 | 0 | 2 | 17
PIN | spi_int<2> | 64 | 0 | N/A | 92 | 2 | 2 | 4 | 2 | 17
PIN | spi_int<3> | 64 | 0 | N/A | 11 | 2 | 2 | 7 | 2 | 17
PIN | extclk | 64 | 0 | N/A | 21 | 1 | 2 | 3
PIN | spi_mosi | 536871040 | 0 | N/A | 87
PIN | spi_Nsel<0> | 536871040 | 0 | N/A | 68
PIN | spi_Nsel<1> | 536871040 | 0 | N/A | 65
PIN | spi_Nsel<2> | 536871040 | 0 | N/A | 63
PIN | spi_Nsel<3> | 536871040 | 0 | N/A | 62
PIN | spi_sclk | 536871040 | 0 | N/A | 83
PIN | diag | 536871040 | 0 | N/A | 72
PIN | cpu_Nirq | 536871040 | 0 | N/A | 38
PIN | cpu_d<0> | 536870976 | 0 | N/A | 12 | 4 | 3 | 10 | 0 | 17 | 0 | 13 | 0 | 3
PIN | cpu_d<1> | 536870976 | 0 | N/A | 13 | 4 | 3 | 7 | 0 | 15 | 0 | 12 | 0 | 2
PIN | cpu_d<2> | 536870976 | 0 | N/A | 15 | 4 | 3 | 4 | 0 | 10 | 0 | 11 | 0 | 1
PIN | cpu_d<3> | 536870976 | 0 | N/A | 26 | 3 | 3 | 1 | 0 | 6 | 0 | 0
PIN | cpu_d<4> | 536870976 | 0 | N/A | 27 | 3 | 0 | 9 | 0 | 8 | 3 | 8
PIN | cpu_d<5> | 536870976 | 0 | N/A | 29 | 3 | 3 | 14 | 3 | 6 | 3 | 13
PIN | cpu_d<6> | 536870976 | 0 | N/A | 31 | 4 | 3 | 15 | 3 | 12 | 3 | 5 | 3 | 14
PIN | cpu_d<7> | 536870976 | 0 | N/A | 33 | 2 | 3 | 11 | 3 | 3

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<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ibis [
<!ELEMENT ibis (part, pin+)>
<!ELEMENT part EMPTY>
<!ELEMENT pin EMPTY>
<!ATTLIST part
arch CDATA #REQUIRED
device CDATA #REQUIRED
spg CDATA #REQUIRED
pkg CDATA #REQUIRED>
<!ATTLIST pin
nm CDATA #REQUIRED
no CDATA #REQUIRED
iostd (TTL|LVTTL|LVCMOS2|NA) "NA"
sr (SLOW|FAST|slow|fast) "SLOW"
dir (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
]>
<ibis><part pkg="PC44" spg="-10" arch="xc9500xl" device="XC9572XL"/><pin nm="cpu_Nres" no="19" dir="input"/><pin nm="cpu_rnw" no="7" dir="input"/><pin nm="Ncs2" no="18" dir="input"/><pin nm="cs1" no="20" dir="input"/><pin nm="cpu_a&lt;1&gt;" no="24" dir="input"/><pin nm="cpu_a&lt;0&gt;" no="22" dir="input"/><pin nm="spi_miso&lt;3&gt;" no="37" dir="input"/><pin nm="spi_miso&lt;2&gt;" no="38" dir="input"/><pin nm="spi_miso&lt;1&gt;" no="43" dir="input"/><pin nm="spi_miso&lt;0&gt;" no="44" dir="input"/><pin nm="cpu_Nphi2" no="5" dir="input"/><pin nm="spi_int&lt;0&gt;" no="42" dir="input"/><pin nm="spi_int&lt;1&gt;" no="40" dir="input"/><pin nm="spi_int&lt;2&gt;" no="39" dir="input"/><pin nm="spi_int&lt;3&gt;" no="1" dir="input"/><pin nm="extclk" no="6" dir="input"/><pin nm="spi_mosi" no="35" sr="fast" dir="output"/><pin nm="spi_Nsel&lt;0&gt;" no="28" sr="fast" dir="output"/><pin nm="spi_Nsel&lt;1&gt;" no="27" sr="fast" dir="output"/><pin nm="spi_Nsel&lt;2&gt;" no="26" sr="fast" dir="output"/><pin nm="spi_Nsel&lt;3&gt;" no="25" sr="fast" dir="output"/><pin nm="spi_sclk" no="34" sr="fast" dir="output"/><pin nm="diag" no="29" sr="fast" dir="output"/><pin nm="cpu_Nirq" no="14" sr="fast" dir="output"/><pin nm="cpu_d&lt;0&gt;" no="2" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;1&gt;" no="3" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;2&gt;" no="4" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;3&gt;" no="8" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;4&gt;" no="9" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;5&gt;" no="11" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;6&gt;" no="12" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;7&gt;" no="13" sr="fast" dir="bidir"/></ibis>

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vhdl work SPI6502B1.1.vhd

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cpldfit: version G.38 Xilinx Inc.
Fitter Report
Design Name: spi6502b Date: 5- 6-2017, 5:27PM
Device Used: XC9572XL-10-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
56 /72 ( 78%) 247 /360 ( 69%) 43 /72 ( 60%) 32 /34 ( 94%) 127/216 ( 59%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 16 16 | I/O : 26 2
Output : 8 8 | GCK/IO : 3 0
Bidirectional : 8 8 | GTS/IO : 2 0
GCK : 0 0 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 32 32
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 43
Non-registered Macrocell driving I/O 10
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 56 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 56 macrocells used (MC).
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
$OpTx$INV$22__$INT 3 5 FB3_4 STD (b) (b)
cpha 5 8 FB1_18 STD (b) (b) RESET
cpol 5 8 FB1_16 STD (b) (b) RESET
cpu_Nirq 1 1 FB3_9 STD FAST 14 I/O O
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST 5 10 FB3_18 STD (b) (b)
cpu_d<0> 5 10 FB1_5 STD FAST 2 I/O I/O
cpu_d<1> 5 10 FB1_6 STD FAST 3 I/O I/O
cpu_d<2> 5 10 FB1_8 STD FAST 4 I/O I/O
cpu_d<3> 4 9 FB1_15 STD FAST 8 I/O I/O
cpu_d<4> 5 10 FB1_17 STD FAST 9 I/O I/O
cpu_d<5> 6 11 FB3_2 STD FAST 11 I/O I/O
cpu_d<6> 5 10 FB3_5 STD FAST 12 I/O I/O
cpu_d<7> 5 10 FB3_8 STD FAST 13 I/O I/O
diag 1 3 FB4_14 STD FAST 29 I/O O
divisor<0> 5 8 FB1_14 STD 7 GCK/I/O I RESET
divisor<1> 5 8 FB1_13 STD (b) (b) RESET
divisor<2> 5 8 FB1_12 STD (b) (b) RESET
ece 5 8 FB1_11 STD 6 GCK/I/O I RESET
frx 5 8 FB1_10 STD (b) (b) RESET
ier 5 8 FB4_16 STD (b) (b) RESET
shiftcnt<0> 3 4 FB4_3 STD (b) (b) RESET
shiftcnt<1> 4 5 FB4_10 STD (b) (b) RESET
shiftcnt<2> 4 6 FB3_17 STD 22 I/O I RESET
shiftcnt<3> 4 7 FB3_16 STD 24 I/O I RESET
shiftdone 3 6 FB3_3 STD (b) (b) RESET
shifting2 2 3 FB3_1 STD (b) (b) RESET
slaveinten<0> 5 8 FB1_9 STD 5 GCK/I/O I RESET
slaveinten<1> 5 8 FB4_15 STD 33 I/O (b) RESET
slaveinten<2> 5 8 FB4_13 STD (b) (b) RESET
slaveinten<3> 5 8 FB4_12 STD (b) (b) RESET
spi_Nsel<0> 5 8 FB4_11 STD FAST 28 I/O O RESET
spi_Nsel<1> 5 8 FB4_8 STD FAST 27 I/O O RESET
spi_Nsel<2> 5 8 FB4_5 STD FAST 26 I/O O RESET
spi_Nsel<3> 5 8 FB4_2 STD FAST 25 I/O O RESET
spi_mosi 11 16 FB2_2 STD FAST 35 I/O O RESET
spi_sclk 6 7 FB4_17 STD FAST 34 I/O O RESET
spidatain<0> 7 12 FB4_18 STD (b) (b) RESET
spidatain<1> 4 5 FB3_15 STD 20 I/O I RESET
spidatain<2> 4 5 FB3_14 STD 19 I/O I RESET
spidatain<3> 4 5 FB3_13 STD (b) (b) RESET
spidatain<4> 4 5 FB3_12 STD (b) (b) RESET
spidatain<5> 4 5 FB3_11 STD 18 I/O I RESET
spidatain<6> 4 5 FB3_10 STD (b) (b) RESET
spidatain<7> 4 5 FB3_7 STD (b) (b) RESET
spidataout<0> 4 8 FB1_4 STD (b) (b) RESET
spidataout<1> 4 8 FB1_3 STD (b) (b) RESET
spidataout<2> 4 8 FB1_2 STD 1 I/O I RESET
spidataout<3> 4 8 FB1_1 STD (b) (b) RESET
spidataout<4> 4 8 FB4_9 STD (b) (b) RESET
spidataout<5> 4 8 FB4_7 STD (b) (b) RESET
spidataout<6> 4 8 FB4_6 STD (b) (b) RESET
spidataout<7> 4 8 FB4_4 STD (b) (b) RESET
start_shifting 4 8 FB3_6 STD (b) (b) RESET
start_shifting/start_shifting_RSTF__$INT 1 2 FB2_1 STD (b) (b)
tc 3 5 FB4_1 STD (b) (b) RESET
tmo 5 8 FB1_7 STD (b) (b) RESET
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
Ncs2 FB3_11 18 I/O I
cpu_Nphi2 FB1_9 5 GCK/I/O I
cpu_Nres FB3_14 19 I/O I
cpu_a<0> FB3_17 22 I/O I
cpu_a<1> FB3_16 24 I/O I
cpu_rnw FB1_14 7 GCK/I/O I
cs1 FB3_15 20 I/O I
extclk FB1_11 6 GCK/I/O I
spi_int<0> FB2_14 42 GTS/I/O I
spi_int<1> FB2_11 40 GTS/I/O I
spi_int<2> FB2_9 39 GSR/I/O I
spi_int<3> FB1_2 1 I/O I
spi_miso<0> FB2_17 44 I/O I
spi_miso<1> FB2_15 43 I/O I
spi_miso<2> FB2_8 38 I/O I
spi_miso<3> FB2_6 37 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 18 35 35 85 0/5 9
FB2 2 16 16 12 1/0 9
FB3 18 38 38 70 1/3 9
FB4 18 38 38 80 6/0 7
---- ----- ----- -----
56 247 8/8 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 35/19
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
spidataout<3> 4 0 0 1 FB1_1 STD (b) (b)
spidataout<2> 4 0 0 1 FB1_2 STD 1 I/O I
spidataout<1> 4 0 0 1 FB1_3 STD (b) (b)
spidataout<0> 4 0 0 1 FB1_4 STD (b) (b)
cpu_d<0> 5 0 0 0 FB1_5 STD 2 I/O I/O
cpu_d<1> 5 0 0 0 FB1_6 STD 3 I/O I/O
tmo 5 0 0 0 FB1_7 STD (b) (b)
cpu_d<2> 5 0 0 0 FB1_8 STD 4 I/O I/O
slaveinten<0> 5 0 0 0 FB1_9 STD 5 GCK/I/O I
frx 5 0 0 0 FB1_10 STD (b) (b)
ece 5 0 0 0 FB1_11 STD 6 GCK/I/O I
divisor<2> 5 0 0 0 FB1_12 STD (b) (b)
divisor<1> 5 0 0 0 FB1_13 STD (b) (b)
divisor<0> 5 0 0 0 FB1_14 STD 7 GCK/I/O I
cpu_d<3> 4 0 0 1 FB1_15 STD 8 I/O I/O
cpol 5 0 0 0 FB1_16 STD (b) (b)
cpu_d<4> 5 0 0 0 FB1_17 STD 9 I/O I/O
cpha 5 0 0 0 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: cpu_d<0>.PIN 13: cpu_rnw 25: spi_int<0>
2: cpu_d<1>.PIN 14: cs1 26: spidatain<0>
3: cpu_d<2>.PIN 15: divisor<0> 27: spidatain<1>
4: cpu_d<3>.PIN 16: divisor<1> 28: spidatain<2>
5: cpu_d<4>.PIN 17: divisor<2> 29: spidatain<3>
6: Ncs2 18: ece 30: spidatain<4>
7: cpha 19: frx 31: spidataout<0>
8: cpol 20: slaveinten<0> 32: spidataout<1>
9: cpu_Nphi2 21: spi_Nsel<0> 33: spidataout<2>
10: cpu_Nres 22: spi_Nsel<1> 34: spidataout<3>
11: cpu_a<0> 23: spi_Nsel<2> 35: tmo
12: cpu_a<1> 24: spi_Nsel<3>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
spidataout<3> ...X.X...XXXXX...................X...... 8 8
spidataout<2> ..X..X...XXXXX..................X....... 8 8
spidataout<1> .X...X...XXXXX.................X........ 8 8
spidataout<0> X....X...XXXXX................X......... 8 8
cpu_d<0> .....XX.X.XXXXX.....X....X.............. 10 10
cpu_d<1> .....X.XX.XXXX.X.....X....X............. 10 10
tmo ...X.X...XXXXX....................X..... 8 8
cpu_d<2> .....X..X.XXXX..XX....X....X............ 10 10
slaveinten<0> ....XX...XXXXX.....X.................... 8 8
frx ....XX...XXXXX....X..................... 8 8
ece ..X..X...XXXXX...X...................... 8 8
divisor<2> ..X..X...XXXXX..X....................... 8 8
divisor<1> .X...X...XXXXX.X........................ 8 8
divisor<0> X....X...XXXXXX......................... 8 8
cpu_d<3> .....X..X.XXXX.........X....X.....X..... 9 9
cpol .X...X.X.XXXXX.......................... 8 8
cpu_d<4> .....X..X.XXXX....XX....X....X.......... 10 10
cpha X....XX..XXXXX.......................... 8 8
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 16/38
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
start_shifting/start_shifting_RSTF__$INT
1 0 \/2 2 FB2_1 STD (b) (b)
spi_mosi 11 6<- 0 0 FB2_2 STD 35 I/O O
(unused) 0 0 /\4 1 FB2_3 (b) (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 36 I/O
(unused) 0 0 0 5 FB2_6 37 I/O I
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 38 I/O I
(unused) 0 0 0 5 FB2_9 39 GSR/I/O I
(unused) 0 0 0 5 FB2_10 (b)
(unused) 0 0 0 5 FB2_11 40 GTS/I/O I
(unused) 0 0 0 5 FB2_12 (b)
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 42 GTS/I/O I
(unused) 0 0 0 5 FB2_15 43 I/O I
(unused) 0 0 0 5 FB2_16 (b)
(unused) 0 0 0 5 FB2_17 44 I/O I
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: $OpTx$INV$22__$INT
7: shifting2 12: spidataout<4>
2: cpu_Nres 8: spidataout<0> 13: spidataout<5>
3: shiftcnt<1> 9: spidataout<1> 14: spidataout<6>
4: shiftcnt<2> 10: spidataout<2> 15: spidataout<7>
5: shiftcnt<3> 11: spidataout<3> 16: tmo
6: shiftdone
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
start_shifting/start_shifting_RSTF__$INT
.X...X.................................. 2 2
spi_mosi XXXXXXXXXXXXXXXX........................ 16 16
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 38/16
Number of signals used by logic mapping into function block: 38
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
shifting2 2 0 \/1 2 FB3_1 STD (b) (b)
cpu_d<5> 6 1<- 0 0 FB3_2 STD 11 I/O I/O
shiftdone 3 0 0 2 FB3_3 STD (b) (b)
$OpTx$INV$22__$INT 3 0 0 2 FB3_4 STD (b) (b)
cpu_d<6> 5 0 0 0 FB3_5 STD 12 I/O I/O
start_shifting 4 0 0 1 FB3_6 STD (b) (b)
spidatain<7> 4 0 0 1 FB3_7 STD (b) (b)
cpu_d<7> 5 0 0 0 FB3_8 STD 13 I/O I/O
cpu_Nirq 1 0 0 4 FB3_9 STD 14 I/O O
spidatain<6> 4 0 0 1 FB3_10 STD (b) (b)
spidatain<5> 4 0 0 1 FB3_11 STD 18 I/O I
spidatain<4> 4 0 0 1 FB3_12 STD (b) (b)
spidatain<3> 4 0 0 1 FB3_13 STD (b) (b)
spidatain<2> 4 0 0 1 FB3_14 STD 19 I/O I
spidatain<1> 4 0 0 1 FB3_15 STD 20 I/O I
shiftcnt<3> 4 0 0 1 FB3_16 STD 24 I/O I
shiftcnt<2> 4 0 0 1 FB3_17 STD 22 I/O I
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
5 0 0 0 FB3_18 STD (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$INV$22__$INT
14: shiftcnt<0> 27: spi_int<3>
2: Ncs2 15: shiftcnt<1> 28: spidatain<0>
3: cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
16: shiftcnt<2> 29: spidatain<1>
4: cpu_Nphi2 17: shiftcnt<3> 30: spidatain<2>
5: cpu_Nres 18: shiftdone 31: spidatain<3>
6: cpu_a<0> 19: shifting2 32: spidatain<4>
7: cpu_a<1> 20: slaveinten<0> 33: spidatain<5>
8: cpu_rnw 21: slaveinten<1> 34: spidatain<6>
9: cs1 22: slaveinten<2> 35: spidatain<7>
10: ece 23: slaveinten<3> 36: start_shifting
11: extclk 24: spi_int<0> 37: start_shifting/start_shifting_RSTF__$INT
12: frx 25: spi_int<1> 38: tc
13: ier 26: spi_int<2>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
shifting2 X................X.................X.... 3 3
cpu_d<5> .X.X.XXXX.........X.X...X.......X..X.... 11 11
shiftdone X...X........XXXX....................... 6 6
$OpTx$INV$22__$INT ...X.....XX.......X................X.... 5 5
cpu_d<6> .X.X.XXXX...X........X...X.......X...... 10 10
start_shifting .X...XXXX..X.......................XX... 8 8
spidatain<7> X...X........X....X..............X...... 5 5
cpu_d<7> .X.X.XXXX.............X...X.......X..X.. 10 10
cpu_Nirq ..X..................................... 1 1
spidatain<6> X...X........X....X.............X....... 5 5
spidatain<5> X...X........X....X............X........ 5 5
spidatain<4> X...X........X....X...........X......... 5 5
spidatain<3> X...X........X....X..........X.......... 5 5
spidatain<2> X...X........X....X.........X........... 5 5
spidatain<1> X...X........X....X........X............ 5 5
shiftcnt<3> X...X........XXXX.X..................... 7 7
shiftcnt<2> X...X........XXX..X..................... 6 6
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
............X......XXXXXXXX..........X.. 10 10
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 38/16
Number of signals used by logic mapping into function block: 38
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
tc 3 0 /\2 0 FB4_1 STD (b) (b)
spi_Nsel<3> 5 0 0 0 FB4_2 STD 25 I/O O
shiftcnt<0> 3 0 0 2 FB4_3 STD (b) (b)
spidataout<7> 4 0 0 1 FB4_4 STD (b) (b)
spi_Nsel<2> 5 0 0 0 FB4_5 STD 26 I/O O
spidataout<6> 4 0 0 1 FB4_6 STD (b) (b)
spidataout<5> 4 0 0 1 FB4_7 STD (b) (b)
spi_Nsel<1> 5 0 0 0 FB4_8 STD 27 I/O O
spidataout<4> 4 0 0 1 FB4_9 STD (b) (b)
shiftcnt<1> 4 0 0 1 FB4_10 STD (b) (b)
spi_Nsel<0> 5 0 0 0 FB4_11 STD 28 I/O O
slaveinten<3> 5 0 0 0 FB4_12 STD (b) (b)
slaveinten<2> 5 0 0 0 FB4_13 STD (b) (b)
diag 1 0 \/1 3 FB4_14 STD 29 I/O O
slaveinten<1> 5 1<- \/1 0 FB4_15 STD 33 I/O (b)
ier 5 1<- \/1 0 FB4_16 STD (b) (b)
spi_sclk 6 1<- 0 0 FB4_17 STD 34 I/O O
spidatain<0> 7 2<- 0 0 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$INV$22__$INT
14: cpu_a<0> 27: spi_Nsel<1>
2: cpu_d<0>.PIN 15: cpu_a<1> 28: spi_Nsel<2>
3: cpu_d<1>.PIN 16: cpu_rnw 29: spi_Nsel<3>
4: cpu_d<2>.PIN 17: cs1 30: spi_miso<0>
5: cpu_d<3>.PIN 18: ier 31: spi_miso<1>
6: cpu_d<4>.PIN 19: shiftcnt<0> 32: spi_miso<2>
7: cpu_d<5>.PIN 20: shiftcnt<1> 33: spi_miso<3>
8: cpu_d<6>.PIN 21: shiftdone 34: spidataout<4>
9: cpu_d<7>.PIN 22: shifting2 35: spidataout<5>
10: Ncs2 23: slaveinten<1> 36: spidataout<6>
11: cpha 24: slaveinten<2> 37: spidataout<7>
12: cpol 25: slaveinten<3> 38: start_shifting
13: cpu_Nres 26: spi_Nsel<0>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
tc .........X...XX.X...X................... 5 5
spi_Nsel<3> ....X....X..XXXXX...........X........... 8 8
shiftcnt<0> X...........X.....X..X.................. 4 4
spidataout<7> ........XX..XXXXX...................X... 8 8
spi_Nsel<2> ...X.....X..XXXXX..........X............ 8 8
spidataout<6> .......X.X..XXXXX..................X.... 8 8
spidataout<5> ......X..X..XXXXX.................X..... 8 8
spi_Nsel<1> ..X......X..XXXXX.........X............. 8 8
spidataout<4> .....X...X..XXXXX................X...... 8 8
shiftcnt<1> X...........X.....XX.X.................. 5 5
spi_Nsel<0> .X.......X..XXXXX........X.............. 8 8
slaveinten<3> ........XX..XXXXX.......X............... 8 8
slaveinten<2> .......X.X..XXXXX......X................ 8 8
diag .....................X...X...........X.. 3 3
slaveinten<1> ......X..X..XXXXX.....X................. 8 8
ier .......X.X..XXXXXX...................... 8 8
spi_sclk X.........XXX.....X.XX.................. 7 7
spidatain<0> X...........X.....X..X...XXXXXXXX....... 12 12
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
$OpTx$INV$22__$INT <= ((ece AND NOT extclk)
OR (NOT ece AND NOT cpu_Nphi2)
OR (NOT start_shifting AND NOT shifting2));
FTCPE_cpha: FTCPE port map (cpha,cpha_T,cpha_C,NOT cpu_Nres,'0',NOT cpu_rnw);
cpha_T <= ((cpha AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(0).PIN)
OR (NOT cpha AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(0).PIN));
cpha_C <= NOT ((cs1 AND NOT Ncs2));
FTCPE_cpol: FTCPE port map (cpol,cpol_T,cpol_C,NOT cpu_Nres,'0',NOT cpu_rnw);
cpol_T <= ((cpol AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(1).PIN)
OR (NOT cpol AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(1).PIN));
cpol_C <= NOT ((cs1 AND NOT Ncs2));
cpu_Nirq_I <= '0';
cpu_Nirq <= cpu_Nirq_I when cpu_Nirq_OE = '1' else 'Z';
cpu_Nirq_OE <= cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST;
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST <= ((ier AND tc)
OR (slaveinten(0) AND NOT spi_int(0))
OR (slaveinten(1) AND NOT spi_int(1))
OR (slaveinten(2) AND NOT spi_int(2))
OR (slaveinten(3) AND NOT spi_int(3)));
diag <= (spi_Nsel(0) AND NOT start_shifting AND NOT shifting2);
FTCPE_divisor0: FTCPE port map (divisor(0),divisor_T(0),divisor_C(0),NOT cpu_Nres,'0',NOT cpu_rnw);
divisor_T(0) <= ((divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(0).PIN)
OR (NOT divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(0).PIN));
divisor_C(0) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_divisor1: FTCPE port map (divisor(1),divisor_T(1),divisor_C(1),NOT cpu_Nres,'0',NOT cpu_rnw);
divisor_T(1) <= ((divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(1).PIN)
OR (NOT divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(1).PIN));
divisor_C(1) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_divisor2: FTCPE port map (divisor(2),divisor_T(2),divisor_C(2),NOT cpu_Nres,'0',NOT cpu_rnw);
divisor_T(2) <= ((divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(2).PIN)
OR (NOT divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(2).PIN));
divisor_C(2) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_ece: FTCPE port map (ece,ece_T,ece_C,NOT cpu_Nres,'0',NOT cpu_rnw);
ece_T <= ((ece AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(2).PIN)
OR (NOT ece AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(2).PIN));
ece_C <= NOT ((cs1 AND NOT Ncs2));
FTCPE_frx: FTCPE port map (frx,frx_T,frx_C,NOT cpu_Nres,'0',NOT cpu_rnw);
frx_T <= ((frx AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(4).PIN)
OR (NOT frx AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(4).PIN));
frx_C <= NOT ((cs1 AND NOT Ncs2));
FTCPE_ier: FTCPE port map (ier,ier_T,ier_C,NOT cpu_Nres,'0',NOT cpu_rnw);
ier_T <= ((slaveinten(1).EXP)
OR (NOT ier AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(6).PIN));
ier_C <= NOT ((cs1 AND NOT Ncs2));
cpu_d_I(0) <= ((cpu_rnw AND spi_Nsel(0) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND cpha AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(0) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2));
cpu_d(0) <= cpu_d_I(0) when cpu_d_OE(0) = '1' else 'Z';
cpu_d_OE(0) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(1) <= ((cpu_rnw AND spi_Nsel(1) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND cpol AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(1) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2));
cpu_d(1) <= cpu_d_I(1) when cpu_d_OE(1) = '1' else 'Z';
cpu_d_OE(1) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(2) <= ((cpu_rnw AND spi_Nsel(2) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND ece AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(2) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2));
cpu_d(2) <= cpu_d_I(2) when cpu_d_OE(2) = '1' else 'Z';
cpu_d_OE(2) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(3) <= ((cpu_rnw AND spi_Nsel(3) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND tmo AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(3) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2));
cpu_d(3) <= cpu_d_I(3) when cpu_d_OE(3) = '1' else 'Z';
cpu_d_OE(3) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(4) <= ((cpu_rnw AND frx AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND slaveinten(0) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(4) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND cs1 AND NOT Ncs2 AND
NOT spi_int(0) AND cpu_Nphi2));
cpu_d(4) <= cpu_d_I(4) when cpu_d_OE(4) = '1' else 'Z';
cpu_d_OE(4) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(5) <= ((shifting2.EXP)
OR (cpu_rnw AND slaveinten(1) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(5) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND start_shifting AND NOT cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND NOT Ncs2 AND
shifting2 AND cpu_Nphi2));
cpu_d(5) <= cpu_d_I(5) when cpu_d_OE(5) = '1' else 'Z';
cpu_d_OE(5) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(6) <= ((cpu_rnw AND ier AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND slaveinten(2) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(6) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND cs1 AND NOT Ncs2 AND
NOT spi_int(2) AND cpu_Nphi2));
cpu_d(6) <= cpu_d_I(6) when cpu_d_OE(6) = '1' else 'Z';
cpu_d_OE(6) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(7) <= ((cpu_rnw AND slaveinten(3) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(7) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND tc AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND cs1 AND NOT Ncs2 AND
NOT spi_int(3) AND cpu_Nphi2));
cpu_d(7) <= cpu_d_I(7) when cpu_d_OE(7) = '1' else 'Z';
cpu_d_OE(7) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
FDCPE_spi_mosi: FDCPE port map (spi_mosi_I,spi_mosi,NOT $OpTx$INV$22__$INT,'0',NOT cpu_Nres);
spi_mosi <= ((start_shifting/start_shifting_RSTF__$INT.EXP)
OR (EXP6_.EXP)
OR (shiftcnt(3) AND shiftcnt(2) AND NOT shiftcnt(1) AND
NOT shiftdone AND NOT spidataout(1) AND shifting2)
OR (NOT shiftcnt(3) AND shiftcnt(2) AND NOT shiftcnt(1) AND
NOT shiftdone AND NOT spidataout(5) AND shifting2));
spi_mosi <= spi_mosi_I when spi_mosi_OE = '1' else 'Z';
spi_mosi_OE <= NOT tmo;
FDCPE_spi_sclk: FDCPE port map (spi_sclk,spi_sclk_D,NOT $OpTx$INV$22__$INT,spi_sclk_CLR,spi_sclk_PRE);
spi_sclk_D <= cpol
XOR
spi_sclk_D <= ((ier.EXP)
OR (cpu_Nres AND NOT cpha AND shiftcnt(0) AND NOT shiftdone AND
shifting2));
spi_sclk_CLR <= (NOT cpu_Nres AND NOT cpol);
spi_sclk_PRE <= (NOT cpu_Nres AND cpol);
FDCPE_shiftcnt0: FDCPE port map (shiftcnt(0),shiftcnt_D(0),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0');
shiftcnt_D(0) <= (NOT shiftcnt(0) AND shifting2);
FDCPE_shiftcnt1: FDCPE port map (shiftcnt(1),shiftcnt_D(1),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0');
shiftcnt_D(1) <= ((shiftcnt(0) AND NOT shiftcnt(1) AND shifting2)
OR (NOT shiftcnt(0) AND shiftcnt(1) AND shifting2));
FTCPE_shiftcnt2: FTCPE port map (shiftcnt(2),shiftcnt_T(2),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0');
shiftcnt_T(2) <= ((shiftcnt(2) AND NOT shifting2)
OR (shiftcnt(0) AND shiftcnt(1) AND shifting2));
FTCPE_shiftcnt3: FTCPE port map (shiftcnt(3),shiftcnt_T(3),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0');
shiftcnt_T(3) <= ((shiftcnt(3) AND NOT shifting2)
OR (shiftcnt(2) AND shiftcnt(0) AND shiftcnt(1) AND
shifting2));
FDCPE_shiftdone: FDCPE port map (shiftdone,shiftdone_D,NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0');
shiftdone_D <= (shiftcnt(3) AND shiftcnt(2) AND shiftcnt(0) AND
shiftcnt(1));
FDCPE_shifting2: FDCPE port map (shifting2,shifting2_D,NOT $OpTx$INV$22__$INT,'0','0');
shifting2_D <= (NOT shiftdone AND start_shifting);
FTCPE_slaveinten0: FTCPE port map (slaveinten(0),slaveinten_T(0),slaveinten_C(0),NOT cpu_Nres,'0',NOT cpu_rnw);
slaveinten_T(0) <= ((slaveinten(0) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(4).PIN)
OR (NOT slaveinten(0) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(4).PIN));
slaveinten_C(0) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_slaveinten1: FTCPE port map (slaveinten(1),slaveinten_T(1),slaveinten_C(1),NOT cpu_Nres,'0',NOT cpu_rnw);
slaveinten_T(1) <= ((diag_OBUF.EXP)
OR (NOT slaveinten(1) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(5).PIN));
slaveinten_C(1) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_slaveinten2: FTCPE port map (slaveinten(2),slaveinten_T(2),slaveinten_C(2),NOT cpu_Nres,'0',NOT cpu_rnw);
slaveinten_T(2) <= ((slaveinten(2) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(6).PIN)
OR (NOT slaveinten(2) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(6).PIN));
slaveinten_C(2) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_slaveinten3: FTCPE port map (slaveinten(3),slaveinten_T(3),slaveinten_C(3),NOT cpu_Nres,'0',NOT cpu_rnw);
slaveinten_T(3) <= ((slaveinten(3) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(7).PIN)
OR (NOT slaveinten(3) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(7).PIN));
slaveinten_C(3) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_spi_Nsel0: FTCPE port map (spi_Nsel(0),spi_Nsel_T(0),spi_Nsel_C(0),'0',NOT cpu_Nres,NOT cpu_rnw);
spi_Nsel_T(0) <= ((spi_Nsel(0) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(0).PIN)
OR (NOT spi_Nsel(0) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(0).PIN));
spi_Nsel_C(0) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_spi_Nsel1: FTCPE port map (spi_Nsel(1),spi_Nsel_T(1),spi_Nsel_C(1),'0',NOT cpu_Nres,NOT cpu_rnw);
spi_Nsel_T(1) <= ((spi_Nsel(1) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(1).PIN)
OR (NOT spi_Nsel(1) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(1).PIN));
spi_Nsel_C(1) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_spi_Nsel2: FTCPE port map (spi_Nsel(2),spi_Nsel_T(2),spi_Nsel_C(2),'0',NOT cpu_Nres,NOT cpu_rnw);
spi_Nsel_T(2) <= ((spi_Nsel(2) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(2).PIN)
OR (NOT spi_Nsel(2) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(2).PIN));
spi_Nsel_C(2) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_spi_Nsel3: FTCPE port map (spi_Nsel(3),spi_Nsel_T(3),spi_Nsel_C(3),'0',NOT cpu_Nres,NOT cpu_rnw);
spi_Nsel_T(3) <= ((spi_Nsel(3) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(3).PIN)
OR (NOT spi_Nsel(3) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(3).PIN));
spi_Nsel_C(3) <= NOT ((cs1 AND NOT Ncs2));
FDCPE_spidatain0: FDCPE port map (spidatain(0),spidatain_D(0),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(0));
spidatain_D(0) <= ((tc.EXP)
OR (NOT spi_Nsel(2) AND spi_miso(2))
OR (NOT spi_Nsel(3) AND spi_miso(3)));
spidatain_CE(0) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain1: FDCPE port map (spidatain(1),spidatain(0),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(1));
spidatain_CE(1) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain2: FDCPE port map (spidatain(2),spidatain(1),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(2));
spidatain_CE(2) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain3: FDCPE port map (spidatain(3),spidatain(2),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(3));
spidatain_CE(3) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain4: FDCPE port map (spidatain(4),spidatain(3),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(4));
spidatain_CE(4) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain5: FDCPE port map (spidatain(5),spidatain(4),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(5));
spidatain_CE(5) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain6: FDCPE port map (spidatain(6),spidatain(5),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(6));
spidatain_CE(6) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain7: FDCPE port map (spidatain(7),spidatain(6),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(7));
spidatain_CE(7) <= (shiftcnt(0) AND shifting2);
FTCPE_spidataout0: FTCPE port map (spidataout(0),spidataout_T(0),spidataout_C(0),'0','0',spidataout_CE(0));
spidataout_T(0) <= ((spidataout(0) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
NOT cpu_d(0).PIN)
OR (NOT spidataout(0) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cpu_d(0).PIN));
spidataout_C(0) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(0) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout1: FTCPE port map (spidataout(1),spidataout_T(1),spidataout_C(1),'0','0',spidataout_CE(1));
spidataout_T(1) <= ((spidataout(1) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
NOT cpu_d(1).PIN)
OR (NOT spidataout(1) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cpu_d(1).PIN));
spidataout_C(1) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(1) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout2: FTCPE port map (spidataout(2),spidataout_T(2),spidataout_C(2),'0','0',spidataout_CE(2));
spidataout_T(2) <= ((spidataout(2) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
NOT cpu_d(2).PIN)
OR (NOT spidataout(2) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cpu_d(2).PIN));
spidataout_C(2) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(2) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout3: FTCPE port map (spidataout(3),spidataout_T(3),spidataout_C(3),'0','0',spidataout_CE(3));
spidataout_T(3) <= ((spidataout(3) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
NOT cpu_d(3).PIN)
OR (NOT spidataout(3) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cpu_d(3).PIN));
spidataout_C(3) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(3) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout4: FTCPE port map (spidataout(4),spidataout_T(4),spidataout_C(4),'0','0',spidataout_CE(4));
spidataout_T(4) <= ((spidataout(4) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
NOT cpu_d(4).PIN)
OR (NOT spidataout(4) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cpu_d(4).PIN));
spidataout_C(4) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(4) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout5: FTCPE port map (spidataout(5),spidataout_T(5),spidataout_C(5),'0','0',spidataout_CE(5));
spidataout_T(5) <= ((spidataout(5) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
NOT cpu_d(5).PIN)
OR (NOT spidataout(5) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cpu_d(5).PIN));
spidataout_C(5) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(5) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout6: FTCPE port map (spidataout(6),spidataout_T(6),spidataout_C(6),'0','0',spidataout_CE(6));
spidataout_T(6) <= ((spidataout(6) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
NOT cpu_d(6).PIN)
OR (NOT spidataout(6) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cpu_d(6).PIN));
spidataout_C(6) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(6) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout7: FTCPE port map (spidataout(7),spidataout_T(7),spidataout_C(7),'0','0',spidataout_CE(7));
spidataout_T(7) <= ((spidataout(7) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
NOT cpu_d(7).PIN)
OR (NOT spidataout(7) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cpu_d(7).PIN));
spidataout_C(7) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(7) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_start_shifting: FTCPE port map (start_shifting,start_shifting_T,start_shifting_C,NOT start_shifting/start_shifting_RSTF__$INT,'0');
start_shifting_T <= ((NOT cpu_rnw AND NOT start_shifting AND NOT cpu_a(1) AND NOT cpu_a(0))
OR (frx AND NOT start_shifting AND NOT cpu_a(1) AND NOT cpu_a(0)));
start_shifting_C <= NOT ((cs1 AND NOT Ncs2));
start_shifting/start_shifting_RSTF__$INT <= (cpu_Nres AND NOT shiftdone);
FDCPE_tc: FDCPE port map (tc,'0',tc_C,'0',shiftdone,tc_CE);
tc_C <= NOT ((cs1 AND NOT Ncs2));
tc_CE <= (NOT cpu_a(1) AND NOT cpu_a(0));
FTCPE_tmo: FTCPE port map (tmo,tmo_T,tmo_C,NOT cpu_Nres,'0',NOT cpu_rnw);
tmo_T <= ((tmo AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(3).PIN)
OR (NOT tmo AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(3).PIN));
tmo_C <= NOT ((cs1 AND NOT Ncs2));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
**************************** Device Pin Out ****************************
Device : XC9572XL-10-PC44
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
| 7 39 |
| 8 38 |
| 9 37 |
| 10 36 |
| 11 XC9572XL-10-PC44 35 |
| 12 34 |
| 13 33 |
| 14 32 |
| 15 31 |
| 16 30 |
| 17 29 |
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 spi_int<3> 23 GND
2 cpu_d<0> 24 cpu_a<1>
3 cpu_d<1> 25 spi_Nsel<3>
4 cpu_d<2> 26 spi_Nsel<2>
5 cpu_Nphi2 27 spi_Nsel<1>
6 extclk 28 spi_Nsel<0>
7 cpu_rnw 29 diag
8 cpu_d<3> 30 TDO
9 cpu_d<4> 31 GND
10 GND 32 VCC
11 cpu_d<5> 33 TIE
12 cpu_d<6> 34 spi_sclk
13 cpu_d<7> 35 spi_mosi
14 cpu_Nirq 36 TIE
15 TDI 37 spi_miso<3>
16 TMS 38 spi_miso<2>
17 TCK 39 spi_int<2>
18 Ncs2 40 spi_int<1>
19 cpu_Nres 41 VCC
20 cs1 42 spi_int<0>
21 VCC 43 spi_miso<1>
22 cpu_a<0> 44 spi_miso<0>
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572xl-10-PC44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Set Unused I/O Pin Termination : FLOAT
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25

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Release 6.3.03i - xst G.38
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 0.00 s
--> Reading design: spi6502b.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : spi6502b.prj
Input Format : mixed
Ignore Synthesis Constraint File : NO
Verilog Include Directory :
---- Target Parameters
Output File Name : spi6502b
Output Format : NGC
Target Device : xc9500xl
---- Source Options
Top Module Name : spi6502b
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Mux Extraction : YES
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
Equivalent register Removal : YES
MACRO Preserve : YES
XOR Preserve : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : YES
RTL Output : Yes
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
---- Other Options
lso : spi6502b.lso
verilog2001 : YES
Clock Enable : YES
wysiwyg : NO
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file C:/sources/AppleIISd/SPI6502B1.1.vhd in Library work.
Architecture behavioral of Entity spi6502b is up to date.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <spi6502b> (Architecture <behavioral>).
INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 203: Mux is complete : default of case is discarded
INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 320: Mux is complete : default of case is discarded
Entity <spi6502b> analyzed. Unit <spi6502b> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <spi6502b>.
Related source file is C:/sources/AppleIISd/SPI6502B1.1.vhd.
Found 8-bit tristate buffer for signal <cpu_d>.
Found 1-bit tristate buffer for signal <cpu_Nirq>.
Found 1-bit tristate buffer for signal <spi_mosi>.
Found 1-bit xor3 for signal <$n0040> created at line 206.
Found 4-bit adder for signal <$n0047> created at line 160.
Found 1-bit register for signal <cpha>.
Found 1-bit register for signal <cpol>.
Found 3-bit down counter for signal <divcnt>.
Found 3-bit register for signal <divisor>.
Found 1-bit register for signal <ece>.
Found 1-bit register for signal <frx>.
Found 1-bit register for signal <ier>.
Found 1-bit register for signal <int_mosi>.
Found 1-bit register for signal <int_sclk>.
Found 4-bit register for signal <shiftcnt>.
Found 1-bit register for signal <shiftdone>.
Found 1-bit register for signal <shifting2>.
Found 4-bit register for signal <slaveinten>.
Found 4-bit register for signal <slavesel>.
Found 8-bit register for signal <spidatain>.
Found 8-bit register for signal <spidataout>.
Found 1-bit register for signal <start_shifting>.
Found 1-bit register for signal <tc>.
Found 1-bit register for signal <tmo>.
Found 30 1-bit 2-to-1 multiplexers.
Summary:
inferred 1 Counter(s).
inferred 18 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 10 Tristate(s).
Unit <spi6502b> synthesized.
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
4-bit adder : 1
# Registers : 25
1-bit register : 20
8-bit register : 1
3-bit register : 1
4-bit register : 3
# Multiplexers : 12
2-to-1 multiplexer : 12
# Tristates : 3
1-bit tristate buffer : 2
8-bit tristate buffer : 1
# Xors : 1
1-bit xor3 : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <spi6502b> ...
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : spi6502b.ngr
Top Level Output File Name : spi6502b
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : YES
Target Technology : xc9500xl
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 32
Macro Statistics :
# Registers : 74
# 1-bit register : 74
# Tristates : 3
# 1-bit tristate buffer : 2
# 8-bit tristate buffer : 1
# Xors : 5
# 1-bit xor2 : 5
Cell Usage :
# BELS : 320
# AND2 : 156
# AND3 : 2
# AND4 : 1
# GND : 1
# INV : 95
# OR2 : 56
# OR3 : 1
# OR4 : 1
# OR5 : 1
# VCC : 1
# XOR2 : 5
# FlipFlops/Latches : 43
# FD : 1
# FDC : 5
# FDCE : 30
# FDCP : 1
# FDP : 1
# FDPE : 5
# IO Buffers : 32
# IBUF : 16
# IOBUFE : 8
# OBUF : 6
# OBUFE : 2
=========================================================================
CPU : 0.67 / 1.11 s | Elapsed : 1.00 / 1.00 s
-->
Total memory usage is 68952 kilobytes

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<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE document SYSTEM 'file:///C:/Xilinx/chipviewer/data/xsl/buildXML.dtd'>
<document>
<design name='spi6502b'/>
<xilinx path='C:/Xilinx;'/>
<projDir path='C:\sources\AppleIISd'/>
<xslDir path='C:/Xilinx/chipviewer/data/xsl'/>
<fileDir path='/chipviewer/data/html'/>
<dataFile file='index.htm'/>
<dataFile file='report.htm'/>
<dataFile file='eqns.js'/>
<dataFile file='fbs.js'/>
<dataFile file='maplogic.js'/>
<dataFile file='pins.js'/>
<dataFile file='tooltips.js'/>
<dataFile file='errors.js'/>
<dataFile file='leftnav.js'/>
<dataFile file='paths.js'/>
<dataFile file='summary.js'/>
<dataFile file='topnav.js'/>
<dataFile file='applet.js'/>
<dataFile file='plugin.js'/>
<dataFile file='ns4plugin.js'/>
<dataFile file='equations.htm'/>
<dataFile file='result.htm'/>
<dataFile file='style.css'/>
<dataFile file='blank.gif'/>
<dataFile file='fbview.jpg'/>
<dataFile file='pinview.jpg'/>
<dataFile file='xc9500xl_logo.jpg'/>
<dataFile file='asciidoc.htm'/>
<dataFile file='equationsdoc.htm'/>
<dataFile file='errorsdoc.htm'/>
<dataFile file='fbs_FBdoc.htm'/>
<dataFile file='fbsdoc.htm'/>
<dataFile file='mapinputdoc.htm'/>
<dataFile file='maplogicdoc.htm'/>
<dataFile file='optionsdoc.htm'/>
<dataFile file='pinsdoc.htm'/>
<dataFile file='summarydoc.htm'/>
<dataFile file='check.htm'/>
<dataFile file='checkNS4.htm'/>
<dataFile file='appletref.htm'/>
<dataFile file='newappletref.htm'/>
<dataFile file='errors1.gif'/>
<dataFile file='errors2.gif'/>
<dataFile file='equations.gif'/>
<dataFile file='functionblock.gif'/>
<dataFile file='fb1.gif'/>
<dataFile file='legend.gif'/>
<dataFile file='macrocell.gif'/>
<dataFile file='fb.gif'/>
<dataFile file='pin.gif'/>
<dataFile file='pindiagram.gif'/>
<dataFile file='view.gif'/>
<dataFile file='xml8.jpg'/>
<dataFile file='xml7.jpg'/>
<dataFile file='xml6.jpg'/>
<dataFile file='xml5.jpg'/>
<xmlFileGroup id='1'>
<xmlFile file='spi6502b.xml'>
<xslFile file='topnav.xsl'>
<output file='topnav.htm'/>
</xslFile>
<xslFile file='leftnav.xsl'>
<param name='result' value='1'/>
<output file='leftnav.htm'/>
</xslFile>
<xslFile file='print.xsl'>
<output file='ascii.tmp'/>
</xslFile>
<xslFile file='eqns.xsl'>
<output file='eqns.htm'/>
</xslFile>
<xslFile file='summary.xsl'>
<param name='sumOn' value='1'/>
<param name='optOn' value='0'/>
<param name='legendOn' value='0'/>
<output file='summary.htm'/>
</xslFile>
</xmlFile>
</xmlFileGroup>
<xmlFileGroup id='2'>
<xmlFile file='spi6502b.xml'>
<xslFile file='summary.xsl'>
<param name='sumOn' value='0'/>
<param name='optOn' value='1'/>
<param name='legendOn' value='0'/>
<output file='options.htm'/>
</xslFile>
<xslFile file='printErrors.xsl'>
<output file='errs.htm'/>
</xslFile>
<xslFile file='printPins.xsl'>
<output file='pins.htm'/>
</xslFile>
<xslFile file='wait.xsl'>
<output file='wait.htm'/>
</xslFile>
<xslDebug file='printErrors.xsl'>
<output file='errors.htm'/>
</xslDebug>
<xslDebug file='printPins.xsl'>
<output file='pinout.htm'/>
</xslDebug>
<xslDebug file='printEqns.xsl'>
<output file='eqnout.htm'/>
</xslDebug>
<xslFile file='maplogic.xsl'>
<param name='sortType' value='0'/>
<param name='mapLog' value='1'/>
<param name='mapIn' value='0'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<output file='maplogic_00.htm'/>
<param name='sortType' value='1'/>
<param name='mapLog' value='1'/>
<param name='mapIn' value='0'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<output file='maplogic_01.htm'/>
<param name='sortType' value='2'/>
<param name='mapLog' value='1'/>
<param name='mapIn' value='0'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<output file='maplogic_02.htm'/>
<param name='sortType' value='0'/>
<param name='mapLog' value='0'/>
<param name='mapIn' value='1'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<output file='mapinput_00.htm'/>
<param name='sortType' value='1'/>
<param name='mapLog' value='0'/>
<param name='mapIn' value='1'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<output file='mapinput_01.htm'/>
<param name='sortType' value='2'/>
<param name='mapLog' value='0'/>
<param name='mapIn' value='1'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<output file='mapinput_02.htm'/>
</xslFile>
<xslFile file='fbsum.xsl'>
<param name='legendOn' value='0'/>
<output file='fbs.htm'/>
</xslFile>
<xslFile file='fbs.xsl'>
<param name='fb' value='FB1'/>
<param name='type' value='1'/>
<param name='legendOn' value='1'/>
<output file='fbs_FB1.htm'/>
<param name='fb' value='FB2'/>
<param name='type' value='3'/>
<param name='legendOn' value='1'/>
<output file='fbs_FB2.htm'/>
<param name='fb' value='FB3'/>
<param name='type' value='3'/>
<param name='legendOn' value='1'/>
<output file='fbs_FB3.htm'/>
<param name='fb' value='FB4'/>
<param name='type' value='2'/>
<param name='legendOn' value='1'/>
<output file='fbs_FB4.htm'/>
</xslFile>
</xmlFile>
<xmlFile file='C:/Xilinx/chipviewer/data/xsl/pinlegend.xml'>
<xslFile file='legend.xsl'>
<param name='device' value='XC9572XL-10-PC44'/>
<param name='verOn' value='0'/>
<param name='linkName' value='pinlegendV.htm'/>
<output file='pinlegend.htm'/>
<param name='device' value='XC9572XL-10-PC44'/>
<param name='verOn' value='1'/>
<param name='linkName' value='pinlegend.htm'/>
<output file='pinlegendV.htm'/>
</xslFile>
</xmlFile>
<xmlFile file='C:/Xilinx/chipviewer/data/xsl/logiclegend.xml'>
<xslFile file='legend.xsl'>
<param name='device' value='XC9572XL-10-PC44'/>
<param name='verOn' value='0'/>
<param name='linkName' value='logiclegendV.htm'/>
<output file='logiclegend.htm'/>
<param name='device' value='XC9572XL-10-PC44'/>
<param name='verOn' value='1'/>
<param name='linkName' value='logiclegend.htm'/>
<output file='logiclegendV.htm'/>
</xslFile>
</xmlFile>
</xmlFileGroup>
<rptFile file='spi6502b.rpt'/>
<timFile file='spi6502b.tim'/>
<appFile/>
</document>

73
spi6502b_pad.csv Normal file
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Release 6.1i - Fit G.38
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
5- 6-2017 5:27PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The comma ','
character is used as the data field separator.
This file is also designed to support parsing.
Input file: spi6502b.ngd
output file: spi6502b_pad.csv
Part type: xc9572xl
Speed grade: -10
Package: pc44
Pinout by Pin Number:
-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,{blank},Slew Rate,Termination,{blank},Voltage,Constraint,
P1,spi_int<3>,I,I/O,INPUT,,,,,,,,,
P2,cpu_d<0>,I/O,I/O,BIDIR,,,,,,,,,
P3,cpu_d<1>,I/O,I/O,BIDIR,,,,,,,,,
P4,cpu_d<2>,I/O,I/O,BIDIR,,,,,,,,,
P5,cpu_Nphi2,I,I/O/GCK1,INPUT,,,,,,,,,
P6,extclk,I,I/O/GCK2,INPUT,,,,,,,,,
P7,cpu_rnw,I,I/O/GCK3,INPUT,,,,,,,,,
P8,cpu_d<3>,I/O,I/O,BIDIR,,,,,,,,,
P9,cpu_d<4>,I/O,I/O,BIDIR,,,,,,,,,
P10,GND,,GND,,,,,,,,,,
P11,cpu_d<5>,I/O,I/O,BIDIR,,,,,,,,,
P12,cpu_d<6>,I/O,I/O,BIDIR,,,,,,,,,
P13,cpu_d<7>,I/O,I/O,BIDIR,,,,,,,,,
P14,cpu_Nirq,O,I/O,OUTPUT,,,,,,,,,
P15,TDI,,TDI,,,,,,,,,,
P16,TMS,,TMS,,,,,,,,,,
P17,TCK,,TCK,,,,,,,,,,
P18,Ncs2,I,I/O,INPUT,,,,,,,,,
P19,cpu_Nres,I,I/O,INPUT,,,,,,,,,
P20,cs1,I,I/O,INPUT,,,,,,,,,
P21,VCC,,VCCINT,,,,,,,,,,
P22,cpu_a<0>,I,I/O,INPUT,,,,,,,,,
P23,GND,,GND,,,,,,,,,,
P24,cpu_a<1>,I,I/O,INPUT,,,,,,,,,
P25,spi_Nsel<3>,O,I/O,OUTPUT,,,,,,,,,
P26,spi_Nsel<2>,O,I/O,OUTPUT,,,,,,,,,
P27,spi_Nsel<1>,O,I/O,OUTPUT,,,,,,,,,
P28,spi_Nsel<0>,O,I/O,OUTPUT,,,,,,,,,
P29,diag,O,I/O,OUTPUT,,,,,,,,,
P30,TDO,,TDO,,,,,,,,,,
P31,GND,,GND,,,,,,,,,,
P32,VCC,,VCCIO,,,,,,,,,,
P33,TIE,,I/O,,,,,,,,,,
P34,spi_sclk,O,I/O,OUTPUT,,,,,,,,,
P35,spi_mosi,O,I/O,OUTPUT,,,,,,,,,
P36,TIE,,I/O,,,,,,,,,,
P37,spi_miso<3>,I,I/O,INPUT,,,,,,,,,
P38,spi_miso<2>,I,I/O,INPUT,,,,,,,,,
P39,spi_int<2>,I,I/O/GSR,INPUT,,,,,,,,,
P40,spi_int<1>,I,I/O/GTS2,INPUT,,,,,,,,,
P41,VCC,,VCCINT,,,,,,,,,,
P42,spi_int<0>,I,I/O/GTS1,INPUT,,,,,,,,,
P43,spi_miso<1>,I,I/O,INPUT,,,,,,,,,
P44,spi_miso<0>,I,I/O,INPUT,,,,,,,,,
To preserve the pinout above for future design iterations in
Project Navigator simply execute the (Lock Pins) process
located under the (Implement Design) process in a toolbox named
(Optional Implementation Tools) or invoke PIN2UCF from the
command line. The location constraints will be written into your
specified UCF file
1 Release 6.1i - Fit G.38
2 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3 5- 6-2017 5:27PM
4 NOTE: This file is designed to be imported into a spreadsheet program
5 such as Microsoft Excel for viewing, printing and sorting. The comma ','
6 character is used as the data field separator.
7 This file is also designed to support parsing.
8 Input file: spi6502b.ngd
9 output file: spi6502b_pad.csv
10 Part type: xc9572xl
11 Speed grade: -10
12 Package: pc44
13 Pinout by Pin Number:
14 -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
15 Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,{blank},Slew Rate,Termination,{blank},Voltage,Constraint,
16 P1,spi_int<3>,I,I/O,INPUT,,,,,,,,,
17 P2,cpu_d<0>,I/O,I/O,BIDIR,,,,,,,,,
18 P3,cpu_d<1>,I/O,I/O,BIDIR,,,,,,,,,
19 P4,cpu_d<2>,I/O,I/O,BIDIR,,,,,,,,,
20 P5,cpu_Nphi2,I,I/O/GCK1,INPUT,,,,,,,,,
21 P6,extclk,I,I/O/GCK2,INPUT,,,,,,,,,
22 P7,cpu_rnw,I,I/O/GCK3,INPUT,,,,,,,,,
23 P8,cpu_d<3>,I/O,I/O,BIDIR,,,,,,,,,
24 P9,cpu_d<4>,I/O,I/O,BIDIR,,,,,,,,,
25 P10,GND,,GND,,,,,,,,,,
26 P11,cpu_d<5>,I/O,I/O,BIDIR,,,,,,,,,
27 P12,cpu_d<6>,I/O,I/O,BIDIR,,,,,,,,,
28 P13,cpu_d<7>,I/O,I/O,BIDIR,,,,,,,,,
29 P14,cpu_Nirq,O,I/O,OUTPUT,,,,,,,,,
30 P15,TDI,,TDI,,,,,,,,,,
31 P16,TMS,,TMS,,,,,,,,,,
32 P17,TCK,,TCK,,,,,,,,,,
33 P18,Ncs2,I,I/O,INPUT,,,,,,,,,
34 P19,cpu_Nres,I,I/O,INPUT,,,,,,,,,
35 P20,cs1,I,I/O,INPUT,,,,,,,,,
36 P21,VCC,,VCCINT,,,,,,,,,,
37 P22,cpu_a<0>,I,I/O,INPUT,,,,,,,,,
38 P23,GND,,GND,,,,,,,,,,
39 P24,cpu_a<1>,I,I/O,INPUT,,,,,,,,,
40 P25,spi_Nsel<3>,O,I/O,OUTPUT,,,,,,,,,
41 P26,spi_Nsel<2>,O,I/O,OUTPUT,,,,,,,,,
42 P27,spi_Nsel<1>,O,I/O,OUTPUT,,,,,,,,,
43 P28,spi_Nsel<0>,O,I/O,OUTPUT,,,,,,,,,
44 P29,diag,O,I/O,OUTPUT,,,,,,,,,
45 P30,TDO,,TDO,,,,,,,,,,
46 P31,GND,,GND,,,,,,,,,,
47 P32,VCC,,VCCIO,,,,,,,,,,
48 P33,TIE,,I/O,,,,,,,,,,
49 P34,spi_sclk,O,I/O,OUTPUT,,,,,,,,,
50 P35,spi_mosi,O,I/O,OUTPUT,,,,,,,,,
51 P36,TIE,,I/O,,,,,,,,,,
52 P37,spi_miso<3>,I,I/O,INPUT,,,,,,,,,
53 P38,spi_miso<2>,I,I/O,INPUT,,,,,,,,,
54 P39,spi_int<2>,I,I/O/GSR,INPUT,,,,,,,,,
55 P40,spi_int<1>,I,I/O/GTS2,INPUT,,,,,,,,,
56 P41,VCC,,VCCINT,,,,,,,,,,
57 P42,spi_int<0>,I,I/O/GTS1,INPUT,,,,,,,,,
58 P43,spi_miso<1>,I,I/O,INPUT,,,,,,,,,
59 P44,spi_miso<0>,I,I/O,INPUT,,,,,,,,,
60 To preserve the pinout above for future design iterations in
61 Project Navigator simply execute the (Lock Pins) process
62 located under the (Implement Design) process in a toolbox named
63 (Optional Implementation Tools) or invoke PIN2UCF from the
64 command line. The location constraints will be written into your
65 specified UCF file

0
tmperr.err Normal file
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6
userlang.tpl Normal file
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[Verilog.User Templates]
type=folder
[VHDL.User Templates]
type=folder
[ABEL.User Templates]
type=folder