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AppleIISd
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Fixes according to IIgs Tech Note #68

This commit is contained in:
freitz85 2017-10-13 23:04:38 +02:00
parent eeb0b14725
commit 723406657e
5 changed files with 657 additions and 606 deletions
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60
VHDL/AddressDecoder.vhd
View File

@ -31,43 +31,67 @@ use IEEE.STD_LOGIC_1164.ALL;
entity AddressDecoder is
Port ( A : in std_logic_vector (10 downto 8);
B : out std_logic_vector (10 downto 8);
B : out std_logic_vector (10 downto 8); -- to EPROM
CLK : in std_logic;
PHI0 : in std_logic;
RNW : in std_logic;
NDEV_SEL : in std_logic;
NIO_SEL : in std_logic;
NIO_STB : in std_logic;
NDEV_SEL : in std_logic; -- $C0n0 - $C0nF
NIO_SEL : in std_logic; -- $Cs00 - $CsFF
NIO_STB : in std_logic; -- $C800 - $CFFF
NRESET : in std_logic;
DATA_EN : out std_logic;
NG : out std_logic;
NOE : out std_logic);
DATA_EN : out std_logic; -- to CPLD
NG : out std_logic; -- to bus transceiver
NOE : out std_logic); -- to EPROM
end AddressDecoder;
architecture Behavioral of AddressDecoder is
signal cfxx : std_logic;
signal cfxx : std_logic; -- $C800 - $CFFF disable
signal noe_int : std_logic;
signal ncs : std_logic;
signal ndev_sel_int : std_logic;
signal nio_sel_int : std_logic;
signal nio_stb_int : std_logic;
signal ncs : std_logic; -- $C800 - $CFFF enabled
begin
-- According to Apple IIgs Tech Note #68
-- in order to prevent bus fights with video data,
-- data from peripheral to CPU shall be valid on the bus
-- only from the first rising edge of 7M when any select
-- line is low (Phi0 high) to the falling edge of Phi0
B <= A when (NIO_STB = '0') else (others => '0');
DATA_EN <= RNW and not NDEV_SEL;
NG <= NDEV_SEL and noe_int;
NOE <= noe_int;
noe_int <= not RNW or not NDEV_SEL
or (NIO_SEL and NIO_STB)
or (NIO_SEL and ncs);
DATA_EN <= RNW and not ndev_sel_int and PHI0;
NG <= (ndev_sel_int and noe_int) or not PHI0;
NOE <= noe_int or not PHI0;
noe_int <= not RNW or not ndev_sel_int
or (nio_sel_int and nio_stb_int)
or (nio_sel_int and ncs);
cfxx <= A(8) and A(9) and A(10) and not NIO_STB;
cfxx <= A(8) and A(9) and A(10) and not nio_stb_int;
process(NRESET, NIO_SEL, cfxx)
process(NRESET, nio_sel_int, cfxx)
begin
if (NRESET = '0' or cfxx = '1') then
ncs <= '1';
elsif falling_edge(NIO_SEL) then
elsif falling_edge(nio_sel_int) then
ncs <= '0';
end if;
end process;
process(NRESET, CLK)
begin
if(NRESET = '0') then
ndev_sel_int <= '1';
nio_sel_int <= '1';
nio_stb_int <= '1';
elsif rising_edge(CLK) then
ndev_sel_int <= NDEV_SEL;
nio_sel_int <= NIO_SEL;
nio_stb_int <= NIO_STB;
end if;
end process;
end Behavioral;

68
VHDL/AddressDecoder_Test.vhd
View File

@ -43,6 +43,8 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
PORT(
A : IN std_logic_vector(10 downto 8);
B : OUT std_logic_vector(10 downto 8);
CLK : IN std_logic;
PHI0 : IN std_logic;
RNW : IN std_logic;
NDEV_SEL : IN std_logic;
NIO_SEL : IN std_logic;
@ -62,12 +64,17 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
signal NIO_SEL : std_logic := '1';
signal NIO_STB : std_logic := '1';
signal NRESET : std_logic := '1';
signal CLK : std_logic := '0';
signal PHI0 : std_logic := '1';
--Outputs
signal B : std_logic_vector(10 downto 8);
signal DATA_EN : std_logic;
signal NG : std_logic;
signal NOE : std_logic;
-- Clock period definitions
constant CLK_period : time := 142 ns;
BEGIN
@ -75,6 +82,8 @@ BEGIN
uut: AddressDecoder PORT MAP (
A => A,
B => B,
CLK => CLK,
PHI0 => PHI0,
RNW => RNW,
NDEV_SEL => NDEV_SEL,
NIO_SEL => NIO_SEL,
@ -85,50 +94,77 @@ BEGIN
NOE => NOE
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
PHI0_process :process(CLK)
variable counter : integer range 0 to 7;
begin
if rising_edge(CLK) or falling_edge(CLK) then
counter := counter + 1;
if counter = 7 then
PHI0 <= not PHI0;
counter := 0;
end if;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 50 ns;
-- hold reset state.
wait for CLK_period * 10;
NRESET <= '0';
wait for 50 ns;
wait for CLK_period * 20;
NRESET <= '1';
wait for 50 ns;
wait for CLK_period * 10;
-- insert stimulus here
-- CPLD access
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
wait for 10 ns;
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for 20 ns;
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- CnXX access
NIO_SEL <= '0';
wait for 10 ns;
wait until falling_edge(PHI0);
NIO_SEL <= '1';
wait for 20 ns;
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- C8xx access, selected
NIO_STB <= '0';
wait for 10 ns;
wait until falling_edge(PHI0);
NIO_STB <= '1';
wait for 20 ns;
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- CPLD access
NDEV_SEL <= '0';
wait for 10 ns;
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for 20 ns;
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- CFFF access
A <= "111";
NIO_STB <= '0';
wait for 10 ns;
wait until falling_edge(PHI0);
A <= "000";
NIO_STB <= '1';
wait for 20 ns;
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- C8xx access, unselected
NIO_STB <= '0';
wait for 10 ns;
wait until falling_edge(PHI0);
NIO_STB <= '1';
wait for 20 ns;
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
wait;
end process;

1110
VHDL/AppleIISd.jed
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File diff suppressed because it is too large Load Diff

23
VHDL/AppleIISd.vhd
View File

@ -70,9 +70,7 @@ architecture Behavioral of AppleIISd is
signal card_int : std_logic;
signal miso_int : std_logic;
signal rnw_int : std_logic;
signal data_en : std_logic;
signal ndev_sel_int : std_logic;
component SpiController is
Port (
@ -98,6 +96,8 @@ component AddressDecoder
Port (
A : in std_logic_vector (10 downto 8);
B : out std_logic_vector (10 downto 8);
CLK : in std_logic;
PHI0 : in std_logic;
RNW : in std_logic;
NDEV_SEL : in std_logic;
NIO_SEL : in std_logic;
@ -113,7 +113,7 @@ begin
spi: SpiController port map(
data_in => data_in,
data_out => data_out,
is_read => rnw_int,
is_read => RNW,
nreset => NRESET,
addr => addr_low_int,
phi0 => PHI0,
@ -131,8 +131,10 @@ begin
addDec: AddressDecoder port map(
A => ADD_HIGH,
B => B,
CLK => CLK,
PHI0 => PHI0,
RNW => RNW,
NDEV_SEL => ndev_sel_int,
NDEV_SEL => NDEV_SEL,
NIO_SEL => NIO_SEL,
NIO_STB => NIO_STB,
NRESET => NRESET,
@ -144,27 +146,16 @@ begin
ctrl_latch: process(CLK, NRESET)
begin
if(NRESET = '0') then
rnw_int <= '1';
wp_int <= '1';
card_int <= '1';
miso_int <= '1';
elsif falling_edge(CLK) then
rnw_int <= RNW;
wp_int <= WP;
card_int <= CARD;
miso_int <= MISO;
end if;
end process;
process(CLK, NRESET)
begin
if(NRESET = '0') then
ndev_sel_int <= '1';
elsif rising_edge(CLK) then
ndev_sel_int <= NDEV_SEL;
end if;
end process;
DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
-- synthesis translate_off
@ -175,9 +166,9 @@ begin
data_latch: process(CLK)
begin
if falling_edge(CLK) then
addr_low_int <= ADD_LOW;
if (NDEV_SEL = '0') then
data_in <= DATA;
addr_low_int <= ADD_LOW;
end if;
end if;
end process;

2
VHDL/AppleIISd_Test.vhd
View File

@ -76,7 +76,7 @@ ARCHITECTURE behavior OF AppleIISd_Test IS
signal NDEV_SEL : std_logic := '1';
signal NIO_SEL : std_logic := '1';
signal NIO_STB : std_logic := '1';
signal PHI0 : std_logic := '0';
signal PHI0 : std_logic := '1';
signal NRESET : std_logic := '1';
signal RNW : std_logic := '1';
signal MISO : std_logic := '1';