Apple-2-HW/AppleIISd
1
0
Fork 1
mirror of https://github.com/freitz85/AppleIISd.git synced 2025-02-15 08:31:10 +00:00
Code Issues Projects Releases Wiki Activity

Synthesis guards for debug signals

Browse Source
This commit is contained in:
freitz85 2017-10-10 21:58:22 +02:00
parent 2e4ebd9ac0
commit 74c6b83b4e
3 changed files with 495 additions and 488 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
VHDL/AppleIISd.xise
View File

@ -21,17 +21,17 @@
</file> </file>
<file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC"> <file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="IO.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="IO.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="IO_Test.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="IO_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
</file> </file>
</files> </files>
@ -149,7 +149,7 @@
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/IO_Test/uut" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/IO_Test/uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work." xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.IO" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
@ -159,7 +159,7 @@
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work." xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.IO" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@ -173,9 +173,9 @@
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Global Clocks" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Global Output Enables" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Global Set/Reset" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/> <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
@ -194,7 +194,7 @@
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|IO_Test|behavior" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|IO|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>

952
VHDL/IO.jed
View File

File diff suppressed because it is too large Load Diff

13
VHDL/IO.vhd
View File

@ -52,10 +52,14 @@ Port (
MOSI : out std_logic; MOSI : out std_logic;
NSEL : out std_logic; NSEL : out std_logic;
SCLK : out std_logic; SCLK : out std_logic;
WP : in std_logic; WP : in std_logic
-- synthesis translate_off
;
data_dbg : out std_logic_vector (7 downto 0); data_dbg : out std_logic_vector (7 downto 0);
add_dbg : out std_logic_vector (1 downto 0) add_dbg : out std_logic_vector (1 downto 0)
-- synthesis translate_on
); );
end IO; end IO;
@ -163,8 +167,11 @@ begin
end process; end process;
DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
data_dbg <= data_in;
add_dbg <= addr_low_int; -- synthesis translate_off
--data_dbg <= data_in;
--add_dbg <= addr_low_int;
-- synthesis translate_on
data_latch: process(CLK) data_latch: process(CLK)
begin begin