Test bench added

VHDL/AppleIISd.xise

@@ -20,24 +20,24 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="20"/>
-    </file>
     <file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="25"/>
     </file>
     <file xil_pn:name="IO.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
+    <file xil_pn:name="IO_Test.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
+    </file>
   </files>
 
   <properties>
@@ -152,18 +152,18 @@
     <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AppleIISd_Test/uut" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/IO_Test" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AppleIISd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.IO_Test" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="100 us" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="20 us" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AppleIISd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.IO_Test" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -198,7 +198,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd_Test|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|IO_Test|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>

VHDL/IO_Test.vhd

@@ -0,0 +1,206 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   00:42:59 10/10/2017
+-- Design Name:   
+-- Module Name:   U:/AppleIISd/VHDL/IO_Test.vhd
+-- Project Name:  AppleIISd
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: IO
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+ 
+ENTITY IO_Test IS
+END IO_Test;
+ 
+ARCHITECTURE behavior OF IO_Test IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT IO
+    PORT(
+         ADD_HIGH : IN  std_logic_vector(10 downto 8);
+         ADD_LOW : IN  std_logic_vector(1 downto 0);
+         B10 : OUT  std_logic;
+         B9 : OUT  std_logic;
+         B8 : OUT  std_logic;
+         CARD : IN  std_logic;
+         DATA : INOUT  std_logic_vector(7 downto 0);
+         CLK : IN  std_logic;
+         LED : OUT  std_logic;
+         NDEV_SEL : IN  std_logic;
+         NG : OUT  std_logic;
+         NIO_SEL : IN  std_logic;
+         NIO_STB : IN  std_logic;
+         NOE : OUT  std_logic;
+         PHI0 : IN  std_logic;
+         NRESET : IN  std_logic;
+         RNW : IN  std_logic;
+         MISO : IN  std_logic;
+         MOSI : OUT  std_logic;
+         NSEL : OUT  std_logic;
+         SCLK : OUT  std_logic;
+         WP : IN  std_logic
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal ADD_HIGH : std_logic_vector(10 downto 8) := (others => 'U');
+   signal ADD_LOW : std_logic_vector(1 downto 0) := (others => 'U');
+   signal CARD : std_logic := '0';
+   signal CLK : std_logic := '0';
+   signal NDEV_SEL : std_logic := '1';
+   signal NIO_SEL : std_logic := '1';
+   signal NIO_STB : std_logic := '1';
+   signal PHI0 : std_logic := '0';
+   signal NRESET : std_logic := '1';
+   signal RNW : std_logic := '1';
+   signal MISO : std_logic := '1';
+   signal WP : std_logic := '0';
+
+	--BiDirs
+   signal DATA : std_logic_vector(7 downto 0) := (others => 'Z');
+
+ 	--Outputs
+   signal B10 : std_logic;
+   signal B9 : std_logic;
+   signal B8 : std_logic;
+   signal LED : std_logic;
+   signal NG : std_logic;
+   signal NOE : std_logic;
+   signal MOSI : std_logic;
+   signal NSEL : std_logic;
+   signal SCLK : std_logic;
+
+   -- Clock period definitions
+   constant CLK_period : time := 142 ns;
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: IO PORT MAP (
+          ADD_HIGH => ADD_HIGH,
+          ADD_LOW => ADD_LOW,
+          B10 => B10,
+          B9 => B9,
+          B8 => B8,
+          CARD => CARD,
+          DATA => DATA,
+          CLK => CLK,
+          LED => LED,
+          NDEV_SEL => NDEV_SEL,
+          NG => NG,
+          NIO_SEL => NIO_SEL,
+          NIO_STB => NIO_STB,
+          NOE => NOE,
+          PHI0 => PHI0,
+          NRESET => NRESET,
+          RNW => RNW,
+          MISO => MISO,
+          MOSI => MOSI,
+          NSEL => NSEL,
+          SCLK => SCLK,
+          WP => WP
+        );
+
+   -- Clock process definitions
+   CLK_process :process
+   begin
+		CLK <= '0';
+		wait for CLK_period/2;
+		CLK <= '1';
+		wait for CLK_period/2;
+   end process;
+ 
+   PHI0_process :process(CLK)
+   variable counter : integer range 0 to 7;
+   begin
+        if rising_edge(CLK) or falling_edge(CLK) then
+            counter := counter + 1;
+            if counter = 7 then
+                PHI0 <= not PHI0;
+                counter := 0;
+            end if;
+        end if;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      -- hold reset state.
+      wait for CLK_period * 20;	
+      NRESET <= '0';
+      wait for CLK_period * 20;
+      NRESET <= '1';
+      wait for CLK_period * 10;
+      
+      -- read reg 0
+      wait until falling_edge(PHI0);
+      wait for 300 ns;
+      ADD_LOW <= (others => '0');
+      RNW <= '1';
+      DATA <= (others => 'U');
+      wait until rising_edge(PHI0);
+      NDEV_SEL <= '0';
+      DATA <= (others => 'Z');
+      wait until falling_edge(PHI0);
+      NDEV_SEL <= '1';
+      wait for 15 ns;
+      ADD_LOW <= (others => 'U');
+      
+      -- read reg 3
+      wait until falling_edge(PHI0);
+      wait for 300 ns;
+      ADD_LOW <= (others => '1');
+      RNW <= '1';
+      DATA <= (others => 'U');
+      wait until rising_edge(PHI0);
+      NDEV_SEL <= '0';
+      DATA <= (others => 'Z');
+      wait until falling_edge(PHI0);
+      NDEV_SEL <= '1';
+      wait for 15 ns;
+      ADD_LOW <= (others => 'U');
+      
+      -- send data
+      wait until falling_edge(PHI0);
+      wait for 300 ns;
+      ADD_LOW <= (others => '0');
+      RNW <= '0';
+      wait until rising_edge(PHI0);
+      NDEV_SEL <= '0';
+      DATA <= (others => '0');
+      wait until falling_edge(PHI0);
+      NDEV_SEL <= '1';
+      wait for CLK_period;
+      ADD_LOW <= (others => 'U');
+      RNW <= '1';
+      DATA <= (others => 'Z');
+      wait;
+   end process;
+
+END;