Apple-2-HW
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AppleIISd
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Test bench

This commit is contained in:
freitz85 2017-10-10 00:41:31 +02:00
parent caa40196d7
commit c03bc37834
4 changed files with 28 additions and 23 deletions
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6
VHDL/AppleIISd.vhd
View File

@ -72,14 +72,14 @@ architecture Behavioral of AppleIISd is
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
signal slavesel: std_logic; -- slave select output (0=selected)
signal slavesel: std_logic := '1'; -- slave select output (0=selected)
signal int_miso: std_logic;
--------------------------
-- helper signals
-- shift engine
signal start_shifting: std_logic; -- shifting data
signal shifting2: std_logic; -- shifting data
signal start_shifting: std_logic := '0'; -- shifting data
signal shifting2: std_logic := '0'; -- shifting data
signal shiftdone: std_logic; -- shifting data done
signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)

10
VHDL/AppleIISd.xise
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@ -31,11 +31,11 @@
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="IO.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
</files>
@ -152,14 +152,14 @@
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/io_buffers/XLXI_17" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AppleIISd_Test/uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AppleIISd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="100 us" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
@ -198,7 +198,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd_Test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>

34
VHDL/AppleIISd_Test.vhd
View File

@ -61,7 +61,7 @@ ARCHITECTURE behavior OF AppleIISd_Test IS
--Inputs
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal data_in : std_logic_vector(7 downto 0) := (others => '1');
signal is_read : std_logic := '0';
signal reset : std_logic := '0';
signal addr : std_logic_vector(1 downto 0) := (others => '0');
@ -112,30 +112,36 @@ BEGIN
wait for clk_period/2;
end process;
phi0_process :process
phi0_process :process(clk)
variable counter : integer range 0 to 7;
begin
phi0 <= '1';
wait for clk_period/14;
phi0 <= '0';
wait for clk_period/14;
if rising_edge(clk) or falling_edge(clk) then
counter := counter + 1;
if counter = 7 then
phi0 <= not phi0;
counter := 0;
end if;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- hold reset state.
wait for clk_period * 20;
reset <= '1';
wait for 100 ns;
wait for clk_period * 20;
reset <= '0';
wait for clk_period*10;
wait for clk_period * 5;
wait until rising_edge(phi0);
-- insert stimulus here
selected <= '1';
data_in <= (others => '1');
wait for clk_period * 7;
wait for clk_period;
data_in <= (others => '0');
wait until falling_edge(phi0);
selected <= '0';
wait for clk_period * 10;
wait for clk_period;
data_in <= (others => '1');
wait;
end process;

1
VHDL/sch2HdlBatchFile
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@ -1 +0,0 @@
sch2hdl,-intstyle,ise,-family,xc9500xl,-flat,-suppress,-vhdl,U:/AppleIISd/VHDL/AddressDecoder.vhf,-w,U:/AppleIISd/VHDL/AddressDecoder.sch