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AppleIISd
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Fix for unintended PGMEN usage

This commit is contained in:
Florian Reitz 2020-08-12 11:49:53 +02:00
parent 320602e692
commit 95e3c94914
7 changed files with 100 additions and 101 deletions
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2
.gitignore vendored
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@ -219,3 +219,5 @@ VHDL/_pace\.ucf
VHDL/AppleIISd\.tim
VHDL/AppleIISd\.jed
Firmware/AppleIISd.bin

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1
Firmware/src/AppleIISd.inc
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@ -48,7 +48,6 @@ KNOWNRTS := $FF58
OAPPLE := $C061 ; open apple key
DATA := $C080
CTRL := DATA+1
DIV := DATA+2
SS := DATA+3
; Constants

18
Firmware/src/AppleIISd.s
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@ -1,10 +1,10 @@
;*******************************
;
; Apple][Sd Firmware
; Version 1.2.1
; Version 1.2.2
; Main source
;
; (c) Florian Reitz, 2017 - 2018
; (c) Florian Reitz, 2017 - 2020
;
; X register usually contains SLOT16
; Y register is used for counting or SLOT
@ -228,13 +228,9 @@ DRIVER: CLC ; ProDOS entry
;*******************************
.segment "EXTROM"
INIT: LDA #$03 ; set SPI mode 3
STA CTRL,X
LDA SS,X
ORA #SS0 ; set CS high
INIT: STZ CTRL,X ; reset SPI controller
LDA #SS0 ; set CS high
STA SS,X
LDA #7 ; set 400 kHz
STA DIV,X
LDY #10
LDA #DUMMY
@ -362,13 +358,13 @@ INIT: LDA #$03 ; set SPI mode 3
@END1: LDA SS,X ; set CS high
ORA #SS0
STA SS,X
LDA #0 ; set div to 2
STA DIV,X
TYA ; retval in A
RTS
TEXT: .asciiz " Apple][Sd v1.2.1 (c)2018 Florian Reitz "
TEXT: .asciiz " Apple][Sd v1.2.2 (c)2020 Florian Reitz"
.assert(*-TEXT)=40, error, "TEXT must be 40 bytes long"
CMD0: .byt $40, $00, $00
.byt $00, $00, $95

2
README.md
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@ -112,6 +112,8 @@ The control registers of the *AppleIISd* are mapped to the usual I/O space at **
**DATA** SPI data register - Is used for both input and output. When the register is written to, the controller will output the byte on the SPI bus. When it is read from, it reflects the data that was received over the SPI bus.
**PGMEN** Program Enable - Enable programing of the internal firmware eeprom. Should be reset immediately after writing to the device.
**ECE** External Clock Enable - This bit enables the the external clock input to the SPI controller. In the *AppleIISd*, this effectively switches the SPI clock between 500kHz (ECE = 0) and 3.5MHz (ECE = 1).
**FRX** Fast Receive mode - When set to 1, fast receive mode triggers shifting upon reading or writing the SPI Data register. When set to 0, shifting is only triggered by writing the SPI data register.