Apple-2-HW
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AppleIISd
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Removed BUFG constraint warnings

This commit is contained in:
freitz85 2017-10-09 23:35:52 +02:00
parent b888590d11
commit caa40196d7
7 changed files with 599 additions and 593 deletions
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BIN
VHDL/AppleIISd.ipf
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16
VHDL/AppleIISd.ucf
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@ -1,18 +1,20 @@
#PACE: Start of Constraints generated by PACE
NET "DATA<2>" BUFG = DATA_GATE ;
NET "DATA<3>" BUFG = DATA_GATE ;
NET "DATA<4>" BUFG = DATA_GATE ;
#PACE: Start of PACE I/O Pin Assignments
NET "A10" LOC = "P38" ;
NET "A8" LOC = "P36" ;
NET "A9" LOC = "P37" ;
NET "A0" LOC = "P19" ;
NET "A1" LOC = "P18" ;
NET "ADD_HIGH<10>" LOC = "P38" ;
NET "ADD_HIGH<8>" LOC = "P36" ;
NET "ADD_HIGH<9>" LOC = "P37" ;
NET "ADD_LOW<0>" LOC = "P19" ;
NET "ADD_LOW<1>" LOC = "P18" ;
NET "B10" LOC = "P22" ;
NET "B8" LOC = "P26" ;
NET "B9" LOC = "P27" ;
NET "CARD" LOC = "P33" ;
NET "DATA<0>" LOC = "P3" ;
NET "DATA<1>" LOC = "P4" ;
NET "DATA<2>" LOC = "P5" ;
NET "DATA<2>" LOC = "P5" ;
NET "DATA<3>" LOC = "P6" ;
NET "DATA<4>" LOC = "P7" ;
NET "DATA<5>" LOC = "P9" ;

3
VHDL/AppleIISd.vhd
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@ -91,8 +91,7 @@ architecture Behavioral of AppleIISd is
begin
--led <= not (inited);
led <= not bsy;
--led <= not (bsy or not slavesel);
led <= not (bsy or not slavesel);
bsy <= start_shifting or shifting2;
process(start_shifting, shiftdone, shiftclk)

12
VHDL/AppleIISd.xise
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@ -54,7 +54,7 @@
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="90" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@ -87,7 +87,7 @@
<property xil_pn:name="Hierarchy Separator" xil_pn:value="_" xil_pn:valueState="non-default"/>
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|IO|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="IO.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/IO" xil_pn:valueState="non-default"/>
@ -105,7 +105,7 @@
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
@ -177,9 +177,9 @@
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>

9
VHDL/AppleIISd_Test.vhd
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@ -127,10 +127,15 @@ BEGIN
wait for 100 ns;
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
-- insert stimulus here
selected <= '1';
data_in <= (others => '1');
wait for clk_period * 7;
selected <= '0';
wait for clk_period * 10;
wait;
end process;

1152
VHDL/AppleIISd.jed → VHDL/IO.jed
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0
VHDL/IO.tim Normal file
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