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removed unnecessary Xilinx files

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freitz85 2017-07-05 19:32:25 +02:00
parent ef10d991fe
commit cb9891374f
147 changed files with 0 additions and 12566 deletions
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0
.untf
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0
VHDL/SPI6502B.cel
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27
VHDL/SPI6502B.lfp
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# begin LFP file C:\sources\AppleIISd\SPI6502B.lfp
designfile spi6502b.ngd
IO_GROUP "spi_Nsel" ;
IO_GROUP "spi_miso" ;
IO_GROUP "spi_int" ;
IO_GROUP "cpu_d" ;
IO_GROUP "cpu_a" ;
NET "spi_sclk" COLOR=6 ;
NET "spi_mosi" COLOR=6 ;
NET "Ncs2" COLOR=6 ;
NET "extclk" COLOR=6 ;
NET "cpu_rnw" COLOR=6 ;
NET "cpu_Nres" COLOR=6 ;
NET "cpu_Nphi2" COLOR=6 ;
NET "cpu_Nirq" COLOR=6 ;
NET "cpu_d<7>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<6>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<5>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<4>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<3>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<2>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<1>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_d<0>" COLOR=6 IO_GROUP="cpu_d" ;
NET "cpu_a<1>" COLOR=6 IO_GROUP="cpu_a" ;
NET "cpu_a<0>" COLOR=6 IO_GROUP="cpu_a" ;
INST "spi_mosi_OBUFE" COLOR=7 ;
INST "cpu_Nirq_OBUFE" COLOR=8 ;

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VHDL/SPI6502B.ucf.untf
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VHDL/_pace.ucf
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#net "diag" loc="P29";
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "A10" LOC = "P38" ;
NET "A10_B" LOC = "P25" ;
NET "A8" LOC = "P36" ;
NET "A8_B" LOC = "P27" ;
NET "A9" LOC = "P37" ;
NET "A9_B" LOC = "P26" ;
NET "cpu_a<0>" LOC = "P22" ;
NET "cpu_a<1>" LOC = "P24" ;
NET "cpu_d<0>" LOC = "P2" ;
NET "cpu_d<1>" LOC = "P3" ;
NET "cpu_d<2>" LOC = "P4" ;
NET "cpu_d<3>" LOC = "P8" ;
NET "cpu_d<4>" LOC = "P9" ;
NET "cpu_d<5>" LOC = "P11" ;
NET "cpu_d<6>" LOC = "P12" ;
NET "cpu_d<7>" LOC = "P13" ;
NET "cpu_Nirq" LOC = "P14" ;
NET "cpu_Nphi2" LOC = "P5" ;
NET "cpu_Nres" LOC = "P19" ;
NET "cpu_rnw" LOC = "P7" ;
NET "extclk" LOC = "P6" ;
NET "IO_SEL" LOC = "P40" ;
NET "IO_STB" LOC = "P43" ;
NET "led" LOC = "P29" ;
NET "Ncs2" LOC = "P18" ;
NET "OE" LOC = "P1" ;
NET "spi_int" LOC = "P42" ;
NET "spi_miso" LOC = "P44" ;
NET "spi_mosi" LOC = "P35" ;
NET "spi_Nsel" LOC = "P28" ;
NET "spi_sclk" LOC = "P34" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

0
address_decoder.sch → VHDL/address_decoder.sch
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VHDL/spi65.cdf
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JedecChain;
FileRevision(JESDxxA);
/* NoviceMode */
/* Active Mode BS */
/* Mode BS */
/* Cable PlatformCableUSB usb21 6000000 */
P ActionCode(Cfg)
Device
PartName(xc9572xl)
File("C:\sources\spi65\spi6502b.jed")
;
/* Mode SS */
/* Mode SM */
/* Mode BSFILE */
/* Mode HW140 */
ChainEnd;

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VHDL/spi65.dhp
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XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.2e
$91x4>763-Xnzd}foo8#5+72(-k0=989971304g<9=<=5;=841c851011?9<;=o415567623:?k0=99:410;13g<9=3:94>855c851?381>?95o415;74=31>;k0=97626711=g<9=32>:;=58:8EweoFhgnn6O}ciMan`es{01I`bmdTxrf=>EHEDC_XHJ8;BPFEQCC02Ida}Gasuc8Akrn|pCeyo4Eovjp|Hfelh0JdbjDdrfjau?3OcgiCobec9EmicHjcFby64FhnfTdroi2Lb`h]jrwgpe>OikeoiBle8:KmwqHfel<0@BOKEE:8Hdh`}hmnn6Bfbscq}Kgjm8;0@dl}as{Ppdrbeld55Berqbc`ue3YkhglijN`of=>Vfzzo_e`k;;Qcqp<=V}hfbjdk}f:QSM337:K;%=#xgd018WUO1=98I=#?!vif.5506;2Y[E;;?2C3-5+pol$;;;<=4SQK5154E9';%zej"10627>UWA??;>O?!1/tk`(76=890_]G9510A5+7)~an&=?<>3:QSM337:K;%=#xgd,31745<[YC=9=<M1/3-rmb*9?8:?6]_I7736G7)9'|ch ?93018WUO1=98I=#?!vif.5266;2Y[E;;?2C3-5+pol$;<=<?4SQK5154E9';%zej"2038WUO1=98I=#?!vif.744<[YC=9=<M1/3-rmb*;=;97^^F6421F4(6&bo!>;>2:QSM337:K;%=#xgd,6157=TX@<><?L>.0,ula+3;880_]G9510A5+7)~an&4??=;RRJ2065J8$:"{fk-915?Vcu~lyi7Yk|tWg`pjttj2^d|KgceMkpp==Rf`~Em`kk;TqfWqgsmdoex~?k;YKOMK^*PMH+<#?/SUWA$5(6(HYHED84Xe`\Ma773QnfS@oeosTfvvohf8:0TicPMhllvScu{`ee;6okd^ffgg=flmUoin#>76d8eabumzyThhm`ddp27>gcl{oxRjjcnffv(7?9890mij}erq\``ehllx&=5<>3:cg`wct{Vnnobjjr/hk`41<imnyi~}Pddal``t)ban&=:7>7:cg`wct{Vnnobjjr/hk`(7?8:1j`ao4bdjbrliuieo0nhfnvhmqei+69;o0nhfnvhmqei+6:9o0nhfnvhmqei+6:1o0nhfnvhmqei+6>1o0nhfnvhmqei+6??n0nhfnvhmqei+38m1iieoyinpbh(2?k2hndlxfosco)=b<jlbjzda}am/;<==eagnJ~nfn;ckm`@hsa}si7ogadQc`odab<2cnihl4ioaoqac*992i7d`lltff)471j2ceoa{ke,310g=nfjf~hh#>65`8mkek}mo&=:<n;hl`hpbb%:<27d`lltff)1g<agigyik"45c8mkek}mo&4964ochJjack2yhc}kNrbjLfoe<{je{iKgceN`ig>udgyoGeckAul48wlkwdl20}g9510ag>uwa??;>o#>10a8wuo1=98i!<?6c:qsm337:k':>:m4sqk5154e%8<<o6}i7736g+6?<h0}g9510a)6?e3zzb:8>=b,64e>uwa??;>o#8b:qsm337:k'3;h5|te]okbodW8;=8<<4suf\hjankVediaee58qvc*993<7x}j-0333>stm$;:;:5zsd/25=1<}zo&=?;8;tqf)441?2xi ?9569vw`+6>?=0y~k"1614?pub%8=?:6{|e,142>stm$93:6{|e,662>stm$>=96{|e,76?pub%?<0y~k"8448qvc*0?wKL};l;AB{21<A28o1=v]>0;47>4<6;:k;;?4=a863k5b281e?k4=;%1g>6e<uZl1:94>:010e5152;k28<5\1c850?7=9:9j<:<52`;76>Ua2?>1=7?<3`246?4flk<0_<l56582>454i9=96?okf`9Pb?03280:?>o?7381e`0f3Z;i6;:51;307d6di38h>8o4Sg850?7=9:9j<no52e2f2>U6j3<?6<4>32c3gg<69o8<7^h56582>454i9ii6<<?bb9P5g<1<3;1=>=n0e`95addm2Ym6;:51;307d6cj3;nm=;4S0`921<62898m<<>:3c17g=Tn3<?6<4>32c264<5i;>:7^?m:7695?74;h;n57<;b438Wc<1<3;1=>=n1d;961c212Y:n78;:08276g6mh0:;=9i;Rd921<62898m<kn:0;406=T9k0=87?5121b5`g=90h;?6]i:7695?74;h;nm7?6b078W4d=>=0:6<=<c7c4>7b7mh1Xj78;:08276e1i>09h87:;R3a>32=93;8?n9?a;060d4<[o0=87?5121`35g=:<>i86]>b;47>4<6;:i<<l4=57g3?V`=>=0:6<=<c62b>73c181X=o494;39565d?9k1>::i2:Qe>32=93;8?n9?a;0424c<[8h1:94>:010g2b62;k;=l5\f;47>4<6;:i<h<4=a14b?a03290:6?u\11850?7=9:9j<:<52`;74>h183h=7B=6:19L53<73L9h7>51;394~U683<?6<4>32a4`4<5i9;j7c?l:09a6`<7290>6=ua6282?kc=92E8;7>4$0d94>"6=38?7)?8:19'67<73-8:6l5@1583?J7?291D:?4>{|`6f?6=83:1<v`93;debc`ano1ei7<?0:M03?6<G:h1>vs@1d83?xd013:1<7>50zl57?463go1==>4O2594>"6l3?=7)<?:7d8 75=<11D984?;N41>4}zG831=vsrb6c94?6=83:pb;=5239ma?7782E8;7>4$0f913=#:90<<6*=3;6;?J32291D:?4>{|M2=?7|uth=m7>50;294~h1;39;7ck52:M03?6<,891:85@d;28K34=9rwD=44>{|a0`<7290:6=ua62866>hb2=1D?:4?;%a90<=#;10;7)?<:778K47=82E:>7>4O4694>I1:3;pqB8>:0y~f17=83:1<7>tn719=1=im320C>950:&2e?273-9j69<4O4694>I2;3:0C;<51zL24<6stwvqpxI4783>4<629qX==494;39565d?m;1>l>>b:l2g?7<j==1<7>52;2xj35=92dn6<5@3683?!7a291/=84;5:&23?6<,;81<6*=1;`8K42=82E:47>4O7095~{e<:0;6=4?:1ym26<63go1>6A<7;28 45=<;1Dh7>4O7095~{zj=>1<7>50;2xj35=92dn695@3683?!e=<;1/?54?;%30>14<G8;1<6A>2;28K02=82E=>7?t}N42>4}zutwvqMNL{4a922>fkoimqMNM{1CDU}H:00996A=c;0f?J4d2:90C>?5249L77<5i2E8:7<:;N14>7g<G:h1>85@3b81e>I3:38>7B:<:2f8K1>=:<1D844<d:M64?2d3F??69m4O4c90f=H=k0>96sO@

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VHDL/spi6502b._hrpt
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Up-to-date

61
VHDL/spi6502b.gyd
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Pin Freeze File: version G.38
9572XL44PC XC9572XL-10-PC44
Ncs2 S:PIN18
a10 S:PIN38
a8 S:PIN36
a9 S:PIN37
cpu_Nphi2 S:PIN5
cpu_Nres S:PIN19
cpu_a<0> S:PIN22
cpu_a<1> S:PIN24
cpu_rnw S:PIN7
extclk S:PIN6
nio_sel S:PIN40
nio_stb S:PIN43
spi_int S:PIN42
spi_miso S:PIN44
b10 S:PIN27
b8 S:PIN25
b9 S:PIN26
cpu_Nirq S:PIN39
cpu_d<0> S:PIN2
cpu_d<1> S:PIN3
cpu_d<2> S:PIN4
cpu_d<3> S:PIN8
cpu_d<4> S:PIN9
cpu_d<5> S:PIN11
cpu_d<6> S:PIN12
cpu_d<7> S:PIN13
spi_mosi S:PIN35
spi_sclk S:PIN34
led S:PIN29
ng S:PIN20
noe S:PIN14
spi_Nsel S:PIN28
;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.
PARTITION FB1_1 spidataout<3> spidataout<2> spidataout<1> spidataout<0>
int_dout<0> int_dout<1> tmo int_dout<2>
slaveinten frx ece divisor<2>
divisor<1> divisor<0> int_dout<3> cpol
int_dout<4> cpha
PARTITION FB2_1 EXP6_ int_mosi shifting2 tc
shiftcnt<0> $OpTx$INV$24__$INT spidatain<7> spidatain<6>
cpu_Nirq_OBUFE spidatain<5> spidatain<4> spidatain<3>
spidatain<2>
PARTITION FB2_18 start_shifting/start_shifting_RSTF__$INT
PARTITION FB3_2 int_dout<5>
PARTITION FB3_5 int_dout<6>
PARTITION FB3_8 int_dout<7> noe_OBUF
PARTITION FB3_15 ng_OBUF
PARTITION FB3_17 add_dec/XLXN_11 cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
PARTITION FB4_1 shiftdone b8_OBUF start_shifting spidataout<7>
b9_OBUF spidataout<6> spidataout<5> b10_OBUF
spidataout<4> spidatain<1> slavesel spidatain<0>
shiftcnt<3> led_OBUF shiftcnt<2> shiftcnt<1>
int_sclk ier

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VHDL/spi6502b.imp
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VHDL/spi6502b.jed
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VHDL/spi6502b.mfd
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MDF Database: version 1.0
MDF_INFO | spi6502b | XC9572XL-10-PC44
MACROCELL | 1 | 1 | int_mosi
ATTRIBUTES | 8652706 | 0
INPUTS | 12 | shiftcnt<3> | shiftcnt<2> | shiftcnt<1> | shiftdone | spidataout<4> | shifting2 | spidataout<0> | EXP6_.EXP | shifting2.EXP | $OpTx$INV$24__$INT | cpu_Nres | tmo
INPUTMC | 11 | 3 | 12 | 3 | 14 | 3 | 15 | 3 | 0 | 3 | 8 | 1 | 2 | 0 | 3 | 1 | 0 | 1 | 2 | 1 | 5 | 0 | 6
INPUTP | 1 | 49
IMPORTS | 2 | 1 | 0 | 1 | 2
EQ | 21 |
!spi_mosi.D = shiftcnt<3> & shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<0> & shifting2
# !shiftcnt<3> & shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<4> & shifting2
;Imported pterms FB2_1
# shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<2> & shifting2
# shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<3> & shifting2
# !shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<5> & shifting2
# !shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<6> & shifting2
# !shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<7> & shifting2
;Imported pterms FB2_3
# shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<1> & shifting2;
spi_mosi.CLK = !$OpTx$INV$24__$INT;
spi_mosi.AP = !cpu_Nres;
spi_mosi.OE = !tmo;
MACROCELL | 3 | 10 | slavesel
ATTRIBUTES | 4588514 | 0
OUTPUTMC | 4 | 3 | 10 | 3 | 11 | 0 | 4 | 3 | 13
INPUTS | 7 | spi_Nsel | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 10
INPUTP | 6 | 59 | 52 | 12 | 46 | 49 | 24
EQ | 5 |
spi_Nsel.T = spi_Nsel & cpu_a<1> & cpu_a<0> & !cpu_d<0>.PIN
# !spi_Nsel & cpu_a<1> & cpu_a<0> & cpu_d<0>.PIN;
spi_Nsel.CLK = Ncs2;
spi_Nsel.AP = !cpu_Nres;
spi_Nsel.CE = !cpu_rnw;
MACROCELL | 0 | 15 | cpol
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 0 | 15 | 3 | 16 | 0 | 5
INPUTS | 7 | cpol | cpu_a<1> | cpu_a<0> | cpu_d<1>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 15
INPUTP | 6 | 59 | 52 | 13 | 46 | 49 | 24
EQ | 5 |
cpol.T = cpol & !cpu_a<1> & cpu_a<0> & !cpu_d<1>.PIN
# !cpol & !cpu_a<1> & cpu_a<0> & cpu_d<1>.PIN;
cpol.CLK = Ncs2;
cpol.AR = !cpu_Nres;
cpol.CE = !cpu_rnw;
MACROCELL | 0 | 10 | ece
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 0 | 10 | 0 | 7 | 1 | 5
INPUTS | 7 | ece | cpu_a<1> | cpu_a<0> | cpu_d<2>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 10
INPUTP | 6 | 59 | 52 | 15 | 46 | 49 | 24
EQ | 5 |
ece.T = ece & !cpu_a<1> & cpu_a<0> & !cpu_d<2>.PIN
# !ece & !cpu_a<1> & cpu_a<0> & cpu_d<2>.PIN;
ece.CLK = Ncs2;
ece.AR = !cpu_Nres;
ece.CE = !cpu_rnw;
MACROCELL | 0 | 17 | cpha
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 4 | 0 | 17 | 3 | 16 | 0 | 4 | 3 | 15
INPUTS | 7 | cpha | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 17
INPUTP | 6 | 59 | 52 | 12 | 46 | 49 | 24
EQ | 5 |
cpha.T = cpha & !cpu_a<1> & cpu_a<0> & !cpu_d<0>.PIN
# !cpha & !cpu_a<1> & cpu_a<0> & cpu_d<0>.PIN;
cpha.CLK = Ncs2;
cpha.AR = !cpu_Nres;
cpha.CE = !cpu_rnw;
MACROCELL | 0 | 9 | frx
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 0 | 9 | 3 | 2 | 0 | 16
INPUTS | 7 | frx | cpu_a<1> | cpu_a<0> | cpu_d<4>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 9
INPUTP | 6 | 59 | 52 | 27 | 46 | 49 | 24
EQ | 5 |
frx.T = frx & !cpu_a<1> & cpu_a<0> & !cpu_d<4>.PIN
# !frx & !cpu_a<1> & cpu_a<0> & cpu_d<4>.PIN;
frx.CLK = Ncs2;
frx.AR = !cpu_Nres;
frx.CE = !cpu_rnw;
MACROCELL | 3 | 17 | ier
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 3 | 17 | 2 | 4 | 2 | 17
INPUTS | 7 | ier | cpu_a<1> | cpu_a<0> | cpu_d<6>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 17
INPUTP | 6 | 59 | 52 | 31 | 46 | 49 | 24
EQ | 5 |
ier.T = ier & !cpu_a<1> & cpu_a<0> & !cpu_d<6>.PIN
# !ier & !cpu_a<1> & cpu_a<0> & cpu_d<6>.PIN;
ier.CLK = Ncs2;
ier.AR = !cpu_Nres;
ier.CE = !cpu_rnw;
MACROCELL | 0 | 8 | slaveinten
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 0 | 8 | 0 | 16 | 2 | 17
INPUTS | 7 | slaveinten | cpu_a<1> | cpu_a<0> | cpu_d<4>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 8
INPUTP | 6 | 59 | 52 | 27 | 46 | 49 | 24
EQ | 5 |
slaveinten.T = slaveinten & cpu_a<1> & cpu_a<0> & !cpu_d<4>.PIN
# !slaveinten & cpu_a<1> & cpu_a<0> & cpu_d<4>.PIN;
slaveinten.CLK = Ncs2;
slaveinten.AR = !cpu_Nres;
slaveinten.CE = !cpu_rnw;
MACROCELL | 0 | 6 | tmo
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 1 | 1 | 0 | 6 | 0 | 14
INPUTS | 7 | tmo | cpu_a<1> | cpu_a<0> | cpu_d<3>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 6
INPUTP | 6 | 59 | 52 | 26 | 46 | 49 | 24
EQ | 5 |
tmo.T = tmo & !cpu_a<1> & cpu_a<0> & !cpu_d<3>.PIN
# !tmo & !cpu_a<1> & cpu_a<0> & cpu_d<3>.PIN;
tmo.CLK = Ncs2;
tmo.AR = !cpu_Nres;
tmo.CE = !cpu_rnw;
MACROCELL | 0 | 13 | divisor<0>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 2 | 0 | 13 | 0 | 4
INPUTS | 7 | divisor<0> | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 13
INPUTP | 6 | 59 | 52 | 12 | 46 | 49 | 24
EQ | 5 |
divisor<0>.T = divisor<0> & cpu_a<1> & !cpu_a<0> & !cpu_d<0>.PIN
# !divisor<0> & cpu_a<1> & !cpu_a<0> & cpu_d<0>.PIN;
divisor<0>.CLK = Ncs2;
divisor<0>.AR = !cpu_Nres;
divisor<0>.CE = !cpu_rnw;
MACROCELL | 0 | 12 | divisor<1>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 2 | 0 | 12 | 0 | 5
INPUTS | 7 | divisor<1> | cpu_a<1> | cpu_a<0> | cpu_d<1>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 12
INPUTP | 6 | 59 | 52 | 13 | 46 | 49 | 24
EQ | 5 |
divisor<1>.T = divisor<1> & cpu_a<1> & !cpu_a<0> & !cpu_d<1>.PIN
# !divisor<1> & cpu_a<1> & !cpu_a<0> & cpu_d<1>.PIN;
divisor<1>.CLK = Ncs2;
divisor<1>.AR = !cpu_Nres;
divisor<1>.CE = !cpu_rnw;
MACROCELL | 0 | 11 | divisor<2>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 2 | 0 | 11 | 0 | 7
INPUTS | 7 | divisor<2> | cpu_a<1> | cpu_a<0> | cpu_d<2>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 11
INPUTP | 6 | 59 | 52 | 15 | 46 | 49 | 24
EQ | 5 |
divisor<2>.T = divisor<2> & cpu_a<1> & !cpu_a<0> & !cpu_d<2>.PIN
# !divisor<2> & cpu_a<1> & !cpu_a<0> & cpu_d<2>.PIN;
divisor<2>.CLK = Ncs2;
divisor<2>.AR = !cpu_Nres;
divisor<2>.CE = !cpu_rnw;
MACROCELL | 3 | 11 | spidatain<0>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 3 | 9 | 0 | 4
INPUTS | 6 | spi_Nsel | spi_miso | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 3 | 10 | 1 | 5 | 1 | 4 | 1 | 2
INPUTP | 2 | 10 | 49
EQ | 4 |
spidatain<0>.D = !spi_Nsel & spi_miso;
spidatain<0>.CLK = !$OpTx$INV$24__$INT;
spidatain<0>.AR = !cpu_Nres;
spidatain<0>.CE = shiftcnt<0> & shifting2;
MACROCELL | 3 | 9 | spidatain<1>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 1 | 12 | 0 | 5
INPUTS | 5 | spidatain<0> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 3 | 11 | 1 | 5 | 1 | 4 | 1 | 2
INPUTP | 1 | 49
EQ | 4 |
spidatain<1>.D = spidatain<0>;
spidatain<1>.CLK = !$OpTx$INV$24__$INT;
spidatain<1>.AR = !cpu_Nres;
spidatain<1>.CE = shiftcnt<0> & shifting2;
MACROCELL | 1 | 12 | spidatain<2>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 1 | 11 | 0 | 7
INPUTS | 5 | spidatain<1> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 3 | 9 | 1 | 5 | 1 | 4 | 1 | 2
INPUTP | 1 | 49
EQ | 4 |
spidatain<2>.D = spidatain<1>;
spidatain<2>.CLK = !$OpTx$INV$24__$INT;
spidatain<2>.AR = !cpu_Nres;
spidatain<2>.CE = shiftcnt<0> & shifting2;
MACROCELL | 1 | 11 | spidatain<3>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 1 | 10 | 0 | 14
INPUTS | 5 | spidatain<2> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 1 | 12 | 1 | 5 | 1 | 4 | 1 | 2
INPUTP | 1 | 49
EQ | 4 |
spidatain<3>.D = spidatain<2>;
spidatain<3>.CLK = !$OpTx$INV$24__$INT;
spidatain<3>.AR = !cpu_Nres;
spidatain<3>.CE = shiftcnt<0> & shifting2;
MACROCELL | 1 | 10 | spidatain<4>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 1 | 9 | 0 | 16
INPUTS | 5 | spidatain<3> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 1 | 11 | 1 | 5 | 1 | 4 | 1 | 2
INPUTP | 1 | 49
EQ | 4 |
spidatain<4>.D = spidatain<3>;
spidatain<4>.CLK = !$OpTx$INV$24__$INT;
spidatain<4>.AR = !cpu_Nres;
spidatain<4>.CE = shiftcnt<0> & shifting2;
MACROCELL | 1 | 9 | spidatain<5>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 1 | 7 | 2 | 1
INPUTS | 5 | spidatain<4> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 1 | 10 | 1 | 5 | 1 | 4 | 1 | 2
INPUTP | 1 | 49
EQ | 4 |
spidatain<5>.D = spidatain<4>;
spidatain<5>.CLK = !$OpTx$INV$24__$INT;
spidatain<5>.AR = !cpu_Nres;
spidatain<5>.CE = shiftcnt<0> & shifting2;
MACROCELL | 1 | 7 | spidatain<6>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 2 | 1 | 6 | 2 | 4
INPUTS | 5 | spidatain<5> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 1 | 9 | 1 | 5 | 1 | 4 | 1 | 2
INPUTP | 1 | 49
EQ | 4 |
spidatain<6>.D = spidatain<5>;
spidatain<6>.CLK = !$OpTx$INV$24__$INT;
spidatain<6>.AR = !cpu_Nres;
spidatain<6>.CE = shiftcnt<0> & shifting2;
MACROCELL | 1 | 6 | spidatain<7>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 1 | 2 | 7
INPUTS | 5 | spidatain<6> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2
INPUTMC | 4 | 1 | 7 | 1 | 5 | 1 | 4 | 1 | 2
INPUTP | 1 | 49
EQ | 4 |
spidatain<7>.D = spidatain<6>;
spidatain<7>.CLK = !$OpTx$INV$24__$INT;
spidatain<7>.AR = !cpu_Nres;
spidatain<7>.CE = shiftcnt<0> & shifting2;
MACROCELL | 3 | 16 | int_sclk
ATTRIBUTES | 8651698 | 0
INPUTS | 8 | cpol | cpu_Nres | cpha | shiftcnt<0> | shiftdone | shifting2 | $OpTx$INV$24__$INT | shiftcnt<1>.EXP
INPUTMC | 7 | 0 | 15 | 0 | 17 | 1 | 4 | 3 | 0 | 1 | 2 | 1 | 5 | 3 | 15
INPUTP | 1 | 49
IMPORTS | 1 | 3 | 15
EQ | 9 |
spi_sclk.D = cpol
$ cpu_Nres & !cpha & shiftcnt<0> & !shiftdone &
shifting2
;Imported pterms FB4_16
# cpu_Nres & cpha & !shiftcnt<0> & !shiftdone &
shifting2;
spi_sclk.CLK = !$OpTx$INV$24__$INT;
spi_sclk.AP = !cpu_Nres & cpol;
spi_sclk.AR = !cpu_Nres & !cpol;
MACROCELL | 0 | 14 | int_dout<3>
ATTRIBUTES | 265986 | 0
INPUTS | 7 | Ncs2 | cpu_rnw | spidatain<3> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | tmo
INPUTMC | 2 | 1 | 11 | 0 | 6
INPUTP | 5 | 46 | 24 | 59 | 52 | 20
EQ | 5 |
cpu_d<3> = !Ncs2 & cpu_rnw & tmo & !cpu_a<1> & cpu_a<0> &
cpu_Nphi2
# !Ncs2 & cpu_rnw & spidatain<3> & !cpu_a<1> &
!cpu_a<0> & cpu_Nphi2;
cpu_d<3>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
MACROCELL | 2 | 1 | int_dout<5>
ATTRIBUTES | 265986 | 0
INPUTS | 8 | Ncs2 | cpu_rnw | cpu_a<1> | start_shifting | cpu_a<0> | cpu_Nphi2 | shifting2 | spidatain<5>
INPUTMC | 3 | 3 | 2 | 1 | 2 | 1 | 9
INPUTP | 5 | 46 | 24 | 59 | 52 | 20
EQ | 7 |
cpu_d<5> = !Ncs2 & cpu_rnw & spidatain<5> & !cpu_a<1> &
!cpu_a<0> & cpu_Nphi2
# !Ncs2 & cpu_rnw & !cpu_a<1> & start_shifting &
cpu_a<0> & cpu_Nphi2
# !Ncs2 & cpu_rnw & !cpu_a<1> & cpu_a<0> &
shifting2 & cpu_Nphi2;
cpu_d<5>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
MACROCELL | 2 | 4 | int_dout<6>
ATTRIBUTES | 265986 | 0
INPUTS | 7 | Ncs2 | cpu_rnw | spidatain<6> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | ier
INPUTMC | 2 | 1 | 7 | 3 | 17
INPUTP | 5 | 46 | 24 | 59 | 52 | 20
EQ | 5 |
cpu_d<6> = !Ncs2 & cpu_rnw & ier & !cpu_a<1> & cpu_a<0> &
cpu_Nphi2
# !Ncs2 & cpu_rnw & spidatain<6> & !cpu_a<1> &
!cpu_a<0> & cpu_Nphi2;
cpu_d<6>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
MACROCELL | 2 | 7 | int_dout<7>
ATTRIBUTES | 265986 | 0
INPUTS | 7 | Ncs2 | cpu_rnw | spidatain<7> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | tc
INPUTMC | 2 | 1 | 6 | 1 | 3
INPUTP | 5 | 46 | 24 | 59 | 52 | 20
EQ | 5 |
cpu_d<7> = !Ncs2 & cpu_rnw & spidatain<7> & !cpu_a<1> &
!cpu_a<0> & cpu_Nphi2
# !Ncs2 & cpu_rnw & !cpu_a<1> & tc & cpu_a<0> &
cpu_Nphi2;
cpu_d<7>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
MACROCELL | 3 | 12 | shiftcnt<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 5 | 1 | 1 | 3 | 12 | 3 | 0 | 1 | 0 | 1 | 2
INPUTS | 7 | shiftcnt<2> | shiftcnt<0> | shiftcnt<1> | shifting2 | shiftcnt<3> | $OpTx$INV$24__$INT | cpu_Nres
INPUTMC | 6 | 3 | 14 | 1 | 4 | 3 | 15 | 1 | 2 | 3 | 12 | 1 | 5
INPUTP | 1 | 49
EQ | 5 |
shiftcnt<3>.T = shiftcnt<3> & !shifting2
# shiftcnt<2> & shiftcnt<0> & shiftcnt<1> &
shifting2;
shiftcnt<3>.CLK = !$OpTx$INV$24__$INT;
shiftcnt<3>.AR = !cpu_Nres;
MACROCELL | 3 | 14 | shiftcnt<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 6 | 1 | 1 | 3 | 12 | 3 | 14 | 3 | 0 | 1 | 0 | 1 | 2
INPUTS | 6 | shiftcnt<0> | shiftcnt<1> | shifting2 | shiftcnt<2> | $OpTx$INV$24__$INT | cpu_Nres
INPUTMC | 5 | 1 | 4 | 3 | 15 | 1 | 2 | 3 | 14 | 1 | 5
INPUTP | 1 | 49
EQ | 4 |
shiftcnt<2>.T = shiftcnt<2> & !shifting2
# shiftcnt<0> & shiftcnt<1> & shifting2;
shiftcnt<2>.CLK = !$OpTx$INV$24__$INT;
shiftcnt<2>.AR = !cpu_Nres;
MACROCELL | 1 | 4 | shiftcnt<0>
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 14 | 3 | 11 | 3 | 9 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 7 | 1 | 6 | 3 | 16 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 3 | 0
INPUTS | 4 | shiftcnt<0> | shifting2 | $OpTx$INV$24__$INT | cpu_Nres
INPUTMC | 3 | 1 | 4 | 1 | 2 | 1 | 5
INPUTP | 1 | 49
EQ | 3 |
shiftcnt<0>.D = !shiftcnt<0> & shifting2;
shiftcnt<0>.CLK = !$OpTx$INV$24__$INT;
shiftcnt<0>.AR = !cpu_Nres;
MACROCELL | 3 | 15 | shiftcnt<1>
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 8 | 1 | 1 | 3 | 12 | 3 | 14 | 3 | 15 | 3 | 0 | 1 | 0 | 1 | 2 | 3 | 16
INPUTS | 7 | shiftcnt<0> | shiftcnt<1> | shifting2 | $OpTx$INV$24__$INT | cpu_Nres | cpha | shiftdone
INPUTMC | 6 | 1 | 4 | 3 | 15 | 1 | 2 | 1 | 5 | 0 | 17 | 3 | 0
INPUTP | 1 | 49
EXPORTS | 1 | 3 | 16
EQ | 6 |
shiftcnt<1>.D = shiftcnt<0> & !shiftcnt<1> & shifting2
# !shiftcnt<0> & shiftcnt<1> & shifting2;
shiftcnt<1>.CLK = !$OpTx$INV$24__$INT;
shiftcnt<1>.AR = !cpu_Nres;
shiftcnt<1>.EXP = cpu_Nres & cpha & !shiftcnt<0> & !shiftdone &
shifting2
MACROCELL | 3 | 0 | shiftdone
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 7 | 1 | 1 | 3 | 16 | 1 | 3 | 1 | 2 | 1 | 17 | 1 | 0 | 3 | 15
INPUTS | 6 | shiftcnt<3> | shiftcnt<2> | shiftcnt<0> | shiftcnt<1> | $OpTx$INV$24__$INT | cpu_Nres
INPUTMC | 5 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 1 | 5
INPUTP | 1 | 49
EQ | 4 |
shiftdone.D = shiftcnt<3> & shiftcnt<2> & shiftcnt<0> &
shiftcnt<1>;
shiftdone.CLK = !$OpTx$INV$24__$INT;
shiftdone.AR = !cpu_Nres;
MACROCELL | 3 | 2 | start_shifting
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 5 | 2 | 1 | 3 | 2 | 1 | 2 | 3 | 13 | 1 | 5
INPUTS | 7 | frx | cpu_a<1> | start_shifting | cpu_a<0> | cpu_rnw | Ncs2 | start_shifting/start_shifting_RSTF__$INT
INPUTMC | 3 | 0 | 9 | 3 | 2 | 1 | 17
INPUTP | 4 | 59 | 52 | 24 | 46
EQ | 4 |
start_shifting.T = !cpu_rnw & !cpu_a<1> & !start_shifting & !cpu_a<0>
# frx & !cpu_a<1> & !start_shifting & !cpu_a<0>;
start_shifting.CLK = Ncs2;
start_shifting.AR = !start_shifting/start_shifting_RSTF__$INT;
MACROCELL | 1 | 3 | tc
ATTRIBUTES | 8520672 | 0
OUTPUTMC | 2 | 2 | 7 | 2 | 17
INPUTS | 4 | Ncs2 | shiftdone | cpu_a<1> | cpu_a<0>
INPUTMC | 1 | 3 | 0
INPUTP | 3 | 46 | 59 | 52
EQ | 4 |
tc.D = Gnd;
tc.CLK = Ncs2;
tc.AP = shiftdone;
tc.CE = !cpu_a<1> & !cpu_a<0>;
MACROCELL | 0 | 3 | spidataout<0>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 1 | 1 | 0 | 3
INPUTS | 7 | cpu_a<1> | spidataout<0> | cpu_a<0> | cpu_d<0>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 3
INPUTP | 6 | 59 | 52 | 12 | 46 | 49 | 24
EQ | 6 |
spidataout<0>.T = !cpu_a<1> & spidataout<0> & !cpu_a<0> &
!cpu_d<0>.PIN
# !cpu_a<1> & !spidataout<0> & !cpu_a<0> &
cpu_d<0>.PIN;
spidataout<0>.CLK = Ncs2;
spidataout<0>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 0 | 2 | spidataout<1>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 0 | 2 | 1 | 2
INPUTS | 7 | cpu_a<1> | spidataout<1> | cpu_a<0> | cpu_d<1>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 2
INPUTP | 6 | 59 | 52 | 13 | 46 | 49 | 24
EQ | 6 |
spidataout<1>.T = !cpu_a<1> & spidataout<1> & !cpu_a<0> &
!cpu_d<1>.PIN
# !cpu_a<1> & !spidataout<1> & !cpu_a<0> &
cpu_d<1>.PIN;
spidataout<1>.CLK = Ncs2;
spidataout<1>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 0 | 1 | spidataout<2>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 1 | 0 | 0 | 1
INPUTS | 7 | cpu_a<1> | spidataout<2> | cpu_a<0> | cpu_d<2>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 1
INPUTP | 6 | 59 | 52 | 15 | 46 | 49 | 24
EQ | 6 |
spidataout<2>.T = !cpu_a<1> & spidataout<2> & !cpu_a<0> &
!cpu_d<2>.PIN
# !cpu_a<1> & !spidataout<2> & !cpu_a<0> &
cpu_d<2>.PIN;
spidataout<2>.CLK = Ncs2;
spidataout<2>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 0 | 0 | spidataout<3>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 1 | 0 | 0 | 0
INPUTS | 7 | cpu_a<1> | spidataout<3> | cpu_a<0> | cpu_d<3>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 0 | 0
INPUTP | 6 | 59 | 52 | 26 | 46 | 49 | 24
EQ | 6 |
spidataout<3>.T = !cpu_a<1> & spidataout<3> & !cpu_a<0> &
!cpu_d<3>.PIN
# !cpu_a<1> & !spidataout<3> & !cpu_a<0> &
cpu_d<3>.PIN;
spidataout<3>.CLK = Ncs2;
spidataout<3>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 3 | 8 | spidataout<4>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 1 | 1 | 3 | 8
INPUTS | 7 | cpu_a<1> | spidataout<4> | cpu_a<0> | cpu_d<4>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 8
INPUTP | 6 | 59 | 52 | 27 | 46 | 49 | 24
EQ | 6 |
spidataout<4>.T = !cpu_a<1> & spidataout<4> & !cpu_a<0> &
!cpu_d<4>.PIN
# !cpu_a<1> & !spidataout<4> & !cpu_a<0> &
cpu_d<4>.PIN;
spidataout<4>.CLK = Ncs2;
spidataout<4>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 3 | 6 | spidataout<5>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 1 | 0 | 3 | 6
INPUTS | 7 | cpu_a<1> | spidataout<5> | cpu_a<0> | cpu_d<5>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 6
INPUTP | 6 | 59 | 52 | 29 | 46 | 49 | 24
EQ | 6 |
spidataout<5>.T = !cpu_a<1> & spidataout<5> & !cpu_a<0> &
!cpu_d<5>.PIN
# !cpu_a<1> & !spidataout<5> & !cpu_a<0> &
cpu_d<5>.PIN;
spidataout<5>.CLK = Ncs2;
spidataout<5>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 3 | 5 | spidataout<6>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 1 | 0 | 3 | 5
INPUTS | 7 | cpu_a<1> | spidataout<6> | cpu_a<0> | cpu_d<6>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 5
INPUTP | 6 | 59 | 52 | 31 | 46 | 49 | 24
EQ | 6 |
spidataout<6>.T = !cpu_a<1> & spidataout<6> & !cpu_a<0> &
!cpu_d<6>.PIN
# !cpu_a<1> & !spidataout<6> & !cpu_a<0> &
cpu_d<6>.PIN;
spidataout<6>.CLK = Ncs2;
spidataout<6>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 3 | 3 | spidataout<7>
ATTRIBUTES | 4326240 | 0
OUTPUTMC | 2 | 1 | 0 | 3 | 3
INPUTS | 7 | cpu_a<1> | spidataout<7> | cpu_a<0> | cpu_d<7>.PIN | Ncs2 | cpu_Nres | cpu_rnw
INPUTMC | 1 | 3 | 3
INPUTP | 6 | 59 | 52 | 33 | 46 | 49 | 24
EQ | 6 |
spidataout<7>.T = !cpu_a<1> & spidataout<7> & !cpu_a<0> &
!cpu_d<7>.PIN
# !cpu_a<1> & !spidataout<7> & !cpu_a<0> &
cpu_d<7>.PIN;
spidataout<7>.CLK = Ncs2;
spidataout<7>.CE = cpu_Nres & !cpu_rnw;
MACROCELL | 2 | 14 | ng_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | Ncs2 | nio_stb | nio_sel
INPUTP | 3 | 46 | 9 | 3
EQ | 1 |
ng = Ncs2 & nio_stb & nio_sel;
MACROCELL | 0 | 4 | int_dout<0>
ATTRIBUTES | 265986 | 0
INPUTS | 9 | Ncs2 | cpu_rnw | spidatain<0> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | divisor<0> | cpha | spi_Nsel
INPUTMC | 4 | 3 | 11 | 0 | 13 | 0 | 17 | 3 | 10
INPUTP | 5 | 46 | 24 | 59 | 52 | 20
EQ | 9 |
cpu_d<0> = !Ncs2 & cpu_rnw & spi_Nsel & cpu_a<1> &
cpu_a<0> & cpu_Nphi2
# !Ncs2 & cpu_rnw & cpha & !cpu_a<1> & cpu_a<0> &
cpu_Nphi2
# !Ncs2 & cpu_rnw & divisor<0> & cpu_a<1> &
!cpu_a<0> & cpu_Nphi2
# !Ncs2 & cpu_rnw & spidatain<0> & !cpu_a<1> &
!cpu_a<0> & cpu_Nphi2;
cpu_d<0>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
MACROCELL | 0 | 5 | int_dout<1>
ATTRIBUTES | 265986 | 0
INPUTS | 8 | Ncs2 | cpu_rnw | spidatain<1> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | cpol | divisor<1>
INPUTMC | 3 | 3 | 9 | 0 | 15 | 0 | 12
INPUTP | 5 | 46 | 24 | 59 | 52 | 20
EQ | 7 |
cpu_d<1> = !Ncs2 & cpu_rnw & cpol & !cpu_a<1> & cpu_a<0> &
cpu_Nphi2
# !Ncs2 & cpu_rnw & divisor<1> & cpu_a<1> &
!cpu_a<0> & cpu_Nphi2
# !Ncs2 & cpu_rnw & spidatain<1> & !cpu_a<1> &
!cpu_a<0> & cpu_Nphi2;
cpu_d<1>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
MACROCELL | 0 | 7 | int_dout<2>
ATTRIBUTES | 265986 | 0
INPUTS | 8 | Ncs2 | cpu_rnw | spidatain<2> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | ece | divisor<2>
INPUTMC | 3 | 1 | 12 | 0 | 10 | 0 | 11
INPUTP | 5 | 46 | 24 | 59 | 52 | 20
EQ | 7 |
cpu_d<2> = !Ncs2 & cpu_rnw & ece & !cpu_a<1> & cpu_a<0> &
cpu_Nphi2
# !Ncs2 & cpu_rnw & divisor<2> & cpu_a<1> &
!cpu_a<0> & cpu_Nphi2
# !Ncs2 & cpu_rnw & spidatain<2> & !cpu_a<1> &
!cpu_a<0> & cpu_Nphi2;
cpu_d<2>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
MACROCELL | 0 | 16 | int_dout<4>
ATTRIBUTES | 265986 | 0
INPUTS | 9 | Ncs2 | cpu_rnw | spidatain<4> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | spi_int | frx | slaveinten
INPUTMC | 3 | 1 | 10 | 0 | 9 | 0 | 8
INPUTP | 6 | 46 | 24 | 59 | 52 | 20 | 7
EQ | 9 |
cpu_d<4> = !Ncs2 & cpu_rnw & frx & !cpu_a<1> & cpu_a<0> &
cpu_Nphi2
# !Ncs2 & cpu_rnw & slaveinten & cpu_a<1> &
cpu_a<0> & cpu_Nphi2
# !Ncs2 & cpu_rnw & spidatain<4> & !cpu_a<1> &
!cpu_a<0> & cpu_Nphi2
# !Ncs2 & cpu_rnw & cpu_a<1> & !cpu_a<0> & !spi_int &
cpu_Nphi2;
cpu_d<4>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2;
MACROCELL | 1 | 2 | shifting2
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 19 | 1 | 1 | 3 | 11 | 3 | 9 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 7 | 1 | 6 | 3 | 16 | 2 | 1 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 3 | 13 | 1 | 5 | 1 | 0 | 1 | 2
INPUTS | 8 | shiftdone | start_shifting | $OpTx$INV$24__$INT | shiftcnt<3> | shiftcnt<2> | shiftcnt<1> | spidataout<1> | shifting2
INPUTMC | 8 | 3 | 0 | 3 | 2 | 1 | 5 | 3 | 12 | 3 | 14 | 3 | 15 | 0 | 2 | 1 | 2
EXPORTS | 1 | 1 | 1
EQ | 4 |
shifting2.D = !shiftdone & start_shifting;
shifting2.CLK = !$OpTx$INV$24__$INT;
shifting2.EXP = shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<1> & shifting2
MACROCELL | 2 | 16 | add_dec/XLXN_11
ATTRIBUTES | 8553216 | 0
OUTPUTMC | 1 | 2 | 8
INPUTS | 4 | nio_stb | a9 | a8 | a10
INPUTP | 4 | 9 | 89 | 88 | 90
EQ | 2 |
!add_dec/XLXN_11.D = !nio_stb & a9 & a8 & a10;
add_dec/XLXN_11.CLK = extclk; // GCK
GLOBALS | 1 | 2 | extclk
MACROCELL | 3 | 7 | b10_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | a10 | nio_sel
INPUTP | 2 | 90 | 3
EQ | 1 |
b10 = a10 & nio_sel;
MACROCELL | 3 | 1 | b8_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | a8 | nio_sel
INPUTP | 2 | 88 | 3
EQ | 1 |
b8 = a8 & nio_sel;
MACROCELL | 3 | 4 | b9_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | a9 | nio_sel
INPUTP | 2 | 89 | 3
EQ | 1 |
b9 = a9 & nio_sel;
MACROCELL | 3 | 13 | led_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | spi_Nsel | start_shifting | shifting2
INPUTMC | 3 | 3 | 10 | 3 | 2 | 1 | 2
EQ | 1 |
led = spi_Nsel & !start_shifting & !shifting2;
MACROCELL | 2 | 8 | noe_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | nio_sel | add_dec/XLXN_11 | nio_stb
INPUTMC | 1 | 2 | 16
INPUTP | 2 | 3 | 9
EQ | 2 |
!noe = !nio_stb & add_dec/XLXN_11
# !nio_sel & add_dec/XLXN_11;
MACROCELL | 1 | 8 | cpu_Nirq_OBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 1 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
INPUTMC | 1 | 2 | 17
EQ | 2 |
cpu_Nirq = Gnd;
cpu_Nirq.OE = cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST;
MACROCELL | 1 | 5 | $OpTx$INV$24__$INT
ATTRIBUTES | 133888 | 0
OUTPUTMC | 16 | 1 | 1 | 3 | 11 | 3 | 9 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 7 | 1 | 6 | 3 | 16 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 3 | 0 | 1 | 2
INPUTS | 5 | ece | cpu_Nphi2 | extclk | start_shifting | shifting2
INPUTMC | 3 | 0 | 10 | 3 | 2 | 1 | 2
INPUTP | 2 | 20 | 21
EQ | 3 |
$OpTx$INV$24__$INT = ece & !extclk
# !ece & !cpu_Nphi2
# !start_shifting & !shifting2;
MACROCELL | 1 | 17 | start_shifting/start_shifting_RSTF__$INT
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 3 | 2
INPUTS | 2 | cpu_Nres | shiftdone
INPUTMC | 1 | 3 | 0
INPUTP | 1 | 49
EQ | 1 |
start_shifting/start_shifting_RSTF__$INT = cpu_Nres & !shiftdone;
MACROCELL | 2 | 17 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 1 | 8
INPUTS | 4 | ier | tc | slaveinten | spi_int
INPUTMC | 3 | 3 | 17 | 1 | 3 | 0 | 8
INPUTP | 1 | 7
EQ | 2 |
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST = ier & tc
# slaveinten & !spi_int;
MACROCELL | 1 | 0 | EXP6_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 1 | 1
INPUTS | 10 | shiftcnt<3> | shiftcnt<2> | shiftcnt<1> | shiftdone | spidataout<2> | shifting2 | spidataout<3> | spidataout<5> | spidataout<6> | spidataout<7>
INPUTMC | 10 | 3 | 12 | 3 | 14 | 3 | 15 | 3 | 0 | 0 | 1 | 1 | 2 | 0 | 0 | 3 | 6 | 3 | 5 | 3 | 3
EXPORTS | 1 | 1 | 1
EQ | 10 |
EXP6_.EXP = shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<2> & shifting2
# shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<3> & shifting2
# !shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<5> & shifting2
# !shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> &
!shiftdone & !spidataout<6> & shifting2
# !shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> &
!shiftdone & !spidataout<7> & shifting2
PIN | cpu_Nres | 64 | 0 | N/A | 49 | 35 | 1 | 1 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 3 | 11 | 3 | 9 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 7 | 1 | 6 | 3 | 16 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 3 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 1 | 17
PIN | Ncs2 | 64 | 0 | N/A | 46 | 30 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 1 | 3 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 2 | 14 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
PIN | cpu_rnw | 64 | 0 | N/A | 24 | 28 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
PIN | cpu_a<0> | 64 | 0 | N/A | 52 | 29 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 1 | 3 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
PIN | cpu_a<1> | 64 | 0 | N/A | 59 | 29 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 1 | 3 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16
PIN | spi_miso | 64 | 0 | N/A | 10 | 1 | 3 | 11
PIN | nio_stb | 64 | 0 | N/A | 9 | 3 | 2 | 14 | 2 | 16 | 2 | 8
PIN | a9 | 64 | 0 | N/A | 89 | 2 | 2 | 16 | 3 | 4
PIN | a8 | 64 | 0 | N/A | 88 | 2 | 2 | 16 | 3 | 1
PIN | a10 | 64 | 0 | N/A | 90 | 2 | 2 | 16 | 3 | 7
PIN | cpu_Nphi2 | 64 | 0 | N/A | 20 | 9 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16 | 1 | 5
PIN | nio_sel | 64 | 0 | N/A | 3 | 5 | 2 | 14 | 3 | 7 | 3 | 1 | 3 | 4 | 2 | 8
PIN | spi_int | 64 | 0 | N/A | 7 | 2 | 0 | 16 | 2 | 17
PIN | extclk | 8256 | 0 | N/A | 21 | 2 | 1 | 5 | 2 | 16
PIN | spi_mosi | 536871040 | 0 | N/A | 87
PIN | spi_Nsel | 536871040 | 0 | N/A | 68
PIN | spi_sclk | 536871040 | 0 | N/A | 83
PIN | ng | 536871040 | 0 | N/A | 50
PIN | b10 | 536871040 | 0 | N/A | 65
PIN | b8 | 536871040 | 0 | N/A | 62
PIN | b9 | 536871040 | 0 | N/A | 63
PIN | led | 536871040 | 0 | N/A | 72
PIN | noe | 536871040 | 0 | N/A | 38
PIN | cpu_Nirq | 536871040 | 0 | N/A | 92
PIN | cpu_d<3> | 536870976 | 0 | N/A | 26 | 2 | 0 | 6 | 0 | 0
PIN | cpu_d<5> | 536870976 | 0 | N/A | 29 | 1 | 3 | 6
PIN | cpu_d<6> | 536870976 | 0 | N/A | 31 | 2 | 3 | 17 | 3 | 5
PIN | cpu_d<7> | 536870976 | 0 | N/A | 33 | 1 | 3 | 3
PIN | cpu_d<0> | 536870976 | 0 | N/A | 12 | 4 | 3 | 10 | 0 | 17 | 0 | 13 | 0 | 3
PIN | cpu_d<1> | 536870976 | 0 | N/A | 13 | 3 | 0 | 15 | 0 | 12 | 0 | 2
PIN | cpu_d<2> | 536870976 | 0 | N/A | 15 | 3 | 0 | 10 | 0 | 11 | 0 | 1
PIN | cpu_d<4> | 536870976 | 0 | N/A | 27 | 3 | 0 | 9 | 0 | 8 | 3 | 8

18
VHDL/spi6502b.pnx
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@ -1,18 +0,0 @@
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ibis [
<!ELEMENT ibis (part, pin+)>
<!ELEMENT part EMPTY>
<!ELEMENT pin EMPTY>
<!ATTLIST part
arch CDATA #REQUIRED
device CDATA #REQUIRED
spg CDATA #REQUIRED
pkg CDATA #REQUIRED>
<!ATTLIST pin
nm CDATA #REQUIRED
no CDATA #REQUIRED
iostd (TTL|LVTTL|LVCMOS2|NA) "NA"
sr (SLOW|FAST|slow|fast) "SLOW"
dir (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
]>
<ibis><part pkg="PC44" spg="-10" arch="xc9500xl" device="XC9572XL"/><pin nm="cpu_Nres" no="19" dir="input"/><pin nm="Ncs2" no="18" dir="input"/><pin nm="cpu_rnw" no="7" dir="input"/><pin nm="cpu_a&lt;0&gt;" no="22" dir="input"/><pin nm="cpu_a&lt;1&gt;" no="24" dir="input"/><pin nm="spi_miso" no="44" dir="input"/><pin nm="nio_stb" no="43" dir="input"/><pin nm="a9" no="37" dir="input"/><pin nm="a8" no="36" dir="input"/><pin nm="a10" no="38" dir="input"/><pin nm="cpu_Nphi2" no="5" dir="input"/><pin nm="nio_sel" no="40" dir="input"/><pin nm="spi_int" no="42" dir="input"/><pin nm="extclk" no="6" dir="input"/><pin nm="spi_mosi" no="35" sr="fast" dir="output"/><pin nm="spi_Nsel" no="28" sr="fast" dir="output"/><pin nm="spi_sclk" no="34" sr="fast" dir="output"/><pin nm="ng" no="20" sr="fast" dir="output"/><pin nm="b10" no="27" sr="fast" dir="output"/><pin nm="b8" no="25" sr="fast" dir="output"/><pin nm="b9" no="26" sr="fast" dir="output"/><pin nm="led" no="29" sr="fast" dir="output"/><pin nm="noe" no="14" sr="fast" dir="output"/><pin nm="cpu_Nirq" no="39" sr="fast" dir="output"/><pin nm="cpu_d&lt;3&gt;" no="8" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;5&gt;" no="11" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;6&gt;" no="12" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;7&gt;" no="13" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;0&gt;" no="2" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;1&gt;" no="3" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;2&gt;" no="4" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;4&gt;" no="9" sr="fast" dir="bidir"/></ibis>

798
VHDL/spi6502b.rpt
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@ -1,798 +0,0 @@
cpldfit: version G.38 Xilinx Inc.
Fitter Report
Design Name: spi6502b Date: 5-11-2017, 2:09AM
Device Used: XC9572XL-10-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
56 /72 ( 78%) 209 /360 ( 58%) 38 /72 ( 53%) 32 /34 ( 94%) 116/216 ( 54%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 13 13 | I/O : 26 2
Output : 10 10 | GCK/IO : 3 0
Bidirectional : 8 8 | GTS/IO : 2 0
GCK : 1 1 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 32 32
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 38
Non-registered Macrocell driving I/O 15
GLOBAL RESOURCES:
Signal 'extclk' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 56 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 56 macrocells used (MC).
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
$OpTx$INV$24__$INT 3 5 FB2_6 STD 37 I/O I
add_dec/XLXN_11 1 4 FB3_17 STD 22 I/O I RESET
b10 1 2 FB4_8 STD FAST 27 I/O O
b8 1 2 FB4_2 STD FAST 25 I/O O
b9 1 2 FB4_5 STD FAST 26 I/O O
cpha 5 7 FB1_18 STD (b) (b) RESET
cpol 5 7 FB1_16 STD (b) (b) RESET
cpu_Nirq 1 1 FB2_9 STD FAST 39 GSR/I/O O
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST 2 4 FB3_18 STD (b) (b)
cpu_d<0> 5 9 FB1_5 STD FAST 2 I/O I/O
cpu_d<1> 4 8 FB1_6 STD FAST 3 I/O I/O
cpu_d<2> 4 8 FB1_8 STD FAST 4 I/O I/O
cpu_d<3> 3 7 FB1_15 STD FAST 8 I/O I/O
cpu_d<4> 5 9 FB1_17 STD FAST 9 I/O I/O
cpu_d<5> 4 8 FB3_2 STD FAST 11 I/O I/O
cpu_d<6> 3 7 FB3_5 STD FAST 12 I/O I/O
cpu_d<7> 3 7 FB3_8 STD FAST 13 I/O I/O
divisor<0> 5 7 FB1_14 STD 7 GCK/I/O I RESET
divisor<1> 5 7 FB1_13 STD (b) (b) RESET
divisor<2> 5 7 FB1_12 STD (b) (b) RESET
ece 5 7 FB1_11 STD 6 GCK/I/O GCK/I RESET
frx 5 7 FB1_10 STD (b) (b) RESET
ier 5 7 FB4_18 STD (b) (b) RESET
led 1 3 FB4_14 STD FAST 29 I/O O
ng 1 3 FB3_15 STD FAST 20 I/O O
noe 2 3 FB3_9 STD FAST 14 I/O O
shiftcnt<0> 3 4 FB2_5 STD 36 I/O I RESET
shiftcnt<1> 4 5 FB4_16 STD (b) (b) RESET
shiftcnt<2> 4 6 FB4_15 STD 33 I/O (b) RESET
shiftcnt<3> 4 7 FB4_13 STD (b) (b) RESET
shiftdone 3 6 FB4_1 STD (b) (b) RESET
shifting2 2 3 FB2_3 STD (b) (b) RESET
slaveinten 5 7 FB1_9 STD 5 GCK/I/O I RESET
spi_Nsel 5 7 FB4_11 STD FAST 28 I/O O RESET
spi_mosi 11 16 FB2_2 STD FAST 35 I/O O RESET
spi_sclk 6 7 FB4_17 STD FAST 34 I/O O RESET
spidatain<0> 4 6 FB4_12 STD (b) (b) RESET
spidatain<1> 4 5 FB4_10 STD (b) (b) RESET
spidatain<2> 4 5 FB2_13 STD (b) (b) RESET
spidatain<3> 4 5 FB2_12 STD (b) (b) RESET
spidatain<4> 4 5 FB2_11 STD 40 GTS/I/O I RESET
spidatain<5> 4 5 FB2_10 STD (b) (b) RESET
spidatain<6> 4 5 FB2_8 STD 38 I/O I RESET
spidatain<7> 4 5 FB2_7 STD (b) (b) RESET
spidataout<0> 4 7 FB1_4 STD (b) (b) RESET
spidataout<1> 4 7 FB1_3 STD (b) (b) RESET
spidataout<2> 4 7 FB1_2 STD 1 I/O (b) RESET
spidataout<3> 4 7 FB1_1 STD (b) (b) RESET
spidataout<4> 4 7 FB4_9 STD (b) (b) RESET
spidataout<5> 4 7 FB4_7 STD (b) (b) RESET
spidataout<6> 4 7 FB4_6 STD (b) (b) RESET
spidataout<7> 4 7 FB4_4 STD (b) (b) RESET
start_shifting 4 7 FB4_3 STD (b) (b) RESET
start_shifting/start_shifting_RSTF__$INT 1 2 FB2_18 STD (b) (b)
tc 3 4 FB2_4 STD (b) (b) RESET
tmo 5 7 FB1_7 STD (b) (b) RESET
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
Ncs2 FB3_11 18 I/O I
a10 FB2_8 38 I/O I
a8 FB2_5 36 I/O I
a9 FB2_6 37 I/O I
cpu_Nphi2 FB1_9 5 GCK/I/O I
cpu_Nres FB3_14 19 I/O I
cpu_a<0> FB3_17 22 I/O I
cpu_a<1> FB3_16 24 I/O I
cpu_rnw FB1_14 7 GCK/I/O I
extclk FB1_11 6 GCK/I/O GCK/I
nio_sel FB2_11 40 GTS/I/O I
nio_stb FB2_15 43 I/O I
spi_int FB2_14 42 GTS/I/O I
spi_miso FB2_17 44 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 18 31 31 82 0/5 9
FB2 13 31 31 48 2/0 9
FB3 7 20 20 16 2/3 9
FB4 18 34 34 63 6/0 7
---- ----- ----- -----
56 209 10/8 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 31/23
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
spidataout<3> 4 0 0 1 FB1_1 STD (b) (b)
spidataout<2> 4 0 0 1 FB1_2 STD 1 I/O (b)
spidataout<1> 4 0 0 1 FB1_3 STD (b) (b)
spidataout<0> 4 0 0 1 FB1_4 STD (b) (b)
cpu_d<0> 5 0 0 0 FB1_5 STD 2 I/O I/O
cpu_d<1> 4 0 0 1 FB1_6 STD 3 I/O I/O
tmo 5 0 0 0 FB1_7 STD (b) (b)
cpu_d<2> 4 0 0 1 FB1_8 STD 4 I/O I/O
slaveinten 5 0 0 0 FB1_9 STD 5 GCK/I/O I
frx 5 0 0 0 FB1_10 STD (b) (b)
ece 5 0 0 0 FB1_11 STD 6 GCK/I/O GCK/I
divisor<2> 5 0 0 0 FB1_12 STD (b) (b)
divisor<1> 5 0 0 0 FB1_13 STD (b) (b)
divisor<0> 5 0 0 0 FB1_14 STD 7 GCK/I/O I
cpu_d<3> 3 0 0 2 FB1_15 STD 8 I/O I/O
cpol 5 0 0 0 FB1_16 STD (b) (b)
cpu_d<4> 5 0 0 0 FB1_17 STD 9 I/O I/O
cpha 5 0 0 0 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: cpu_d<0>.PIN 12: cpu_a<1> 22: spidatain<0>
2: cpu_d<1>.PIN 13: cpu_rnw 23: spidatain<1>
3: cpu_d<2>.PIN 14: divisor<0> 24: spidatain<2>
4: cpu_d<3>.PIN 15: divisor<1> 25: spidatain<3>
5: cpu_d<4>.PIN 16: divisor<2> 26: spidatain<4>
6: Ncs2 17: ece 27: spidataout<0>
7: cpha 18: frx 28: spidataout<1>
8: cpol 19: slaveinten 29: spidataout<2>
9: cpu_Nphi2 20: spi_Nsel 30: spidataout<3>
10: cpu_Nres 21: spi_int 31: tmo
11: cpu_a<0>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
spidataout<3> ...X.X...XXXX................X.......... 7 7
spidataout<2> ..X..X...XXXX...............X........... 7 7
spidataout<1> .X...X...XXXX..............X............ 7 7
spidataout<0> X....X...XXXX.............X............. 7 7
cpu_d<0> .....XX.X.XXXX.....X.X.................. 9 9
cpu_d<1> .....X.XX.XXX.X.......X................. 8 8
tmo ...X.X...XXXX.................X......... 7 7
cpu_d<2> .....X..X.XXX..XX......X................ 8 8
slaveinten ....XX...XXXX.....X..................... 7 7
frx ....XX...XXXX....X...................... 7 7
ece ..X..X...XXXX...X....................... 7 7
divisor<2> ..X..X...XXXX..X........................ 7 7
divisor<1> .X...X...XXXX.X......................... 7 7
divisor<0> X....X...XXXXX.......................... 7 7
cpu_d<3> .....X..X.XXX...........X.....X......... 7 7
cpol .X...X.X.XXXX........................... 7 7
cpu_d<4> .....X..X.XXX....XX.X....X.............. 9 9
cpha X....XX..XXXX........................... 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 31/23
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 \/5 0 FB2_1 (b) (b)
spi_mosi 11 6<- 0 0 FB2_2 STD 35 I/O O
shifting2 2 0 /\1 2 FB2_3 STD (b) (b)
tc 3 0 0 2 FB2_4 STD (b) (b)
shiftcnt<0> 3 0 0 2 FB2_5 STD 36 I/O I
$OpTx$INV$24__$INT 3 0 0 2 FB2_6 STD 37 I/O I
spidatain<7> 4 0 0 1 FB2_7 STD (b) (b)
spidatain<6> 4 0 0 1 FB2_8 STD 38 I/O I
cpu_Nirq 1 0 0 4 FB2_9 STD 39 GSR/I/O O
spidatain<5> 4 0 0 1 FB2_10 STD (b) (b)
spidatain<4> 4 0 0 1 FB2_11 STD 40 GTS/I/O I
spidatain<3> 4 0 0 1 FB2_12 STD (b) (b)
spidatain<2> 4 0 0 1 FB2_13 STD (b) (b)
(unused) 0 0 0 5 FB2_14 42 GTS/I/O I
(unused) 0 0 0 5 FB2_15 43 I/O I
(unused) 0 0 0 5 FB2_16 (b)
(unused) 0 0 0 5 FB2_17 44 I/O I
start_shifting/start_shifting_RSTF__$INT
1 0 0 4 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$INV$24__$INT
12: shiftcnt<2> 22: spidataout<0>
2: Ncs2 13: shiftcnt<3> 23: spidataout<1>
3: cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
14: shiftdone 24: spidataout<2>
4: cpu_Nphi2 15: shifting2 25: spidataout<3>
5: cpu_Nres 16: spidatain<1> 26: spidataout<4>
6: cpu_a<0> 17: spidatain<2> 27: spidataout<5>
7: cpu_a<1> 18: spidatain<3> 28: spidataout<6>
8: ece 19: spidatain<4> 29: spidataout<7>
9: extclk 20: spidatain<5> 30: start_shifting
10: shiftcnt<0> 21: spidatain<6> 31: tmo
11: shiftcnt<1>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
spi_mosi X...X.....XXXXX......XXXXXXXX.X......... 16 16
shifting2 X............X...............X.......... 3 3
tc .X...XX......X.......................... 4 4
shiftcnt<0> X...X....X....X......................... 4 4
$OpTx$INV$24__$INT ...X...XX.....X..............X.......... 5 5
spidatain<7> X...X....X....X.....X................... 5 5
spidatain<6> X...X....X....X....X.................... 5 5
cpu_Nirq ..X..................................... 1 1
spidatain<5> X...X....X....X...X..................... 5 5
spidatain<4> X...X....X....X..X...................... 5 5
spidatain<3> X...X....X....X.X....................... 5 5
spidatain<2> X...X....X....XX........................ 5 5
start_shifting/start_shifting_RSTF__$INT
....X........X.......................... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 20/34
Number of signals used by logic mapping into function block: 20
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
cpu_d<5> 4 0 0 1 FB3_2 STD 11 I/O I/O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
cpu_d<6> 3 0 0 2 FB3_5 STD 12 I/O I/O
(unused) 0 0 0 5 FB3_6 (b)
(unused) 0 0 0 5 FB3_7 (b)
cpu_d<7> 3 0 0 2 FB3_8 STD 13 I/O I/O
noe 2 0 0 3 FB3_9 STD 14 I/O O
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 18 I/O I
(unused) 0 0 0 5 FB3_12 (b)
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 19 I/O I
ng 1 0 0 4 FB3_15 STD 20 I/O O
(unused) 0 0 0 5 FB3_16 24 I/O I
add_dec/XLXN_11 1 0 0 4 FB3_17 STD 22 I/O I
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
2 0 0 3 FB3_18 STD (b) (b)
Signals Used by Logic in Function Block
1: Ncs2 8: cpu_a<1> 15: spi_int
2: a10 9: cpu_rnw 16: spidatain<5>
3: a8 10: ier 17: spidatain<6>
4: a9 11: nio_sel 18: spidatain<7>
5: add_dec/XLXN_11 12: nio_stb 19: start_shifting
6: cpu_Nphi2 13: shifting2 20: tc
7: cpu_a<0> 14: slaveinten
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
cpu_d<5> X....XXXX...X..X..X..................... 8 8
cpu_d<6> X....XXXXX......X....................... 7 7
cpu_d<7> X....XXXX........X.X.................... 7 7
noe ....X.....XX............................ 3 3
ng X.........XX............................ 3 3
add_dec/XLXN_11 .XXX.......X............................ 4 4
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
.........X...XX....X.................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 34/20
Number of signals used by logic mapping into function block: 34
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
shiftdone 3 0 0 2 FB4_1 STD (b) (b)
b8 1 0 0 4 FB4_2 STD 25 I/O O
start_shifting 4 0 0 1 FB4_3 STD (b) (b)
spidataout<7> 4 0 0 1 FB4_4 STD (b) (b)
b9 1 0 0 4 FB4_5 STD 26 I/O O
spidataout<6> 4 0 0 1 FB4_6 STD (b) (b)
spidataout<5> 4 0 0 1 FB4_7 STD (b) (b)
b10 1 0 0 4 FB4_8 STD 27 I/O O
spidataout<4> 4 0 0 1 FB4_9 STD (b) (b)
spidatain<1> 4 0 0 1 FB4_10 STD (b) (b)
spi_Nsel 5 0 0 0 FB4_11 STD 28 I/O O
spidatain<0> 4 0 0 1 FB4_12 STD (b) (b)
shiftcnt<3> 4 0 0 1 FB4_13 STD (b) (b)
led 1 0 0 4 FB4_14 STD 29 I/O O
shiftcnt<2> 4 0 0 1 FB4_15 STD 33 I/O (b)
shiftcnt<1> 4 0 \/1 0 FB4_16 STD (b) (b)
spi_sclk 6 1<- 0 0 FB4_17 STD 34 I/O O
ier 5 0 0 0 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$INV$24__$INT
13: cpu_Nres 24: shiftdone
2: cpu_d<0>.PIN 14: cpu_a<0> 25: shifting2
3: cpu_d<4>.PIN 15: cpu_a<1> 26: spi_Nsel
4: cpu_d<5>.PIN 16: cpu_rnw 27: spi_miso
5: cpu_d<6>.PIN 17: frx 28: spidatain<0>
6: cpu_d<7>.PIN 18: ier 29: spidataout<4>
7: Ncs2 19: nio_sel 30: spidataout<5>
8: a10 20: shiftcnt<0> 31: spidataout<6>
9: a8 21: shiftcnt<1> 32: spidataout<7>
10: a9 22: shiftcnt<2> 33: start_shifting
11: cpha 23: shiftcnt<3> 34: start_shifting/start_shifting_RSTF__$INT
12: cpol
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
shiftdone X...........X......XXXX................. 6 6
b8 ........X.........X..................... 2 2
start_shifting ......X......XXXX...............XX...... 7 7
spidataout<7> .....XX.....XXXX...............X........ 7 7
b9 .........X........X..................... 2 2
spidataout<6> ....X.X.....XXXX..............X......... 7 7
spidataout<5> ...X..X.....XXXX.............X.......... 7 7
b10 .......X..........X..................... 2 2
spidataout<4> ..X...X.....XXXX............X........... 7 7
spidatain<1> X...........X......X....X..X............ 5 5
spi_Nsel .X....X.....XXXX.........X.............. 7 7
spidatain<0> X...........X......X....XXX............. 6 6
shiftcnt<3> X...........X......XXXX.X............... 7 7
led ........................XX......X....... 3 3
shiftcnt<2> X...........X......XXX..X............... 6 6
shiftcnt<1> X...........X......XX...X............... 5 5
spi_sclk X.........XXX......X...XX............... 7 7
ier ....X.X.....XXXX.X...................... 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
$OpTx$INV$24__$INT <= ((ece AND NOT extclk)
OR (NOT ece AND NOT cpu_Nphi2)
OR (NOT start_shifting AND NOT shifting2));
FDCPE_add_dec/XLXN_11: FDCPE port map (add_dec/XLXN_11,add_dec/XLXN_11_D,extclk,'0','0');
add_dec/XLXN_11_D <= (NOT nio_stb AND a9 AND a8 AND a10);
b10 <= (a10 AND nio_sel);
b8 <= (a8 AND nio_sel);
b9 <= (a9 AND nio_sel);
FTCPE_cpha: FTCPE port map (cpha,cpha_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
cpha_T <= ((cpha AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(0).PIN)
OR (NOT cpha AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(0).PIN));
FTCPE_cpol: FTCPE port map (cpol,cpol_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
cpol_T <= ((cpol AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(1).PIN)
OR (NOT cpol AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(1).PIN));
cpu_Nirq_I <= '0';
cpu_Nirq <= cpu_Nirq_I when cpu_Nirq_OE = '1' else 'Z';
cpu_Nirq_OE <= cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST;
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST <= ((ier AND tc)
OR (slaveinten AND NOT spi_int));
FTCPE_divisor0: FTCPE port map (divisor(0),divisor_T(0),Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
divisor_T(0) <= ((divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(0).PIN)
OR (NOT divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(0).PIN));
FTCPE_divisor1: FTCPE port map (divisor(1),divisor_T(1),Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
divisor_T(1) <= ((divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(1).PIN)
OR (NOT divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(1).PIN));
FTCPE_divisor2: FTCPE port map (divisor(2),divisor_T(2),Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
divisor_T(2) <= ((divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(2).PIN)
OR (NOT divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(2).PIN));
FTCPE_ece: FTCPE port map (ece,ece_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
ece_T <= ((ece AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(2).PIN)
OR (NOT ece AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(2).PIN));
FTCPE_frx: FTCPE port map (frx,frx_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
frx_T <= ((frx AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(4).PIN)
OR (NOT frx AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(4).PIN));
FTCPE_ier: FTCPE port map (ier,ier_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
ier_T <= ((ier AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(6).PIN)
OR (NOT ier AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(6).PIN));
cpu_d_I(0) <= ((NOT Ncs2 AND cpu_rnw AND spi_Nsel AND cpu_a(1) AND
cpu_a(0) AND cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND cpha AND NOT cpu_a(1) AND cpu_a(0) AND
cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND divisor(0) AND cpu_a(1) AND
NOT cpu_a(0) AND cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND spidatain(0) AND NOT cpu_a(1) AND
NOT cpu_a(0) AND cpu_Nphi2));
cpu_d(0) <= cpu_d_I(0) when cpu_d_OE(0) = '1' else 'Z';
cpu_d_OE(0) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
cpu_d_I(1) <= ((NOT Ncs2 AND cpu_rnw AND cpol AND NOT cpu_a(1) AND cpu_a(0) AND
cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND divisor(1) AND cpu_a(1) AND
NOT cpu_a(0) AND cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND spidatain(1) AND NOT cpu_a(1) AND
NOT cpu_a(0) AND cpu_Nphi2));
cpu_d(1) <= cpu_d_I(1) when cpu_d_OE(1) = '1' else 'Z';
cpu_d_OE(1) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
cpu_d_I(2) <= ((NOT Ncs2 AND cpu_rnw AND ece AND NOT cpu_a(1) AND cpu_a(0) AND
cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND divisor(2) AND cpu_a(1) AND
NOT cpu_a(0) AND cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND spidatain(2) AND NOT cpu_a(1) AND
NOT cpu_a(0) AND cpu_Nphi2));
cpu_d(2) <= cpu_d_I(2) when cpu_d_OE(2) = '1' else 'Z';
cpu_d_OE(2) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
cpu_d_I(3) <= ((NOT Ncs2 AND cpu_rnw AND tmo AND NOT cpu_a(1) AND cpu_a(0) AND
cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND spidatain(3) AND NOT cpu_a(1) AND
NOT cpu_a(0) AND cpu_Nphi2));
cpu_d(3) <= cpu_d_I(3) when cpu_d_OE(3) = '1' else 'Z';
cpu_d_OE(3) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
cpu_d_I(4) <= ((NOT Ncs2 AND cpu_rnw AND frx AND NOT cpu_a(1) AND cpu_a(0) AND
cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND slaveinten AND cpu_a(1) AND
cpu_a(0) AND cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND spidatain(4) AND NOT cpu_a(1) AND
NOT cpu_a(0) AND cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND NOT spi_int AND
cpu_Nphi2));
cpu_d(4) <= cpu_d_I(4) when cpu_d_OE(4) = '1' else 'Z';
cpu_d_OE(4) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
cpu_d_I(5) <= ((NOT Ncs2 AND cpu_rnw AND spidatain(5) AND NOT cpu_a(1) AND
NOT cpu_a(0) AND cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND NOT cpu_a(1) AND start_shifting AND
cpu_a(0) AND cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND NOT cpu_a(1) AND cpu_a(0) AND
shifting2 AND cpu_Nphi2));
cpu_d(5) <= cpu_d_I(5) when cpu_d_OE(5) = '1' else 'Z';
cpu_d_OE(5) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
cpu_d_I(6) <= ((NOT Ncs2 AND cpu_rnw AND ier AND NOT cpu_a(1) AND cpu_a(0) AND
cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND spidatain(6) AND NOT cpu_a(1) AND
NOT cpu_a(0) AND cpu_Nphi2));
cpu_d(6) <= cpu_d_I(6) when cpu_d_OE(6) = '1' else 'Z';
cpu_d_OE(6) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
cpu_d_I(7) <= ((NOT Ncs2 AND cpu_rnw AND spidatain(7) AND NOT cpu_a(1) AND
NOT cpu_a(0) AND cpu_Nphi2)
OR (NOT Ncs2 AND cpu_rnw AND NOT cpu_a(1) AND tc AND cpu_a(0) AND
cpu_Nphi2));
cpu_d(7) <= cpu_d_I(7) when cpu_d_OE(7) = '1' else 'Z';
cpu_d_OE(7) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
FDCPE_spi_mosi: FDCPE port map (spi_mosi_I,spi_mosi,NOT $OpTx$INV$24__$INT,'0',NOT cpu_Nres);
spi_mosi <= ((EXP6_.EXP)
OR (shifting2.EXP)
OR (shiftcnt(3) AND shiftcnt(2) AND shiftcnt(1) AND
NOT shiftdone AND NOT spidataout(0) AND shifting2)
OR (NOT shiftcnt(3) AND shiftcnt(2) AND shiftcnt(1) AND
NOT shiftdone AND NOT spidataout(4) AND shifting2));
spi_mosi <= spi_mosi_I when spi_mosi_OE = '1' else 'Z';
spi_mosi_OE <= NOT tmo;
FDCPE_spi_sclk: FDCPE port map (spi_sclk,spi_sclk_D,NOT $OpTx$INV$24__$INT,spi_sclk_CLR,spi_sclk_PRE);
spi_sclk_D <= cpol
XOR
spi_sclk_D <= ((shiftcnt(1).EXP)
OR (cpu_Nres AND NOT cpha AND shiftcnt(0) AND NOT shiftdone AND
shifting2));
spi_sclk_CLR <= (NOT cpu_Nres AND NOT cpol);
spi_sclk_PRE <= (NOT cpu_Nres AND cpol);
led <= (spi_Nsel AND NOT start_shifting AND NOT shifting2);
ng <= (Ncs2 AND nio_stb AND nio_sel);
noe <= NOT (((NOT nio_stb AND add_dec/XLXN_11)
OR (NOT nio_sel AND add_dec/XLXN_11)));
FDCPE_shiftcnt0: FDCPE port map (shiftcnt(0),shiftcnt_D(0),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
shiftcnt_D(0) <= (NOT shiftcnt(0) AND shifting2);
FDCPE_shiftcnt1: FDCPE port map (shiftcnt(1),shiftcnt_D(1),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
shiftcnt_D(1) <= ((shiftcnt(0) AND NOT shiftcnt(1) AND shifting2)
OR (NOT shiftcnt(0) AND shiftcnt(1) AND shifting2));
FTCPE_shiftcnt2: FTCPE port map (shiftcnt(2),shiftcnt_T(2),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
shiftcnt_T(2) <= ((shiftcnt(2) AND NOT shifting2)
OR (shiftcnt(0) AND shiftcnt(1) AND shifting2));
FTCPE_shiftcnt3: FTCPE port map (shiftcnt(3),shiftcnt_T(3),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
shiftcnt_T(3) <= ((shiftcnt(3) AND NOT shifting2)
OR (shiftcnt(2) AND shiftcnt(0) AND shiftcnt(1) AND
shifting2));
FDCPE_shiftdone: FDCPE port map (shiftdone,shiftdone_D,NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
shiftdone_D <= (shiftcnt(3) AND shiftcnt(2) AND shiftcnt(0) AND
shiftcnt(1));
FDCPE_shifting2: FDCPE port map (shifting2,shifting2_D,NOT $OpTx$INV$24__$INT,'0','0');
shifting2_D <= (NOT shiftdone AND start_shifting);
FTCPE_slaveinten: FTCPE port map (slaveinten,slaveinten_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
slaveinten_T <= ((slaveinten AND cpu_a(1) AND cpu_a(0) AND NOT cpu_d(4).PIN)
OR (NOT slaveinten AND cpu_a(1) AND cpu_a(0) AND cpu_d(4).PIN));
FTCPE_spi_Nsel: FTCPE port map (spi_Nsel,spi_Nsel_T,Ncs2,'0',NOT cpu_Nres,NOT cpu_rnw);
spi_Nsel_T <= ((spi_Nsel AND cpu_a(1) AND cpu_a(0) AND NOT cpu_d(0).PIN)
OR (NOT spi_Nsel AND cpu_a(1) AND cpu_a(0) AND cpu_d(0).PIN));
FDCPE_spidatain0: FDCPE port map (spidatain(0),spidatain_D(0),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(0));
spidatain_D(0) <= (NOT spi_Nsel AND spi_miso);
spidatain_CE(0) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain1: FDCPE port map (spidatain(1),spidatain(0),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(1));
spidatain_CE(1) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain2: FDCPE port map (spidatain(2),spidatain(1),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(2));
spidatain_CE(2) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain3: FDCPE port map (spidatain(3),spidatain(2),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(3));
spidatain_CE(3) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain4: FDCPE port map (spidatain(4),spidatain(3),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(4));
spidatain_CE(4) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain5: FDCPE port map (spidatain(5),spidatain(4),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(5));
spidatain_CE(5) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain6: FDCPE port map (spidatain(6),spidatain(5),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(6));
spidatain_CE(6) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain7: FDCPE port map (spidatain(7),spidatain(6),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(7));
spidatain_CE(7) <= (shiftcnt(0) AND shifting2);
FTCPE_spidataout0: FTCPE port map (spidataout(0),spidataout_T(0),Ncs2,'0','0',spidataout_CE(0));
spidataout_T(0) <= ((NOT cpu_a(1) AND spidataout(0) AND NOT cpu_a(0) AND
NOT cpu_d(0).PIN)
OR (NOT cpu_a(1) AND NOT spidataout(0) AND NOT cpu_a(0) AND
cpu_d(0).PIN));
spidataout_CE(0) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout1: FTCPE port map (spidataout(1),spidataout_T(1),Ncs2,'0','0',spidataout_CE(1));
spidataout_T(1) <= ((NOT cpu_a(1) AND spidataout(1) AND NOT cpu_a(0) AND
NOT cpu_d(1).PIN)
OR (NOT cpu_a(1) AND NOT spidataout(1) AND NOT cpu_a(0) AND
cpu_d(1).PIN));
spidataout_CE(1) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout2: FTCPE port map (spidataout(2),spidataout_T(2),Ncs2,'0','0',spidataout_CE(2));
spidataout_T(2) <= ((NOT cpu_a(1) AND spidataout(2) AND NOT cpu_a(0) AND
NOT cpu_d(2).PIN)
OR (NOT cpu_a(1) AND NOT spidataout(2) AND NOT cpu_a(0) AND
cpu_d(2).PIN));
spidataout_CE(2) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout3: FTCPE port map (spidataout(3),spidataout_T(3),Ncs2,'0','0',spidataout_CE(3));
spidataout_T(3) <= ((NOT cpu_a(1) AND spidataout(3) AND NOT cpu_a(0) AND
NOT cpu_d(3).PIN)
OR (NOT cpu_a(1) AND NOT spidataout(3) AND NOT cpu_a(0) AND
cpu_d(3).PIN));
spidataout_CE(3) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout4: FTCPE port map (spidataout(4),spidataout_T(4),Ncs2,'0','0',spidataout_CE(4));
spidataout_T(4) <= ((NOT cpu_a(1) AND spidataout(4) AND NOT cpu_a(0) AND
NOT cpu_d(4).PIN)
OR (NOT cpu_a(1) AND NOT spidataout(4) AND NOT cpu_a(0) AND
cpu_d(4).PIN));
spidataout_CE(4) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout5: FTCPE port map (spidataout(5),spidataout_T(5),Ncs2,'0','0',spidataout_CE(5));
spidataout_T(5) <= ((NOT cpu_a(1) AND spidataout(5) AND NOT cpu_a(0) AND
NOT cpu_d(5).PIN)
OR (NOT cpu_a(1) AND NOT spidataout(5) AND NOT cpu_a(0) AND
cpu_d(5).PIN));
spidataout_CE(5) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout6: FTCPE port map (spidataout(6),spidataout_T(6),Ncs2,'0','0',spidataout_CE(6));
spidataout_T(6) <= ((NOT cpu_a(1) AND spidataout(6) AND NOT cpu_a(0) AND
NOT cpu_d(6).PIN)
OR (NOT cpu_a(1) AND NOT spidataout(6) AND NOT cpu_a(0) AND
cpu_d(6).PIN));
spidataout_CE(6) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout7: FTCPE port map (spidataout(7),spidataout_T(7),Ncs2,'0','0',spidataout_CE(7));
spidataout_T(7) <= ((NOT cpu_a(1) AND spidataout(7) AND NOT cpu_a(0) AND
NOT cpu_d(7).PIN)
OR (NOT cpu_a(1) AND NOT spidataout(7) AND NOT cpu_a(0) AND
cpu_d(7).PIN));
spidataout_CE(7) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_start_shifting: FTCPE port map (start_shifting,start_shifting_T,Ncs2,NOT start_shifting/start_shifting_RSTF__$INT,'0');
start_shifting_T <= ((NOT cpu_rnw AND NOT cpu_a(1) AND NOT start_shifting AND NOT cpu_a(0))
OR (frx AND NOT cpu_a(1) AND NOT start_shifting AND NOT cpu_a(0)));
start_shifting/start_shifting_RSTF__$INT <= (cpu_Nres AND NOT shiftdone);
FDCPE_tc: FDCPE port map (tc,'0',Ncs2,'0',shiftdone,tc_CE);
tc_CE <= (NOT cpu_a(1) AND NOT cpu_a(0));
FTCPE_tmo: FTCPE port map (tmo,tmo_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
tmo_T <= ((tmo AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(3).PIN)
OR (NOT tmo AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(3).PIN));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
**************************** Device Pin Out ****************************
Device : XC9572XL-10-PC44
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
| 7 39 |
| 8 38 |
| 9 37 |
| 10 36 |
| 11 XC9572XL-10-PC44 35 |
| 12 34 |
| 13 33 |
| 14 32 |
| 15 31 |
| 16 30 |
| 17 29 |
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 TIE 23 GND
2 cpu_d<0> 24 cpu_a<1>
3 cpu_d<1> 25 b8
4 cpu_d<2> 26 b9
5 cpu_Nphi2 27 b10
6 extclk 28 spi_Nsel
7 cpu_rnw 29 led
8 cpu_d<3> 30 TDO
9 cpu_d<4> 31 GND
10 GND 32 VCC
11 cpu_d<5> 33 TIE
12 cpu_d<6> 34 spi_sclk
13 cpu_d<7> 35 spi_mosi
14 noe 36 a8
15 TDI 37 a9
16 TMS 38 a10
17 TCK 39 cpu_Nirq
18 Ncs2 40 nio_sel
19 cpu_Nres 41 VCC
20 ng 42 spi_int
21 VCC 43 nio_stb
22 cpu_a<0> 44 spi_miso
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572xl-10-PC44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Set Unused I/O Pin Termination : FLOAT
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25

3543
VHDL/spi6502b.vm6
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3
VHDL/spi6502b.xml
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205
VHDL/spi6502b_build.xml
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<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE document SYSTEM 'file:///C:/Xilinx/chipviewer/data/xsl/buildXML.dtd'>
<document>
<design name='spi6502b'/>
<xilinx path='C:/Xilinx;'/>
<projDir path='C:\sources\AppleIISd'/>
<xslDir path='C:/Xilinx/chipviewer/data/xsl'/>
<fileDir path='/chipviewer/data/html'/>
<dataFile file='index.htm'/>
<dataFile file='report.htm'/>
<dataFile file='eqns.js'/>
<dataFile file='fbs.js'/>
<dataFile file='maplogic.js'/>
<dataFile file='pins.js'/>
<dataFile file='tooltips.js'/>
<dataFile file='errors.js'/>
<dataFile file='leftnav.js'/>
<dataFile file='paths.js'/>
<dataFile file='summary.js'/>
<dataFile file='topnav.js'/>
<dataFile file='applet.js'/>
<dataFile file='plugin.js'/>
<dataFile file='ns4plugin.js'/>
<dataFile file='equations.htm'/>
<dataFile file='result.htm'/>
<dataFile file='style.css'/>
<dataFile file='blank.gif'/>
<dataFile file='fbview.jpg'/>
<dataFile file='pinview.jpg'/>
<dataFile file='xc9500xl_logo.jpg'/>
<dataFile file='asciidoc.htm'/>
<dataFile file='equationsdoc.htm'/>
<dataFile file='errorsdoc.htm'/>
<dataFile file='fbs_FBdoc.htm'/>
<dataFile file='fbsdoc.htm'/>
<dataFile file='mapinputdoc.htm'/>
<dataFile file='maplogicdoc.htm'/>
<dataFile file='optionsdoc.htm'/>
<dataFile file='pinsdoc.htm'/>
<dataFile file='summarydoc.htm'/>
<dataFile file='check.htm'/>
<dataFile file='checkNS4.htm'/>
<dataFile file='appletref.htm'/>
<dataFile file='newappletref.htm'/>
<dataFile file='errors1.gif'/>
<dataFile file='errors2.gif'/>
<dataFile file='equations.gif'/>
<dataFile file='functionblock.gif'/>
<dataFile file='fb1.gif'/>
<dataFile file='legend.gif'/>
<dataFile file='macrocell.gif'/>
<dataFile file='fb.gif'/>
<dataFile file='pin.gif'/>
<dataFile file='pindiagram.gif'/>
<dataFile file='view.gif'/>
<dataFile file='xml8.jpg'/>
<dataFile file='xml7.jpg'/>
<dataFile file='xml6.jpg'/>
<dataFile file='xml5.jpg'/>
<xmlFileGroup id='1'>
<xmlFile file='spi6502b.xml'>
<xslFile file='topnav.xsl'>
<output file='topnav.htm'/>
</xslFile>
<xslFile file='leftnav.xsl'>
<param name='result' value='1'/>
<output file='leftnav.htm'/>
</xslFile>
<xslFile file='print.xsl'>
<output file='ascii.tmp'/>
</xslFile>
<xslFile file='eqns.xsl'>
<output file='eqns.htm'/>
</xslFile>
<xslFile file='summary.xsl'>
<param name='sumOn' value='1'/>
<param name='optOn' value='0'/>
<param name='legendOn' value='0'/>
<output file='summary.htm'/>
</xslFile>
</xmlFile>
</xmlFileGroup>
<xmlFileGroup id='2'>
<xmlFile file='spi6502b.xml'>
<xslFile file='summary.xsl'>
<param name='sumOn' value='0'/>
<param name='optOn' value='1'/>
<param name='legendOn' value='0'/>
<output file='options.htm'/>
</xslFile>
<xslFile file='printErrors.xsl'>
<output file='errs.htm'/>
</xslFile>
<xslFile file='printPins.xsl'>
<output file='pins.htm'/>
</xslFile>
<xslFile file='wait.xsl'>
<output file='wait.htm'/>
</xslFile>
<xslDebug file='printErrors.xsl'>
<output file='errors.htm'/>
</xslDebug>
<xslDebug file='printPins.xsl'>
<output file='pinout.htm'/>
</xslDebug>
<xslDebug file='printEqns.xsl'>
<output file='eqnout.htm'/>
</xslDebug>
<xslFile file='maplogic.xsl'>
<param name='sortType' value='0'/>
<param name='mapLog' value='1'/>
<param name='mapIn' value='0'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<output file='maplogic_00.htm'/>
<param name='sortType' value='1'/>
<param name='mapLog' value='1'/>
<param name='mapIn' value='0'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<output file='maplogic_01.htm'/>
<param name='sortType' value='2'/>
<param name='mapLog' value='1'/>
<param name='mapIn' value='0'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<output file='maplogic_02.htm'/>
<param name='sortType' value='0'/>
<param name='mapLog' value='0'/>
<param name='mapIn' value='1'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<output file='mapinput_00.htm'/>
<param name='sortType' value='1'/>
<param name='mapLog' value='0'/>
<param name='mapIn' value='1'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<output file='mapinput_01.htm'/>
<param name='sortType' value='2'/>
<param name='mapLog' value='0'/>
<param name='mapIn' value='1'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<output file='mapinput_02.htm'/>
</xslFile>
<xslFile file='fbsum.xsl'>
<param name='legendOn' value='0'/>
<output file='fbs.htm'/>
</xslFile>
<xslFile file='fbs.xsl'>
<param name='fb' value='FB1'/>
<param name='type' value='1'/>
<param name='legendOn' value='1'/>
<output file='fbs_FB1.htm'/>
<param name='fb' value='FB2'/>
<param name='type' value='3'/>
<param name='legendOn' value='1'/>
<output file='fbs_FB2.htm'/>
<param name='fb' value='FB3'/>
<param name='type' value='3'/>
<param name='legendOn' value='1'/>
<output file='fbs_FB3.htm'/>
<param name='fb' value='FB4'/>
<param name='type' value='2'/>
<param name='legendOn' value='1'/>
<output file='fbs_FB4.htm'/>
</xslFile>
</xmlFile>
<xmlFile file='C:/Xilinx/chipviewer/data/xsl/pinlegend.xml'>
<xslFile file='legend.xsl'>
<param name='device' value='XC9572XL-10-PC44'/>
<param name='verOn' value='0'/>
<param name='linkName' value='pinlegendV.htm'/>
<output file='pinlegend.htm'/>
<param name='device' value='XC9572XL-10-PC44'/>
<param name='verOn' value='1'/>
<param name='linkName' value='pinlegend.htm'/>
<output file='pinlegendV.htm'/>
</xslFile>
</xmlFile>
<xmlFile file='C:/Xilinx/chipviewer/data/xsl/logiclegend.xml'>
<xslFile file='legend.xsl'>
<param name='device' value='XC9572XL-10-PC44'/>
<param name='verOn' value='0'/>
<param name='linkName' value='logiclegendV.htm'/>
<output file='logiclegend.htm'/>
<param name='device' value='XC9572XL-10-PC44'/>
<param name='verOn' value='1'/>
<param name='linkName' value='logiclegend.htm'/>
<output file='logiclegendV.htm'/>
</xslFile>
</xmlFile>
</xmlFileGroup>
<rptFile file='spi6502b.rpt'/>
<timFile file='spi6502b.tim'/>
<appFile/>
</document>

0
VHDL/tmperr.err
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VHDL/userlang.tpl
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[Verilog.User Templates]
type=folder
[VHDL.User Templates]
type=folder
[ABEL.User Templates]
type=folder

2
_ngo/netlist.lst
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C:\sources\AppleIISd\spi6502b.ngc 1494461294
OK

0
address_decoder._u_
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address_decoder.lfp
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# begin LFP file C:\sources\AppleIISd\address_decoder.lfp
designfile address_decoder.ngd
INST "address_decoder" COLOR=15 ;
NET "OE" COLOR=6 ;
NET "IO_STB" COLOR=6 ;
NET "IO_SEL" COLOR=6 ;
NET "extclk" COLOR=6 ;
NET "A10_B" COLOR=6 ;
NET "A10" COLOR=6 ;
NET "A9_B" COLOR=6 ;
NET "A9" COLOR=6 ;
NET "A8_B" COLOR=6 ;
NET "A8" COLOR=6 ;
INST "XLXI_16" COLOR=7 ;
INST "XLXI_16/U0" COLOR=7 ;

19
address_decoder.ucf
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#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "A10" LOC = "P37" ;
NET "A10_B" LOC = "P38" ;
NET "A8" LOC = "P27" ;
NET "A8_B" LOC = "P29" ;
NET "A9" LOC = "P33" ;
NET "A9_B" LOC = "P36" ;
NET "extclk" LOC = "p6" ;
NET "IO_SEL" LOC = "P39" ;
NET "IO_STB" LOC = "P40" ;
NET "OE" LOC = "P1" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

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address_decoder.vhf
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 6.3.03i
-- \ \ Application :
-- / / Filename : address_decoder.vhf
-- /___/ /\ Timestamp : 05/11/2017 02:05:37
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name: FD_MXILINX_address_decoder
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FD_MXILINX_address_decoder is
port ( C : in std_logic;
D : in std_logic;
Q : out std_logic);
end FD_MXILINX_address_decoder;
architecture BEHAVIORAL of FD_MXILINX_address_decoder is
attribute BOX_TYPE : string ;
signal XLXN_4 : std_logic;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component FDCP
port ( C : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCP : component is "BLACK_BOX";
begin
I_36_43 : GND
port map (G=>XLXN_4);
U0 : FDCP
port map (C=>C,
CLR=>XLXN_4,
D=>D,
PRE=>XLXN_4,
Q=>Q);
end BEHAVIORAL;
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 6.3.03i
-- \ \ Application :
-- / / Filename : address_decoder.vhf
-- /___/ /\ Timestamp : 05/11/2017 02:05:37
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name: FDRS_MXILINX_address_decoder
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FDRS_MXILINX_address_decoder is
port ( C : in std_logic;
D : in std_logic;
R : in std_logic;
S : in std_logic;
Q : out std_logic);
end FDRS_MXILINX_address_decoder;
architecture BEHAVIORAL of FDRS_MXILINX_address_decoder is
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
signal XLXN_6 : std_logic;
signal XLXN_7 : std_logic;
signal XLXN_8 : std_logic;
component AND2B1
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
component OR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
component FD_MXILINX_address_decoder
port ( C : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute HU_SET of U0 : label is "U0_0";
begin
I_36_112 : AND2B1
port map (I0=>R,
I1=>S,
O=>XLXN_6);
I_36_113 : AND2B1
port map (I0=>R,
I1=>D,
O=>XLXN_8);
I_36_120 : OR2
port map (I0=>XLXN_6,
I1=>XLXN_8,
O=>XLXN_7);
U0 : FD_MXILINX_address_decoder
port map (C=>C,
D=>XLXN_7,
Q=>Q);
end BEHAVIORAL;
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 6.3.03i
-- \ \ Application :
-- / / Filename : address_decoder.vhf
-- /___/ /\ Timestamp : 05/11/2017 02:05:37
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name: address_decoder
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity address_decoder is
port ( A8 : in std_logic;
A9 : in std_logic;
A10 : in std_logic;
CLK : in std_logic;
NIO_SEL : in std_logic;
NIO_STB : in std_logic;
A8_B : out std_logic;
A9_B : out std_logic;
A10_B : out std_logic;
NOE : out std_logic);
end address_decoder;
architecture BEHAVIORAL of address_decoder is
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
signal XLXN_4 : std_logic;
signal XLXN_10 : std_logic;
signal XLXN_11 : std_logic;
signal XLXN_14 : std_logic;
signal XLXN_19 : std_logic;
component NAND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of NAND2 : component is "BLACK_BOX";
component FDRS_MXILINX_address_decoder
port ( C : in std_logic;
D : in std_logic;
R : in std_logic;
S : in std_logic;
Q : out std_logic);
end component;
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component INV
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of INV : component is "BLACK_BOX";
component AND4B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX";
attribute HU_SET of XLXI_16 : label is "XLXI_16_1";
begin
XLXI_13 : NAND2
port map (I0=>NIO_SEL,
I1=>NIO_STB,
O=>XLXN_4);
XLXI_14 : NAND2
port map (I0=>XLXN_11,
I1=>XLXN_4,
O=>NOE);
XLXI_16 : FDRS_MXILINX_address_decoder
port map (C=>CLK,
D=>XLXN_14,
R=>XLXN_10,
S=>XLXN_19,
Q=>XLXN_11);
XLXI_17 : VCC
port map (P=>XLXN_14);
XLXI_18 : AND2
port map (I0=>A10,
I1=>NIO_SEL,
O=>A10_B);
XLXI_19 : AND2
port map (I0=>A9,
I1=>NIO_SEL,
O=>A9_B);
XLXI_20 : AND2
port map (I0=>A8,
I1=>NIO_SEL,
O=>A8_B);
XLXI_22 : INV
port map (I=>NIO_SEL,
O=>XLXN_19);
XLXI_23 : AND4B1
port map (I0=>NIO_STB,
I1=>A10,
I2=>A9,
I3=>A8,
O=>XLXN_10);
end BEHAVIORAL;

128
address_decoder_html/fit/applet.js
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@ -1,128 +0,0 @@
var tmpStr = "";
var waitWin;
function openWait() {
waitWin = window.open("wait.htm", "wait",
"toolbar=no,location=no,"+
"directories=no,status=no,menubar=no,scrollbars=no,"+
"resizable=no,width=300,height=50" );
}
function closeWait() { if (waitWin) waitWin.close(); }
function setMsg(msg){
parent.leftnav.setAppletMsg( msg );
// now send it reload forces
// call to applet paint
location.reload();
}
function getMsg(){
return( parent.leftnav.getAppletMsg() );
}
function resetMsg(){ parent.leftnav.setAppletMsg(""); }
function printAppletPkg() {
if( isNS() ){
setMsg("cmd printPkg ");
}
else{
document.ChipViewerApplet.PrintPkg();
}
}
function showAppletGraphicMC(mc) {
if( isNS() ){
setMsg("cmd showMac " + mc);
}
else{
document.ChipViewerApplet.ShowMac(mc);
}
}
function ShowMC() { showAppletGraphicMC(tmpStr); }
function showAppletGraphicFB(fb) {
if( isNS() ){
setMsg("cmd showFB " + fb);
}
else{
document.ChipViewerApplet.ShowFB(fb);
}
}
function showAppletGraphicPin(pin) {
if( isNS() ){
setMsg("cmd showPin " + pin);
}
else{
document.ChipViewerApplet.ShowPin(pin);
}
}
function ShowFB() { showAppletGraphicFB(tmpStr); }
function isNS() {
return ((navigator.appName.indexOf("Netscape") >= 0) && (parseFloat(navigator.appVersion) < 5) ) ? true : false;
}
function isIE(){
var agt=navigator.userAgent.toLowerCase();
return( ( (agt.indexOf("msie") != -1) && (agt.indexOf("opera") == -1) ) ? true: false );
}
function waitUntilOK() {
if (!waitWin) openWait();
if (isNS()) {
if (document.ChipViewerApplet.isActive()) closeWait();
else settimeout("waitUntilOK()",100);
}
else {
if (document.ChipViewerApplet.readyState == 4) closeWait();
else settimeout("waitUntilOK()",100);
}
}
// check that the applet if file has been generated
// this can only be done if the applets been loaded.
function fileExists(fileName){
if( document.ChipViewerApplet.readyState != 4 ) {
window.alert("Navigation disabled until the applet is loaded." );
}
if( isIE() ){
if( parent.leftnav.getAppletPermission() == 1 ){
if( document.ChipViewerApplet.TestFileExists(fileName) == 1 ){
window.alert("file exist tests true" );
return( true );
}
}
else{
window.alert("file exist returns true no permission" );
return( true );
}
}
else{
return( true );
}
window.alert("file exist returns false" );
return( false );
}
function setPermission(){
if( isIE() ){
if( document.ChipViewerApplet.granted() ){
parent.leftnav.setAppletPermission();
}
}
else{
return( true );
}
}

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<html>
<head>
<title></title>
</head>
<frameset frameborder="NO" framespacing="0" border="0" rows="94,*,0,0" col="*">
<frame name="topnav" src="../tim/topnav.htm" scrolling="no" noresize marginwidth="0" marginheight="0">
<frameset frameborder="NO" framespacing="0" border="0" cols="125,*">
<frame name="leftnav" src="leftnav.htm" noresize marginwidth="0" marginheight="0">
<frame name="content" src="summary.htm">
</frameset>
<frame name="applets" src="applet.htm" scrolling="no">
<frame name="eqns" src="eqns.htm" scrolling="no">
</frameset>
</html>

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<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
<html>
<!--(==============================================================)-->
<!--(Document created with RoboEditor. )============================-->
<!--(==============================================================)-->
<head>
<title>Text Report</title>
<!--(Meta)==========================================================-->
<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
<meta name=generator-major-version content=0.1>
<meta name=generator-minor-version content=1>
<meta name=filetype content=kadov>
<meta name=filetype-version content=1>
<meta name=page-count content=1>
<meta name=layout-height content=375>
<meta name=layout-width content=798>
<meta name=date content="05 1, 2002 4:24:59 PM">
<style>
<!--
p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
--></style><script language="javascript" title="WebHelpInlineScript">
<!--
function reDo() {
if (innerWidth != origWidth || innerHeight != origHeight)
location.reload();
}
if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
origWidth = innerWidth;
origHeight = innerHeight;
onresize = reDo;
}
//-->
</script><style>
<!--
div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
p.WebHelpNavBar {text-align:right;}
-->
</style>
</head>
<!--(Body)==========================================================-->
<body>
<h1>Text Report</h1>
<p class="whs1">Selecting Text
Report from the left-hand frame will give you a printable text version
of the fitter report. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->It
contains sections similar to those of the XML report (a summary section,
errors and warnings, mapped logic, function blocks, function block details,
a text-graphical display of the pinout, and a summary of compiler options),
but it is not easily navigable. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->It
is best to use the text report only when you need to print out a hard
copy of the fitter results.</p>
</body>
</html>

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<html></html>

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<html>
<head>
<script src="XilinxD.js"> </script>
<script src="applet.js"> </script>
<script src="plugin.js"> </script>
</head>
<body onload="javascript:checkJre()" bgcolor="#ffffff" topmargin="0" leftmargin="0" marginheight="0" marginwidth="0" >
</body>
</html>

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<html>
<head>
<script src="xilinxD.js"> </script>
<script src="applet.js"> </script>
<script src="ns4plugin.js"> </script>
</head>
<body onload="javascript:checkJre()" bgcolor="#ffffff" topmargin="0" leftmargin="0" marginheight="0" marginwidth="0" >
</body>
</html>

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address_decoder_html/fit/eqns.js
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var eqnType = 0;
var spcStr = "&nbsp;";
var nlStr = "<br>";
var tabStr = spcStr + spcStr + spcStr + spcStr + spcStr;
var nlTabStr = nlStr + tabStr;
var rClrS = "<font color='blue'>";
var rClrE = "</font>";
var cClrS = "<font color='green'>";
var cClrE = "</font>";
var abelOper = new Array();
abelOper["GND"] = new Array("Gnd");
abelOper["VCC"] = new Array("Vcc");
abelOper["NOT"] = new Array(rClrS + "!" + rClrE);
abelOper["AND"] = new Array(rClrS + "*" + rClrE);
abelOper["OR"] = new Array(rClrS + "#" + rClrE);
abelOper["XOR"] = new Array(rClrS + "$" + rClrE);
abelOper["EQUAL_COLON"] = new Array(":= ");
abelOper["EQUAL"] = new Array("= ");
abelOper["ASSIGN"] = new Array("");
abelOper["OPEN_NEGATE"] = new Array("(");
abelOper["CLOSE_NEGATE"] = new Array(")");
abelOper["OPEN_PTERM"] = new Array("");
abelOper["CLOSE_PTERM"] = new Array("");
abelOper["OPEN_BRACE"] = new Array("<");
abelOper["CLOSE_BRACE"] = new Array(">");
abelOper["INVALID_OPEN_BRACE"] = new Array("<");
abelOper["INVALID_CLOSE_BRACE"] = new Array(">");
abelOper["ENDLN"] = new Array(";");
abelOper["COMMENT"] = new Array("//");
abelOper["IMPORT"] = new Array(";Imported pterms ");
abelOper["GCK_COM"] = new Array("GCK");
abelOper["GTS_COM"] = new Array("GTS");
abelOper["GSR_COM"] = new Array("GSR");
abelOper["START_EQN"] = new Array("");
abelOper["END_EQN"] = new Array("");
abelOper["_I"] = new Array(".I");
abelOper["_T"] = new Array(".T");
abelOper["_D"] = new Array(".D");
abelOper["_C"] = new Array(".CLK");
abelOper["_LH"] = new Array(".LH");
abelOper["_CLR"] = new Array(".AR");
abelOper["_PRE"] = new Array(".AP");
abelOper["_CE"] = new Array(".CE");
abelOper["_OE"] = new Array(".OE");
abelOper["OE_START"] = new Array(" <= ");
abelOper["OE_WHEN"] = new Array(" when ");
abelOper["OE_EQUAL"] = new Array(" = ");
abelOper["OE_ELSE"] = new Array(" else ");
abelOper["B0"] = new Array("'0'");
abelOper["B1"] = new Array("'1'");
abelOper["BZ"] = new Array("'Z'");
abelOper["FD"] = new Array(".D");
abelOper["FT"] = new Array(".T");
abelOper["FDD"] = new Array(".D");
abelOper["FTD"] = new Array(".T");
abelOper["LD"] = new Array(".LH");
abelOper["Q"] = new Array(".Q");
var vhdlOper = new Array();
vhdlOper["GND"] = new Array("'0'");
vhdlOper["VCC"] = new Array("'1'");
vhdlOper["NOT"] = new Array(rClrS + "NOT " + rClrE);
vhdlOper["AND"] = new Array(rClrS + "AND" + rClrE);
vhdlOper["OR"] = new Array(rClrS + "OR" + rClrE);
vhdlOper["XOR"] = new Array(rClrS + "XOR" + rClrE);
vhdlOper["EQUAL_COLON"] = new Array("<= ");
vhdlOper["EQUAL"] = new Array("<= ");
vhdlOper["ASSIGN"] = new Array("");
vhdlOper["OPEN_NEGATE"] = new Array("(");
vhdlOper["CLOSE_NEGATE"] = new Array(")");
vhdlOper["OPEN_PTERM"] = new Array("(");
vhdlOper["CLOSE_PTERM"] = new Array(")");
vhdlOper["OPEN_BRACE"] = new Array("(");
vhdlOper["CLOSE_BRACE"] = new Array(")");
vhdlOper["INVALID_OPEN_BRACE"] = new Array("<");
vhdlOper["INVALID_CLOSE_BRACE"] = new Array(">");
vhdlOper["ENDLN"] = new Array(";");
vhdlOper["COMMENT"] = new Array("--");
vhdlOper["IMPORT"] = new Array("");
vhdlOper["GCK_COM"] = new Array("GCK");
vhdlOper["GTS_COM"] = new Array("GTS");
vhdlOper["GSR_COM"] = new Array("GSR");
vhdlOper["START_EQN"] = new Array(rClrS + "port map" + rClrE + " (");
vhdlOper["END_EQN"] = new Array(")");
vhdlOper["_I"] = new Array("_I");
vhdlOper["_T"] = new Array("_T");
vhdlOper["_D"] = new Array("_D");
vhdlOper["_C"] = new Array("_C");
vhdlOper["_LH"] = new Array("_C");
vhdlOper["_CLR"] = new Array("_CLR");
vhdlOper["_PRE"] = new Array("_PRE");
vhdlOper["_CE"] = new Array("_CE");
vhdlOper["_OE"] = new Array("_OE");
vhdlOper["OE_START"] = new Array(" <= ");
vhdlOper["OE_WHEN"] = new Array(" when ");
vhdlOper["OE_EQUAL"] = new Array(" = ");
vhdlOper["OE_ELSE"] = new Array(" else ");
vhdlOper["B0"] = new Array("'0'");
vhdlOper["B1"] = new Array("'1'");
vhdlOper["BZ"] = new Array("'Z'");
vhdlOper["FD"] = new Array("FDCPE");
vhdlOper["FT"] = new Array("FTCPE");
vhdlOper["FDD"] = new Array("FDDCPE");
vhdlOper["FTD"] = new Array("FTDCPE");
vhdlOper["LD"] = new Array("LDCP");
vhdlOper["Q"] = new Array("");
var verOper = new Array();
verOper["GND"] = new Array("1'b0");
verOper["VCC"] = new Array("1'b1");
verOper["NOT"] = new Array(rClrS + "!" + rClrE);
verOper["AND"] = new Array(rClrS + "&&" + rClrE);
verOper["OR"] = new Array(rClrS + "||" + rClrE);
verOper["XOR"] = new Array(rClrS + "XOR" + rClrE);
verOper["EQUAL_COLON"] = new Array("= ");
verOper["EQUAL"] = new Array("= ");
verOper["ASSIGN"] = new Array("assign ");
verOper["OPEN_NEGATE"] = new Array("(");
verOper["CLOSE_NEGATE"] = new Array(")");
verOper["OPEN_PTERM"] = new Array("(");
verOper["CLOSE_PTERM"] = new Array(")");
verOper["OPEN_BRACE"] = new Array("[");
verOper["CLOSE_BRACE"] = new Array("]");
verOper["INVALID_OPEN_BRACE"] = new Array("<");
verOper["INVALID_CLOSE_BRACE"] = new Array(">");
verOper["ENDLN"] = new Array(";");
verOper["COMMENT"] = new Array("//");
verOper["IMPORT"] = new Array("");
verOper["GCK_COM"] = new Array("GCK");
verOper["GTS_COM"] = new Array("GTS");
verOper["GSR_COM"] = new Array("GSR");
verOper["START_EQN"] = new Array(" (");
verOper["END_EQN"] = new Array(")");
verOper["_I"] = new Array("_I");
verOper["_T"] = new Array("_T");
verOper["_D"] = new Array("_D");
verOper["_C"] = new Array("_C");
verOper["_LH"] = new Array("_C");
verOper["_CLR"] = new Array("_CLR");
verOper["_PRE"] = new Array("_PRE");
verOper["_CE"] = new Array("_CE");
verOper["_OE"] = new Array("_OE");
verOper["OE_START"] = new Array(" = ");
verOper["OE_WHEN"] = new Array(" ? ");
verOper["OE_EQUAL"] = new Array("");
verOper["OE_ELSE"] = new Array(" : ");
verOper["B0"] = new Array("1'b0");
verOper["B1"] = new Array("1'b1");
verOper["BZ"] = new Array("1'bz");
verOper["FD"] = new Array("FDCPE");
verOper["FT"] = new Array("FTCPE");
verOper["FDD"] = new Array("FDDCPE");
verOper["FTD"] = new Array("FTDCPE");
verOper["LD"] = new Array("LDCP");
verOper["Q"] = new Array("");
var operator = abelOper;
var pterms = new Array();
var d1 = new Array();
var d2 = new Array();
var clk = new Array();
var set = new Array();
var rst = new Array();
var trst = new Array();
var d1imp = new Array();
var d2imp = new Array();
var clkimp = new Array();
var setimp = new Array();
var rstimp = new Array();
var trstimp = new Array();
var gblclk = new Array();
var gblset = new Array();
var gblrst = new Array();
var gbltrst = new Array();
var ce = new Array();
var ceimp = new Array();
var prld = new Array();
var specSig = new Array();
var clkNegs = new Array();
var setNegs = new Array();
var rstNegs = new Array();
var trstNegs = new Array();
var ceNegs = new Array();
var fbnand = new Array();
var inreg = new Array();
var dOneLit = true;
function setOper(type) {
if (type == "1") { operator = vhdlOper; eqnType = 1; }
else if (type == "2") { operator = verOper; eqnType = 2; }
else { operator = abelOper; eqnType = 0; }
}
function isXC95() {
if (device.indexOf("95") != -1) return true;
return false;
}
function is9500() {
if ((device.indexOf("95") != -1) &&
(device.indexOf("XL") == -1) &&
(device.indexOf("XV") == -1)) return true;
return false;
}
function retSigType(s) {
var sigType = sigTypes[s];
var str = operator["Q"];
if (sigType == "D") str = operator["FD"];
else if (sigType == "T") str = operator["FT"];
else if (sigType.indexOf("LATCH") != -1) str = operator["LD"];
else if (sigType.indexOf("DDEFF") != -1) str = operator["FDD"];
else if (sigType.indexOf("DEFF") != -1) str = operator["FD"];
else if (sigType.indexOf("DDFF") != -1) str = operator["FDD"];
else if (sigType.indexOf("TDFF") != -1) str = operator["FTD"];
else if (sigType.indexOf("DFF") != -1) str = operator["FD"];
else if (sigType.indexOf("TFF") != -1) str = operator["FT"];
return str;
}
function retSigIndex(signal) {
for (s=0; s<signals.length; s++) { if (signals[s] == signal) return s; }
return -1;
}
function retSigName(signal) {
var str = "";
if (specSig[signal]) str += specSig[signal];
else str += signal;
var idx1 = str.indexOf(operator["INVALID_OPEN_BRACE"]);
var idx2 = str.indexOf(operator["INVALID_CLOSE_BRACE"]);
if ((idx1 != -1) && (idx2 != -1))
str = str.substring(0,idx1) + operator["OPEN_BRACE"] +
str.substring(idx1+1,idx2) + operator["CLOSE_BRACE"] +
str.substring(idx2+1,str.length);
return str;
}
function removePar(signal) {
var str = signal;
var idx = str.indexOf(operator["OPEN_BRACE"]);
if (idx != -1)
str = str.substring(0,idx) +
str.substring(idx+1,str.indexOf(operator["CLOSE_BRACE"]));
return str;
}
function isOneLiteral(str) {
if ((str.indexOf(operator["AND"]) != -1) ||
(str.indexOf(operator["OR"]) != -1) ||
(str.indexOf(operator["XOR"]) != -1)) return false;
return true;
}
function updateName(signal, index) {
var str;
var idx = signal.indexOf(operator["OPEN_BRACE"]);
if (idx != -1)
str = signal.substring(0,idx) +
index + signal.substring(idx);
else str = signal + index;
return str;
}
function retPterm(pt) {
var str = "";
if (!pterms[pt]) {
if (specSig[pt]) pt = specSig[pt];
return pt;
}
if (pterms[pt].length > 1) str += operator["OPEN_PTERM"];
for (p=0; p<pterms[pt].length; p++) {
var sig = pterms[pt][p];
if (sig.indexOf("xPUP_0") != -1) continue;
if (p>0) str += " " + operator["AND"] + " ";
var neg = 0;
if (sig.indexOf("/") != -1) {
sig = sig.substring(1, sig.length);
str += operator["NOT"];
neg = 1;
}
str += retSigName(sig);
}
if (pterms[pt].length > 1) str += operator["CLOSE_PTERM"];
return str;
}
function retFBMC(str) {
return str.substring(0,str.length-2);
}
function retD1D2(signal) {
var str = "";
dOneLit = true;
if (d1[signal]) {
var currImp = "";
for (i=0; i<d1[signal].length; i++) {
if (!eqnType && d1imp[signal] && (d1imp[signal][i] == "1")) {
if (currImp != retFBMC(d1[signal][i])) {
currImp = retFBMC(d1[signal][i]);
str += nlStr + operator["IMPORT"] + currImp;
}
}
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
str += retPterm(d1[signal][i]);
}
if (d2[signal]) str += nlTabStr + operator["XOR"]+ spcStr;
}
if (d2[signal]) {
var currImp = "";
for (i=0; i<d2[signal].length; i++) {
if (!eqnType && d2imp[signal] && (d2imp[signal][i] == "1")) {
if (currImp != retFBMC(d2[signal][i])) {
currImp = retFBMC(d2[signal][i]);
str += nlStr + operator["IMPORT"] + currImp;
}
}
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
str += retPterm(d2[signal][i]);
}
}
if (str == "GND") str = operator["GND"];
else if (str == "VCC") str = operator["VCC"];
else if (!isOneLiteral(str)) {
dOneLit = false;
var type = retSigType(retSigIndex(signal));
if ((type == operator["FD"]) ||
(type == operator["FDD"])) type = operator["_D"];
else if ((type == operator["FT"]) ||
(type == operator["FTD"])) type = operator["_T"];
else if (type == operator["LD"] && eqnType) type = "_D";
var tmpStr = updateName(retSigName(signal), type);
tmpStr += spcStr + operator["EQUAL_COLON"];
var idx = retSigIndex(signal);
if (eqnType && sigNegs[idx] == "ON") tmpStr += operator["NOT"] + operator["OPEN_NEGATE"];
str = tmpStr + str;
if (eqnType && sigNegs[idx] == "ON") str += operator["CLOSE_NEGATE"];
str += operator["ENDLN"];
}
return str;
}
function retClk(signal) {
var str = "";
if (clk[signal]) {
if (clk[signal].length == 1) {
var pterm = retPterm(clk[signal][0]);
if (clkNegs[signal]) {
str += operator["NOT"];
if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"];
}
str += pterm;
if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"];
}
else {
if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
var currImp = "";
for (i=0; i<clk[signal].length; i++) {
if (!eqnType && clkimp[signal] && (clkimp[signal][i] == "1")) {
if (currImp != retFBMC(clk[signal][i])) {
currImp = retFBMC(clk[signal][i]);
str += nlStr + operator["IMPORT"] + currImp;
}
}
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
str += retPterm(clk[signal][i]);
}
if (clkNegs[signal]) str += operator["CLOSE_NEGATE"];
str += operator["ENDLN"];
}
}
else if (gblclk[signal]) {
if (gblclk[signal].length == 1) {
var pterm = retPterm(gblclk[signal][0]);
if (clkNegs[signal]) {
str += operator["NOT"];
if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"];
}
str += pterm;
if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"];
}
else {
if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
for (i=0; i<gblclk[signal].length; i++) {
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
str += retPterm(gblclk[signal][i]);
}
if (clkNegs[signal]) str += operator["CLOSE_NEGATE"];
str += operator["ENDLN"] + tabStr + cClrS +
operator["COMMENT"] + spcStr + operator["GCK_COM"] + cClrE;
}
}
else if (eqnType) str += operator["B0"];
return str;
}
function retRst(signal) {
var str = "";
if (rst[signal]) {
if (rst[signal].length == 1) {
var currImp;
if (!eqnType && rstimp[signal] && (rstimp[signal][0] == "1")) {
if (currImp != retFBMC(rst[signal][0])) {
currImp = retFBMC(rst[signal][0]);
str += nlStr + operator["IMPORT"] + currImp;
}
}
if (rstNegs[signal]) str += operator["NOT"];
str += retPterm(rst[signal][0]);
}
else {
var currImp = "";
if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
for (i=0; i<rst[signal].length; i++) {
if (!eqnType && rstimp[signal] && (rstimp[signal][i] == "1")) {
if (currImp != retFBMC(rst[signal][i])) {
currImp = retFBMC(rst[signal][i]);
str += nlStr + operator["IMPORT"] + currImp;
}
}
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
str += retPterm(rst[signal][i]);
}
if (rstNegs[signal]) str += operator["CLOSE_NEGATE"];
str += operator["ENDLN"];
}
}
else if (gblrst[signal]) {
if (gblrst[signal].length == 1) {
if (rstNegs[signal]) str += operator["NOT"];
str += retPterm(gblrst[signal][0]);
}
else {
if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
for (i=0; i<gblrst[signal].length; i++) {
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
str += retPterm(gblrst[signal][i]);
}
if (rstNegs[signal]) str += operator["CLOSE_NEGATE"];
str += operator["ENDLN"] + tabStr + cClrS +
operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE;
}
}
else if (eqnType) str += operator["B0"];
return str;
}
function retSet(signal) {
var str = "";
if (set[signal]) {
if (set[signal].length == 1) {
var currImp = "";
if (!eqnType && setimp[signal] && (setimp[signal][0] == "1")) {
if (currImp != retFBMC(set[signal][0])) {
currImp = retFBMC(set[signal][0]);
str += nlStr + operator["IMPORT"] + currImp;
}
}
if (setNegs[signal]) str += operator["NOT"];
str += retPterm(set[signal][0]);
}
else {
var currImp = "";
if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
for (i=0; i<set[signal].length; i++) {
if (!eqnType && setimp[signal] && (setimp[signal][i] == "1")) {
if (currImp != retFBMC(set[signal][i])) {
currImp = retFBMC(set[signal][i]);
str += nlStr + operator["IMPORT"] + currImp;
}
}
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
str += retPterm(set[signal][i]);
}
if (setNegs[signal]) str += operator["CLOSE_NEGATE"];
str += operator["ENDLN"];
}
}
else if (gblset[signal]) {
if (gblset[signal].length == 1) {
if (setNegs[signal]) str += operator["NOT"];
str += retPterm(gblset[signal][0]);
}
else {
if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
for (i=0; i<gblset[signal].length; i++) {
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
str += retPterm(gblset[signal][i]);
}
if (setNegs[signal]) str += operator["CLOSE_NEGATE"];
str += operator["ENDLN"] + tabStr + cClrS +
operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE;
}
}
else if (eqnType) str += operator["B0"];
return str;
}
function retCE(signal) {
var str = "";
if (ce[signal]) {
if (ce[signal].length == 1) {
var currImp = "";
if (!eqnType && ceimp[signal] && (ceimp[signal][0] == "1")) {
if (currImp != retFBMC(ce[signal][0])) {
currImp = retFBMC(ce[signal][0]);
str += nlStr + operator["IMPORT"] + currImp;
}
}
if (ceNegs[signal]) str += operator["NOT"];
str += retPterm(ce[signal][0]);
}
else {
var currImp = "";
if (ceNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
for (i=0; i<ce[signal].length; i++) {
if (!eqnType && ceimp[signal] && (ceimp[signal][i] == "1")) {
if (currImp != retFBMC(ce[signal][i])) {
currImp = retFBMC(ce[signal][i]);
str += nlStr + operator["IMPORT"] + currImp;
}
}
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
str += retPterm(ce[signal][i]);
}
if (ceNegs[signal]) str += operator["CLOSE_NEGATE"];
str += operator["ENDLN"];
}
}
else if (eqnType) str += operator["B1"];
return str;
}
function retTrst(signal) {
var str = "";
if (trst[signal]) {
if (trstNegs[signal])
str += operator["NOT"] + operator["OPEN_NEGATE"];
for (i=0; i<trst[signal].length; i++) {
var currImp = "";
if (!eqnType && trstimp[signal] && (trstimp[signal][0] == "1")) {
if (currImp != retFBMC(trst[signal][0])) {
currImp = retFBMC(trst[signal][0]);
str += nlStr + operator["IMPORT"] + currImp;
}
}
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
str += retPterm(trst[signal][i]);
}
if (trstNegs[signal]) str += operator["CLOSE_NEGATE"];
}
else if (gbltrst[signal]) {
if (trstNegs[signal])
str += operator["NOT"] + operator["OPEN_NEGATE"];
for (i=0; i<gbltrst[signal].length; i++) {
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
str += retPterm(gbltrst[signal][i]);
}
if (trstNegs[signal]) str += operator["CLOSE_NEGATE"];
}
str += operator["ENDLN"];
return str;
}
function retEqn(signal) {
var str = inregStr = "";
var iStr = qStr = "";
var dStr = dEqn = "";
var cStr = cEqn = "";
var clrStr = clrEqn = "";
var preStr = preEqn = "";
var ceStr = ceEqn = "";
var oeStr = oeEqn = "";
var sigName = retSigName(signal);
var type = retSigType(retSigIndex(signal));
if (gbltrst[signal] || trst[signal]) iStr = operator["_I"];
if (eqnType) qStr = updateName(sigName, iStr);
if (inreg[signal]) {
if (!eqnType)
inregStr = operator["COMMENT"] + " Direct Input Register" + nlStr;
dStr = retSigName(inreg[signal][0]);
}
else dStr = retD1D2(signal);
if (eqnType && !dOneLit) {
dEqn = dStr;
dStr = dStr.substring(0,dStr.indexOf(operator["EQUAL_COLON"]));
}
else if (!eqnType) {
if (!dOneLit) dStr = dStr.substring(dStr.indexOf(operator["EQUAL_COLON"])+2);
if (sigNegs[retSigIndex(signal)] == "ON") dEqn += operator["NOT"];
dEqn += sigName;
if ((type == operator["FT"]) ||
(type == operator["FTD"])) dEqn += operator["_T"];
else if ((type == operator["FD"]) ||
(type == operator["FTD"])||
(type == operator["LD"])) dEqn += operator["_D"];
dEqn += " ";
if ((type != operator["Q"]) && (type != operator["LD"]))
dEqn += operator["EQUAL_COLON"];
else dEqn += operator["EQUAL"];
dEqn += dStr;
if (dOneLit) dEqn += operator["ENDLN"];
}
cStr = retClk(signal);
if (eqnType && !isOneLiteral(cStr)){
cEqn = cStr;
if (cEqn.indexOf(operator["ENDLN"]) == -1)
cEqn += operator["ENDLN"];
cStr = updateName(sigName, operator["_C"]);
}
else if (!eqnType && cStr) {
cEqn += cStr;
cStr = tabStr + sigName;
if (type == operator["LD"]) cStr += operator["_LH"];
else cStr += operator["_C"];
if (cEqn.indexOf(operator["ENDLN"]) == -1)
cEqn += operator["ENDLN"];
if (gblclk[signal]) cEqn += tabStr + operator["COMMENT"] + " " + operator["GCK_COM"];
}
clrStr = retRst(signal);
if (eqnType && !isOneLiteral(clrStr)){
clrEqn = clrStr;
if (cEqn.indexOf(operator["ENDLN"]) == -1)
clrEqn += operator["ENDLN"];
clrStr = updateName(sigName, operator["_CLR"]);
}
else if (!eqnType && clrStr) {
clrEqn += clrStr;
clrStr = tabStr + sigName + operator["_CLR"];
if (clrEqn.indexOf(operator["ENDLN"]) == -1)
clrEqn += operator["ENDLN"];
if (gblrst[signal]) clrEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"];
}
preStr = retSet(signal);
if (eqnType && !isOneLiteral(preStr)){
preEqn = preStr;
if (cEqn.indexOf(operator["ENDLN"]) == -1)
preEqn += operator["ENDLN"];
preStr = updateName(sigName, operator["_PRE"]);
}
else if (!eqnType && preStr) {
preEqn += preStr;
preStr = tabStr + sigName + operator["_PRE"];
if (preEqn.indexOf(operator["ENDLN"]) == -1)
preEqn += operator["ENDLN"];
if (gblset[signal]) preEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"];
}
if (!is9500()) {
ceStr = retCE(signal);
if (eqnType && !isOneLiteral(ceStr)){
ceEqn = ceStr;
if (cEqn.indexOf(operator["ENDLN"]) == -1)
ceEqn += operator["ENDLN"];
ceStr = updateName(sigName, operator["_CE"]);
}
else if (!eqnType && ceStr) {
ceEqn += ceStr;
ceStr = tabStr + sigName + operator["_CE"];
if (ceEqn.indexOf(operator["ENDLN"]) == -1)
ceEqn += operator["ENDLN"];
}
}
if (eqnType && trst[signal]) oeEqn = retTrst(signal)
else if (!eqnType && (trst[signal] || gbltrst[signal])) oeEqn = retTrst(signal);
var newline = false;
if (type == "") {
str += operator["ASSIGN"] + qStr + " " + operator["EQUAL"];
if (dOneLit) str += dStr;
else str += dEqn.substring(dEqn.indexOf(operator["EQUAL"])+2);
if (oeEqn != "") {
var oeStr = updateName(sigName, operator["_OE"]);
if (eqnType == 1) {
str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr +
operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] +
operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"];
}
else if (eqnType == 2) {
str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] +
oeStr + operator["OE_WHEN"] + qStr +
operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"];
}
str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
}
}
else {
if (eqnType == 1) {
str += type + "_" + removePar(retSigName(signal)) +
": " + type + " " + operator["START_EQN"] +
qStr + ", " + dStr + ", " + cStr + ", " +
clrStr + ", " + preStr;
if (!is9500() && (type != operator["LD"])) str += ", " + ceStr;
str += operator["END_EQN"] + operator["ENDLN"];
newline = true;
}
else if (eqnType == 2) {
str += type + " " +
type + "_" + removePar(retSigName(signal)) +
operator["START_EQN"] +
qStr + ", " + dStr + ", " + cStr + ", " +
clrStr + ", " + preStr;
if (!is9500() && (type != operator["LD"])) str += ", " + ceStr;
str += operator["END_EQN"] + operator["ENDLN"];
newline = true;
}
if (dEqn != "") {
if (newline) str += nlStr;
if (inregStr) str += inregStr;
str += operator["ASSIGN"] + dEqn;
}
if (cEqn != "") {
if (newline || !eqnType) str += nlStr;
str += operator["ASSIGN"] + cStr + " " + operator["EQUAL"] + " " + cEqn;
}
if (clrEqn != "") {
if (newline || !eqnType) str += nlStr;
str += operator["ASSIGN"] + clrStr + " " + operator["EQUAL"] + " " + clrEqn;
}
if (preEqn != "") {
if (newline || !eqnType) str += nlStr;
str += operator["ASSIGN"] + preStr + " " + operator["EQUAL"] + " " + preEqn;
}
if (ceEqn != "") {
if (newline || !eqnType) str += nlStr;
str += operator["ASSIGN"] + ceStr + " " + operator["EQUAL"] + " " + ceEqn;
}
if (oeEqn != "") {
if (eqnType == 1) {
var oeStr = updateName(sigName, operator["_OE"]);
str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr +
operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] +
operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"];
str += nlStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
}
else if (eqnType == 2) {
var oeStr = updateName(sigName, operator["_OE"]);
str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] + oeStr + operator["OE_WHEN"] + qStr +
operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"];
str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
}
else {
var oeStr = sigName + operator["_OE"];
if (gbltrst[signal])
oeEqn += tabStr + operator["COMMENT"] + " " + operator["GTS_COM"];
str += nlStr + tabStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
}
}
}
return str;
}
function retFamily() {
var family = "xc9500";
if (device.indexOf("XC2C") != -1) {
if (device.indexOf("S") != -1) family = "cr2s";
else family = "xbr";
}
else if (device.indexOf("XCR3") != -1) family = "xpla3";
else {
if (device.indexOf("XL") != -1) family = "xc9500xl";
if (device.indexOf("XV") != -1) family = "xc9500xv";
}
return family;
}
function retDesign() { return design; }
function getPterm(pt, type) {
if (type) return type + " = " + retPterm(pt);
return "PT" + pt.substring(pt.indexOf('_')+1,pt.length) + " = " + retPterm(pt);
}
function getPRLDName(prld) {
if (eqnType != 0) return prld;
else if (prld == "VCC") return "S";
return "R";
}
function retFbnand(signal) {
var str = operator["COMMENT"] + spcStr + "Foldback NAND";
str += nlStr + retSigName(signal) + spcStr + operator["EQUAL"] + spcStr;
for (i=0; i<fbnand[signal].length; i++) {
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
str += retPterm(fbnand[signal][i]);
}
return str;
}
function getEqn(signal) { return retEqn(signal); }
function retUimPterm(pt) {
var str = "";
if (!uimPterms[pt]) return pt;
for (p=0; p<uimPterms[pt].length; p++) {
if (p>0) str += spcStr + operator["AND"] + spcStr;
var sig = uimPterms[pt][p];
if (sig.indexOf("/") != -1) sig = sig.substring(1, sig.length);
str += retSigName(sig);
}
return str;
}
function retUimEqn(signal) {
var str = operator["COMMENT"] + spcStr + "FC Node" + nlStr;
var neg = 0;
if (uimSigNegs[s] == "ON") str += operator["NOT"];
str += retSigName(signal) + spcStr + operator["EQUAL"];
str += retUimPterm(signal) + ";";
return str;
}
function retLegend(url) {
var str = "";
if (!eqnType && !isXC95()) {
str = "Legend: " + "&lt;" + "signame" + "&gt;" + ".COMB = combinational node mapped to ";
str += "the same physical macrocell as the FastInput \"signal\" (not logically related)";
}
else if (eqnType) {
str = "Register Legend:";
if (is9500()) {
str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE);";
str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE);";
str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);";
}
else if (retFamily() == "xbr") {
str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);";
str += nlTabStr + "FDDCPE (Q,D,C,CLR,PRE,CE);";
str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);";
str += nlTabStr + "FTDCPE (Q,D,C,CLR,PRE,CE);";
str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);";
}
else {
str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);";
str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);";
str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);";
}
}
return str;
}

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<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
<html>
<!--(==============================================================)-->
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<head>
<title>Equations</title>
<!--(Meta)==========================================================-->
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<meta name=date content="05 1, 2002 4:30:09 PM">
</head>
<!--(Body)==========================================================-->
<body>
<h1>Equations</h1>
<p><span style="font-size: 10pt; font-family: arial, sans-serif;">The Equations
page provides a list of equations organized by signal name. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You
can use the pulldown menu in the left-hand frame of the page to select
ABEL, VHDL, or Verilog as your language of display.</span> </p>
<p><img src="xml8.jpg"
x-maintain-ratio=TRUE
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width: 181px;
height: 448px;
float: none;"
width=181
height=448
border=0></p>
</body>
</html>

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var warnList = new Array();
var errorList = new Array();
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parent.leftnav.showError();
}
function init() {
if (!document.options) return;
with (document.options) {
if (parent.leftnav.document.options.info.value == 1) info.checked = 1;
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<body>
<h1>Errors/Warnings</h1>
<p class="whs1">The Errors/Warnings
section of the report lists all of the error, warning, and information
messages generated by the fitter. By default, this section will display
the number of each kind of message you have and the full text of the messages,
but checkboxes at the top of the screen allow you to filter message details
as you choose. </p>
<p class="whs2">Checking all
the boxes will give you a display like this:</p>
<p><SCRIPT LANGUAGE="JavaScript"><!--
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function showFBApplet(fb) { parent.leftnav.showAppletFB(fb); }
function showFB(fb) { parent.leftnav.showFB(fb); }
function showMC(mc) { parent.leftnav.showAppletMC(mc); }
function showPT(pterm, type) { parent.leftnav.showPterm(pterm, type); }
function showPin(pin) { parent.leftnav.showAppletPin(pin); }
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function showFBDetail(fb) { parent.leftnav.showFB(fb); }
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<body>
<h1>Function Block Specifics</h1>
<p class="whs1">To access specific
details for a particular function block, click on that function block
in either the <a href="maplogicdoc.htm">Mapped Logic</a>, <a href="mapinputdoc.htm">Mapped
Inputs</a>, or <a href="fbsdoc.htm" style="font-family: arial, sans-serif; font-size: 10pt;">Function
Blocks</a> sections of the fitter report. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The
function block details page displays a table of details about the particular
function block you selected, a view button you can click to show a graphical
display of the function block, and a pulldown menu you can use to select
other function blocks to see.</p>
<p class="whs2">The Table</p>
<p class="whs3">The View</p>
<p><SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='xml5.jpg' x-maintain-ratio='TRUE' width='648' height='397' border='0'>");}
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<h4 class="whs4"><a name=table></a>The Table</h4>
<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The table
at the top of the function block details page provides the following information
about the function block:</FONT></span>
<ul type="disc" class="whs5">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
signal name </FONT></span></li>
</ul>
<p class="whs6"><span style="font-weight: bold;
font-family: arial, sans-serif;
font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><B>Note:</B></FONT></span><span
style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> Clicking on
a signal name will open a new window with the equations for that signal.
</FONT></span></p>
<ul type="disc" class="whs7">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
total product terms used </FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->A
list of product terms</FONT></span></li>
</ul>
<p class="whs8"><span style="font-weight: bold;
font-family: arial, sans-serif;
font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><B>Note:</B></FONT></span><span
style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> Clicking on
a <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->product
term will open a new window with the equations for that term. </FONT></span></p>
<ul type="disc" class="whs9">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
macrocell number in which the function block is located</FONT></span></li>
</ul>
<p class="whs10"><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><span
style="font-weight: bold;"><B>Note:</B></span> Clicking on the underscored macrocell
number will provide a graphical display of the macrocell that looks like
this:</FONT></span></p>
<p class="whs11"><SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' width='540' height='420' border='0'>");}
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<ul type="disc" class="whs12">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
power mode</FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
pin number</FONT></span></li>
</ul>
<ul type="disc" class="whs13">
<li class=kadov-p><p class="whs14"><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><span
style="font-weight: bold;"><B>N</B></span>ote:</FONT></span><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">
Clicking on the underscored pin number will provide the pin layout diagram
for the highlighted pin. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Rolling
your mouse over the colored pin will pop up a tooltip with the signal
name assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->the
I/O style, the slew rate, and/or any constraints assigned to the pin:</FONT></span></p></li>
</ul>
<p class="whs15"><SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
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<ul type="disc" class="whs16">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
pin type</FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
pin use </FONT></span></li>
</ul>
<p class="whs17"><span style="font-weight: bold;
font-family: arial, sans-serif;
font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><B>Note:</B></FONT></span><span
style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> Moving your
mouse cursor over an &quot;I&quot; in the Pin Use column will display
that input signal as a tooltip.</FONT></span></p>
<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Below the
resource table you will find a list of signals used by logic in the function
block you are viewing. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The
list displays output signals as links. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Clicking
on an output signal link will open a new window showing the equations
for that signal.</FONT></span>
<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}-->&nbsp;
<p class="whs18"><span style="font-family: arial, sans-serif;
font-size: 10pt;
font-weight: bold;"><FONT SIZE=2 style="font-size:10pt;"><B>Note:</B></FONT></span><span
style="font-family: arial, sans-serif; font-size: 10pt;"> <FONT SIZE=2 style="font-size:10pt;"><!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->There
is also a <SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
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//--></SCRIPT> button below the table. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Click
this button to open a new window describing all of the acronyms used in
the function block table. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You
can select either brief descriptions or more detailed descriptions by
clicking the &quot;Verbose&quot; button at the top of the window.</FONT></span>
</p>
<h4 class="whs19"><a name=view></a>The View</h4>
<p class="whs20">When you click
on the <SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' width='61' height='53' border='0'>");}
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//--></SCRIPT>button above the table, a new window will open with
a graphical display of the function block you are examining. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The
pins are all color-coded: input pins are green, output pins are blue,
and clocks are magenta:</p>
<p class="whs21"><SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='fb1.gif' x-maintain-ratio='TRUE' width='482' height='378' border='0'>");}
else
{ document.write("<img src='fb1.gif' x-maintain-ratio='TRUE' style='border: none; width: 482px; height: 378px; float: none;' width='482' height='378' border='0'>");}
//--></SCRIPT></p>
<p class="whs22">Right-click
anywhere within the window to pull up a menu that allows you to zoom in
or out for easier viewing. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
<p class="whs23">This menu also
allows you choose to see all of the input connections, all of the output
connections, or both at once. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Like
the pins, the signals are color-coded: inputs are red, outputs are yellow,
and macrocell connections are aqua:</p>
<p class="whs24"><SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='fb.gif' x-maintain-ratio='TRUE' width='497' height='377' border='0'>");}
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//--></SCRIPT></p>
<p class="whs25">To examine
the signals of single pins, simply click the pin whose signals you wish
to see. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->To
examine multiple pins without having to see everything at once, hold down
the control key while you click the pins you want to view. </p>
<p class="whs26">To view the
signals for individual macrocells:</p>
<ul type="disc" class="whs27">
<li class=kadov-p><p class="whs28">Click
the inside edge of the macrocell to display its macrocell connections
and inputs. </p></li>
<li class=kadov-p><p class="whs29">Click
the outer edge to display its output signals</p></li>
<li class=kadov-p><p class="whs30">Click
in the center to display everything</p></li>
<li class=kadov-p><p class="whs31">Double
click in the center to open a new window with a detailed macrocell diagram</p></li>
</ul>
<p class="whs32">&nbsp;</p>
</body>
</html>

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<h1>Function Blocks</h1>
<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The Function
Blocks page provides a summary of all function blocks' resources. Clicking
on one of the function blocks in the summary table will display the <a href="fbs_FBdoc.htm">specific details</a> for that function block. <!--kadov_tag{{<spaces>}}-->&nbsp;</FONT></span><!--kadov_tag{{</spaces>}}-->
<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}-->&nbsp;
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<li class=kadov-p
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function block</FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
number of macrocell used </FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
number of function block inputs used </FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
number of product terms used</FONT></span></li>
<li class=kadov-p
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<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
local control terms used</FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
number of foldback NANDs used (CoolRunner only)</FONT></span></li>
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&nbsp;
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if (parent.applets) parent.applets.printAppletPkg();
else showNoAppletAlert();
}
function popWin(url) {
var win = window.open(url, 'win',
'location=yes,directories=yes,menubar=yes,toolbar=yes,status=yes,scrollbars=yes,resizable=yes,width=800,height=600');
win.focus();
}

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<html><body><pre>
</pre></body></html>

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<html><body><pre>
I/O Style - OD - OpenDrain
- PU - Pullup
- KPR - Keeper
- S - SchmittTrigger
- DG - DataGate
Reg Use - LATCH - Transparent latch
- DFF - D-flip-flop
- DEFF - D-flip-flop with clock enable
- TFF - T-flip-flop
- TDFF - Dual-edge-triggered T-flip-flop
- DDFF - Dual-edge-triggered flip-flop
- DDEFF - Dual-edge-triggered flip-flop with clock enable
/S (after any above flop/latch type) indicates initial state is Set
</pre></body></html>

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<html><body><pre>
Legend: PU - Pull Up
</pre></body></html>

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<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
<html>
<!--(==============================================================)-->
<!--(Document created with RoboEditor. )============================-->
<!--(==============================================================)-->
<head>
<title>Mapped Inputs</title>
<!--(Meta)==========================================================-->
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<meta name=date content="05 24, 2002 5:49:24 PM">
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<body>
<h1>Mapped Inputs</h1>
<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Like the
<a href="maplogicdoc.htm">Mapped Logic</a> section, the Mapped Inputs
section of the report displays a table detailing the resources allocated
by the fitter to mapped inputs. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Again,
the table can be sorted by Signal Name, Function Block, or Pin Number
by clicking on the appropriate table headings. <!--kadov_tag{{<spaces>}}-->&nbsp;</FONT></span><!--kadov_tag{{</spaces>}}-->
<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}-->&nbsp;
<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span
style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The inputs table
contains the following: </FONT></span>
<ul type="disc" class="whs1">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
input signal name </FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
function block number</FONT></span></li>
</ul>
<p class="whs2"><span style="font-weight: bold;"><B>Note:</B></span>
Clicking on the function block will provide a detailed table of all the
block's resources and a graphical display of the function block diagram
(see <a href="fbs_FBdoc.htm">Function Block Specifics</a> for more details).</p>
<ul type="disc" class="whs3">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
macrocell number</FONT></span></li>
</ul>
<ul type="disc" class="whs4">
<li class=kadov-p><p class="whs5"><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><span
style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><span style="font-weight: bold;"><B>N</B></span>ote:</FONT></span>
Clicking on the underscored macrocell number will provide a graphical
display of the macrocell that looks like this:</FONT></span></p></li>
<li class=kadov-p
class=kadov-p><!--kadov_tag{{<implicit_p>}}--><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' width='540' height='420' border='0'>");}
else
{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' style='border: none; width: 540px; height: 420px; float: none;' width='540' height='420' border='0'>");}
//--></SCRIPT>.The pin number</FONT></span></li>
</ul>
<p class="whs6"><span style="font-weight: bold;"><B>Note:</B></span><span
style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> Clicking on
the underscored pin number will provide the pin layout diagram for the
highlighted pin. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Rolling
your mouse over the colored pin will pop up a tooltip with the signal
name assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->the
I/O style, the slew rate, and/or any constraints assigned to the pin:</FONT></span></p>
<p class="whs7"><SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' width='309' height='312' border='0'>");}
else
{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' style='border: none; width: 309px; height: 312px; float: none;' width='309' height='312' border='0'>");}
//--></SCRIPT></p>
<p class="whs8">&nbsp;</p>
<ul type="disc" class="whs9">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
pin type</FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
pin use </FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
I/O standard</FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
I/O style</FONT></span></li>
</ul>
</body>
</html>

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function showFB(fb) { parent.leftnav.showFB(fb); }
function showMC(mc) { parent.leftnav.showAppletMC(mc); }
function showEqn(sig) { parent.leftnav.showEqn(sig); }
function showPin(pin) { parent.leftnav.showAppletPin(pin); }
function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); }
function showTop() { parent.leftnav.showTop(); }
function Sort(x) {
switch (x) {
case 0: parent.leftnav.showMappedLogics(0); break;
case 1: parent.leftnav.showMappedLogics(2); break;
case 2: parent.leftnav.showMappedLogics(4); break;
case 10: parent.leftnav.showMappedInputs(0); break;
case 11: parent.leftnav.showMappedInputs(2); break;
case 12: parent.leftnav.showMappedInputs(4); break;
case 20: parent.leftnav.showUnMappedLogics(0); break;
case 21: parent.leftnav.showUnMappedLogics(2); break;
case 22: parent.leftnav.showUnMappedLogics(4); break;
case 30: parent.leftnav.showUnMappedInputs(0); break;
case 31: parent.leftnav.showUnMappedInputs(2); break;
case 32: parent.leftnav.showUnMappedInputs(4); break;
}
}

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<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
<html>
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<title>Mapped Logic</title>
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--></style><script language="javascript" title="WebHelpInlineScript">
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}
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<body>
<h1>Mapped Logic</h1>
<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The Mapped
Logic section provides a table listing resources allocated by the fitter
to mapped logic. The page will appear in your browser sorted by Signal
Name, but you can choose to sort it by Signal Name, Function Block, and
Pin Number by clicking on the appropriate table headers. </FONT></span>
<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}-->&nbsp;
<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span
style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The Mapped Logic
table contains the following: </FONT></span>
<ul type="disc" class="whs1">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
output signal name </FONT></span></li>
</ul>
<p class="whs2"><span style="font-weight: bold;
font-family: arial, sans-serif;
font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"><B>Note:</B></FONT></span><span
style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> Clicking on
the signal name will open a new window with the equations for that signal.
</FONT></span></p>
<ul type="disc" class="whs3">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
total number of product terms </FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
number of signals used </FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
function block number </FONT></span></li>
</ul>
<p class="whs4"><span style="font-weight: bold;"><B>Note:</B></span>
Clicking on the function block will provide a detailed table of all the
block's resources and a graphical display of the function block diagram
(see <a href="fbs_FBdoc.htm">Function Block Specifics</a> for more details).
</p>
<ul type="disc" class="whs5">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
macrocell number</FONT></span></li>
</ul>
<p class="whs6"><span style="font-weight: bold;"><B>Note:</B></span>
Clicking on the underscored macrocell number will provide a graphical
display of the macrocell that looks like this:</p>
<p class="whs7"><SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' width='540' height='420' border='0'>");}
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{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' style='border: none; width: 540px; height: 420px; float: none;' width='540' height='420' border='0'>");}
//--></SCRIPT>.</p>
<ul type="disc" class="whs8">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
slew rate</FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
pin number</FONT></span></li>
</ul>
<p class="whs9"><span style="font-weight: bold;"><B>Note:</B></span>
Clicking on the underscored pin number will provide the pin layout diagram
for the highlighted pin. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Rolling
your mouse over the colored pin will pop up a tooltip with the signal
name assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->the
I/O style, the slew rate, and/or any constraints assigned to the pin:</p>
<p class="whs10"><SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' width='309' height='312' border='0'>");}
else
{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' style='border: none; width: 309px; height: 312px; float: none;' width='309' height='312' border='0'>");}
//--></SCRIPT></p>
<ul type="disc" class="whs11">
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
pin type</FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
pin use</FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
input register use</FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
I/O standard</FONT></span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
I/O style</FONT></span></li>
</ul>
</body>
</html>

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<html>
<head>
<title></title>
</head>
<frameset frameborder="NO" framespacing="0" border="0" rows="94,*,0,0" cols="*">
<frame name="topnav" src="../tim/topnav.htm" scrolling="no" noresize marginwidth="0" marginheight="0">
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<frame name="leftnav" noresize src="leftnav.htm" marginwidth="0" marginheight="0">
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var is_major = parseInt(navigator.appVersion);
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&& (agt.indexOf('compatible') == -1) && (agt.indexOf('opera')== -1)
&& (agt.indexOf('webtv')==-1) && (agt.indexOf('hotjava')== -1));
var is_nav4up = (is_nav && (is_major >= 4));
var pluginDetected = false;
// we can check for plugin existence only when browser is 'is_ie5up' or 'is_nav4up'
if(is_nav4up) {
// Refresh 'navigator.plugins' to get newly installed plugins.
// Use 'navigator.plugins.refresh(false)' to refresh plugins
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}
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if(navigator.mimeTypes) {
// window.alert( navigator.mimeTypes.length);
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}
}
}
}
if (pluginDetected) {
// show applet page
document.location.href="appletref.htm";
} else if (confirm("Java Plugin 1.4+ not found, Do you want to download it?\n" +
"if you choose not to install the plugin the reports graphical applets will not be available.")) {
document.location.href=XilinxD;
} else {
document.location.href="appletref.htm";
}
}

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<title>Compiler Options</title>
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<h1>Compiler Options</h1>
<p class="whs1">The Compiler
Options page provides all the fitter options settings for the device family
the fitter has selected.</p>
<h1 class="whs2">Fitter Options</h1>
<p class="whs3"><a href="#Basic Tab"
style="font-family: arial, sans-serif; font-size: 10pt;"><span
style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Basic Tab</a></FONT></span></p>
<p class="whs4"><a href="#XPLA Advanced Options"
style="font-family: arial, sans-serif; font-size: 10pt;"><span
style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">XPLA3 Advanced
Options</a></FONT></span></p>
<p class="whs5"><a href="#CoolRunner-II Advanced Options"
style="font-family: arial, sans-serif; font-size: 10pt;"><span
style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">CoolRunner-II
Advanced Options</a></FONT></span></p>
<p class="whs6"><a href="#XC9500/XL/XV Advanced Options"
style="font-family: arial, sans-serif; font-size: 10pt;">XC9500/XL/XV
Advanced Options</a></p>
<h2 class="whs7"><a name="Basic Tab"></a>Basic
Tab</h2>
<p class=whs1
style="font-family: arial, sans-serif; font-size: 10pt;">The CPLD devices
have the following fitter <span style="font-weight: bold;"><B><b>Implementation
Options </B></span><span style="font-weight: bold;"><B>available</B></span></b> in
the <span style="font-weight: bold;"><B>Basic</B></span> tab:</p>
<ul>
<li class=kadov-h4><h4 class="whs8">Use
Multi-Level Logic Optimization</h4></li>
</ul>
<p class="whs9">This option simplifies the total number
of logic expressions in a design, and then collapses the logic in order
to meet user objectives such as density, speed and timing constraints.
This optimization targets CPLD architecture, making it possible to collapse
to the macrocell limits, reduce levels of logic, and minimize the total
number of p-terms.</p>
<p class="whs10">Multi-level Logic Optimization optimizes
all combinatorial logic arcs spanning from an input pad or register output
to an output pad or register input.</p>
<p class="whs11">Multi-level Logic Optimization operates
on combinatorial logic according to the following rules.</p>
<p class="whs12">If timing constraints are set, the program
optimizes for speed to meet timing constraints.</p>
<p class="whs13">If timing constraints are not set, the
program optimizes either for speed or density, depending on the user setting
for the <span style="font-weight: bold;"><B>Use Timing Optimization</B></span>
option.</p>
<ul>
<ul class=whs1
style="list-style: disc;"
type=disc>
<ul class=whs2
style="list-style: circle;"
type=circle>
<li class=kadov-p><p class="whs14">If
<span style="font-weight: bold;"><B>Use Timing Optimization</B></span> is turned
on, the combinatorial logic will be mapped for speed.</p></li>
<li class=kadov-p-Cwhs3><p class=whs3
style="font-family: arial; font-size: 10pt;">If
<span style="font-weight: bold;"><B>Use Timing Optimization</B></span> is turned
off, the combinatorial logic will be mapped for density. The goal of optimization
will then be to reduce the total number of p-terms.</p></li>
</ul>
</ul>
</ul>
<p class="whs15"><font style="font-family: arial; font-size: 10pt;"
face=arial
size=2><span style="font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Logic
marked with the </FONT></span><span style="font-weight: bold;"><B><b style="font-size: 10pt;">NOREDUCE</b></B></span><span
style="font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> property will not be extracted or optimized.</FONT></span></font></p>
<p class=whs3
style="font-family: arial, sans-serif;
font-size: 10pt;
font-weight: bold;
margin-left: 40px;"><span style="font-family: arial; font-weight: normal;">By
default, this option is on.</span> </p>
<ul>
<li class=kadov-p-Cwhs3><p class=whs3
style="font-family: arial, sans-serif;
font-size: 10pt;
font-weight: bold;"><b style="font-weight: bold;"><span
style="font-weight: bold;"><B>Use Timing Constraints -- </B></span><span style="font-weight: normal;">This
option instructs the fitter use Timing Constraints when fitting the design.
<!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->If this
box is not checked, the fitter will ignore timing constraints, if necessary.</span></b></p></li>
<li class=kadov-p-Cwhs3><p class=whs3
style="font-family: arial, sans-serif; font-size: 10pt;"><b
style="font-weight: bold;"><span style="font-weight: bold;"><B>Enable WYSIWYG
Mode -- (CoolRunner only) </B></span><span style="font-weight: normal;">T</span></b>he
goal of the WYSIWYG options is to have a netlist reflect the user's specifications,
as much as possible. All the nodes declared in the HDL design are preserved.
By default, this property is set to Off (Checkbox is not checked) When
this property is On (checkbox is checked), XST:</p></li>
<ul>
<li style="list-style: circle;"
type=circle
class=kadov-p-Cwhs3><p class=whs3
style="font-family: arial, sans-serif; font-size: 10pt;">Preserves
all the user internal signals (nodes)</p></li>
<li style="list-style: circle;"
type=circle
class=kadov-p-Cwhs3><p class=whs3
style="font-family: arial, sans-serif; font-size: 10pt;">Creates
source_node constraints in NGC file for all these nodes.</p></li>
<li style="list-style: circle;"
type=circle
class=kadov-p-Cwhs3><p class=whs3
style="font-family: arial, sans-serif; font-size: 10pt;">Skips
the design optimization (collapse, factorization). Only the Boolean equation
minimization is performed.</p></li>
</ul>
<li class=kadov-p-Cwhs3><p class=whs3
style="font-family: arial, sans-serif; font-size: 10pt;"><b><span
style="font-weight: bold;"><B>Optimization Style</B></span></b>-- The Optimization
Method allows you to select from one of two basic optimization strategies:
<span style="font-weight: bold;"><B><b>Density</b></B></span> or <span style="font-weight: bold;"><B><b>Speed</b></B></span>.
<span style="font-weight: bold;"><B><b>Density</b></B></span> focuses on solely
on density, and <span style="font-weight: bold;"><B><b>Speed</b></B></span> focuses
solely on speed.</p></li>
<li class=kadov-p><p class="whs16"><span
style="font-weight: bold;"><B>Location Constraints</B></span> -- The Try selection
will attempt to fit the design with the pin assignments specified in the
design source. If the design cannot be fit with these pin assignments,
the fitter will remove the location constraints and attempt to fit the
design with no location constraints. A warning message will tell the user
if the location constraints have been removed.</p></li>
<ul class=whs5
style="list-style: circle;"
type=circle>
<li class=kadov-p><p class="whs17">The
<span style="font-weight: bold;"><B><b>Try</b></B></span> selection will attempt
to fit the design with the pin assignments specified in the design source.
If the design cannot be fit with these pin assignments, the fitter will
ignore the pin assignments.</p></li>
</ul>
<li style="list-style: circle;"
type=circle
class=kadov-p-Cwhs6><p class=whs6
style="font-family: arial, sans-serif; font-size: 10pt;">The
<span style="font-weight: bold;"><B>On </B></span>selection will attempt to fit
the design with the pin assignments specified in the design source. If
the design cannot be fit with these pin assignments, the fitter will notify
the user that the device could not fit. It will not unlock the pins under
this option.</p></li>
<li style="list-style: circle;"
type=circle
class=kadov-p-Cwhs7><p class=whs7
style="font-family: arial, sans-serif; font-size: 10pt;">The
<span style="font-weight: bold;"><B>Off</B></span> selection will attempt to
fit the design and will ignore the pin assignments specified in the design
source. If the design can be fit with no pre-assigned pins, the fitter
will assign pins, which can be viewed in the fitter report (filename.fit).
The user should take these pin assignments and incorporate them back into
the design source file. The user will be notified whether the fitting
operation was successful.</p></li>
<li class=kadov-p-Cwhs8><p class=whs8
style="font-family: arial, sans-serif;
font-size: 10pt;
font-weight: bold;"><b><span style="font-weight: bold;"><B>Output
Slew Rate -- </B></span></b><span style="font-weight: normal;">Use this option
to control the default output slew rate. You can control the transition
time of device output pins by setting the slew rate to Slow or Fast. Limiting
the slew rate (Slow) reduces output switching surges in the device. The
default is Fast.</span></p></li>
</ul>
<p class="whs18"><span style="font-weight: bold;"><B>Note</B></span>:
Any explicit slew rate control properties in the design or constraints
file take precedence over this Output Slew Rate setting. </p>
<ul>
<li class=kadov-p-Cwhs8><p class=whs8
style="font-family: arial, sans-serif;
font-size: 10pt;
font-weight: bold;"><b style="font-weight: bold;"><span
style="font-weight: bold;"><B>FF Initial State -- </B></span><span style="font-weight: normal;">Sets
the initial state for all Flip-Flops. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The
options are Low, High and FPGA.</span></b></p></li>
<li class=kadov-p-Cwhs8><p class=whs8
style="font-family: arial, sans-serif;
font-size: 10pt;
font-weight: bold;"><b><span style="font-weight: bold;"><B>Collapsing
P-Term Limit -- </B></span></b><span style="font-weight: normal;">This option
controls the degree to which the fitter flattens a design netlist. A logic
gate can collapse forward into a subsequent gate only if the number of
product terms in the resulting logic function does not exceed the p-term
limit. If the path delay of a logic function is not acceptable, increase
the p-term limit to allow the larger functions to be further flattened.
Choose a number from 3 to 48.</span> </p></li>
<li class=kadov-p-Cwhs8><p class=whs8
style="font-family: arial, sans-serif;
font-size: 10pt;
font-weight: bold;"><b><span style="font-weight: bold;"><B>Collapsing
Input Limit -- </B></span></b><span style="font-weight: normal;">This is a
secondary option for controlling the degree to which the fitter flattens
a design netlist. A logic gate can collapse forward into a subsequent
gate only if the number of inputs in the resulting logic function does
not exceed the input limit. If the design fails to fit the target device
because flattening uses up too many of the function block inputs, decrease
the input limit to prevent flattening of certain high fan-in functions.
</span><!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p></li>
</ul>
<h2 class="whs19"><b><span
style="font-weight: bold;"><B><a name="XPLA Advanced Options"></a>XPLA Advanced
Options</B></span></b></h2>
<p class="whs20"><b><span style="font-weight: normal;">The
following options are available under XPLA </span><span style="font-weight: bold;"><B>Implementation
Options</B></span><span style="font-weight: normal;">, </span><span style="font-weight: bold;"><B>Advanced</B></span><span
style="font-weight: normal;"> tab.</span></b></p>
<ul>
<li class=kadov-p-Cwhs8><p class=whs8
style="font-family: arial, sans-serif;
font-size: 10pt;
font-weight: bold;">Enable Fast
Input Registers -<span style="font-weight: normal;">- Enables the use
of the Fast Input path in XPLA3 devices.</span></p></li>
<li class=kadov-p-Cwhs8><p class=whs8
style="font-family: arial, sans-serif;
font-size: 10pt;
font-weight: bold;">Enable Use
of Foldback NANDs -- <span style="font-weight: normal;">When selected,
the software will use foldback NANDs. This increases the capability to
fit a design, sometimes at the expense of speed.</span></p></li>
<li class=kadov-p-Cwhs8><p class=whs8
style="font-family: arial, sans-serif; font-size: 10pt;"><span
style="font-weight: bold;"><B>Reserve JTAG Pins for ISP -- </B></span>Checking
this box will instruct the fitter to reserve JTAG pins.</p></li>
</ul>
<h2 class="whs21"><a name="CoolRunner-II Advanced Options"></a>CoolRunner-II
Advanced Options</h2>
<p class="whs22">The following
options are found under the Advanced tab for CoolRunner-II devices.</p>
<ul type="disc" class="whs23">
<li class=kadov-h4><h4 class="whs24">Use
Global Clock(s) -- <span style="font-weight: normal;">Select this option
to allow the fitter to assign input pins used as clocks to dedicated global
clock (GCK) pins of the device. If this option is disabled, only pins
identified with the BUFG=CLK property in the design (or UCF file) will
be assigned to GCK device pins. By default, this option is on.</span>
</h4></li>
<li class=kadov-p><p class="whs25"><span
style="font-weight: bold;"><B>Use Global Output Enable(s)</B></span> -- Select
this option to allow the fitter to assign input pins used as output enable
control to dedicated global OE (GTS) pins of the device. If this option
is disabled, only pins identified with the BUFG=OE property in the design
(or UCF file) will be assigned to GTS device pins. By default, this option
is on. </p></li>
<li class=kadov-p><p class="whs26"><span
style="font-weight: bold;"><B>Use Global Set/Reset</B></span> -- Select this
option to allow the fitter to assign input pins used as register asynchronous
reset or preset control to the dedicated global set/reset (GSR) pin of
the device. If this option is disabled, only a pin identified with the
BUFG=SR property in the design (or UCF file) will be assigned to the GSR
device pin. By default, this option is on.</p></li>
<li class=kadov-p><p class="whs27"><span
style="font-weight: bold;"><B>Enable Fast Input Registers</B></span> -- Enables
fast input registers.</p></li>
<li class=kadov-p><p class="whs28"><span
style="font-weight: bold;"><B>Ignore DATA_GATE Attributes</B></span> -- Data
Gate is a power saving property that can be used in CoolRunner-II designs.
<!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->This option
allows you to turn Data Gate off in case you want the fitter to ignore
data gate.</p></li>
<li class=kadov-p><p class="whs29"><span
style="font-weight: bold;"><B>Tristate Outputs Termination Node</B></span> --
The Tristate Output Termination Mode globally sets all tristate outputs
to the specified termination mode. By default, this field is set to Pullup..
<!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The options
are Pullup, Keeper and Float.</p></li>
<li class=kadov-p><p class="whs30"><span
style="font-weight: bold;"><B>Create Programmable Ground Pins on Unused I/O</B></span>
-- The Create Programmable GND Pins on Unused I/O property controls the
option to indicate that you want all unused I/O pads to be configured
as ground pins. This can reduce ground bounce. By default, this option
is set to ground. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The
options are Ground, Pullup, Keeper and Float.</p></li>
<li class=kadov-p>
<p class="whs31"><span style="font-weight: bold;"><B>Default
Output Voltage Standard</B></span> -- set a default voltage standard for CoolRunner-II
device pins.</p>
<p class="whs32">IOSTANDARD
names supported by CoolRunner-II are:</p>
<!--(Table)=====================================================-->
<table x-use-null-cells width="84.797%" cellspacing="0" class="whs33">
<col class="whs34">
<col class="whs35">
<col class="whs36">
<col class="whs37">
<tr valign=top>
<td width="20.209%" class="whs38">
<p class="whs39">I/O Standard</td>
<td width="16.192%" class="whs40">
<p align="center" class="whs41">VCC<span style="vertical-align: Sub;">IO</span></td>
<td width="22.217%" class="whs42">
<p align="center" class="whs43">Input V<span style="vertical-align: Sub;">REF</span></td>
<td width="41.383%" class="whs44">
<p align="center" class="whs45">Board Termination Voltage (V<span style="vertical-align: Sub;">TT</span>)</td></tr>
<tr valign=top>
<td width="20.209%" class="whs46">
<p class="whs47">LVTTL </td>
<td width="16.192%" class="whs48">
<p align="center" class="whs49">3.3V</td>
<td width="22.217%" class="whs50">
<p align="center" class="whs51">N/A</td>
<td width="41.383%" class="whs52">
<p align="center" class="whs53">N/A</td></tr>
<tr valign=top>
<td width="20.209%" class="whs54">
<p class="whs55">LVCMOS33</td>
<td width="16.192%" class="whs56">
<p align="center" class="whs57">3.3V</td>
<td width="22.217%" class="whs58">
<p align="center" class="whs59">N/A</td>
<td width="41.383%" class="whs60">
<p align="center" class="whs61">N/A</td></tr>
<tr valign=top>
<td width="20.209%" class="whs62">
<p class="whs63">LVCMOS25</td>
<td width="16.192%" class="whs64">
<p align="center" class="whs65">2.5V</td>
<td width="22.217%" class="whs66">
<p align="center" class="whs67">N/A</td>
<td width="41.383%" class="whs68">
<p align="center" class="whs69">N/A</td></tr>
<tr valign=top>
<td width="20.209%" class="whs70">
<p class="whs71">LVCMOS18</td>
<td width="16.192%" class="whs72">
<p align="center" class="whs73">1.8V</td>
<td width="22.217%" class="whs74">
<p align="center" class="whs75">N/A</td>
<td width="41.383%" class="whs76">
<p align="center" class="whs77">N/A</td></tr>
<tr valign=top>
<td width="20.209%" class="whs78">
<p class="whs79">LVCMOS15</td>
<td width="16.192%" class="whs80">
<p align="center" class="whs81">1.5V</td>
<td width="22.217%" class="whs82">
<p align="center" class="whs83">N/A</td>
<td width="41.383%" class="whs84">
<p align="center" class="whs85">N/A</td></tr>
<tr valign=top>
<td width="20.209%" class="whs86">
<p class="whs87">HSTL_I</td>
<td width="16.192%" class="whs88">
<p align="center" class="whs89">1.5V</td>
<td width="22.217%" class="whs90">
<p align="center" class="whs91">0.75V</td>
<td width="41.383%" class="whs92">
<p align="center" class="whs93">0.75V</td></tr>
<tr valign=top>
<td width="20.209%" class="whs94">
<p class="whs95">SSTL2_I</td>
<td width="16.192%" class="whs96">
<p align="center" class="whs97">2.5V</td>
<td width="22.217%" class="whs98">
<p align="center" class="whs99">1.25V</td>
<td width="41.383%" class="whs100">
<p align="center" class="whs101">1.25V</td></tr>
<tr valign=top>
<td width="20.209%" class="whs102">
<p class="whs103">SSTL3_I</td>
<td width="16.192%" class="whs104">
<p align="center" class="whs105">3.3V</td>
<td width="22.217%" class="whs106">
<p align="center" class="whs107">1.5V</td>
<td width="41.383%" class="whs108">
<p align="center" class="whs109">1.5V</td></tr>
</table>
<p class="whs110">The software
automatically groups outputs with similar IOSTANDARD settings into the
same bank when no location constraints are specified. </p>
</li>
</ul>
<h2 class="whs111"><a name="XC9500/XL/XV Advanced Options"></a>XC9500/XL/XV
Advanced Options</h2>
<p class="whs112">The following
options are found under the Advanced tab for XC9500/XL/XV. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Note
that additional options for XC9500 only are also described below.</p>
<ul type="disc" class="whs113">
<li class=kadov-h4><h4 class="whs114">Use
Global Clock(s) -- <span style="font-weight: normal;">Select this option
to allow the fitter to assign input pins used as clocks to dedicated global
clock (GCK) pins of the device. If this option is disabled, only pins
identified with the BUFG=CLK property in the design (or UCF file) will
be assigned to GCK device pins. By default, this option is on.</span>
</h4></li>
<li class=kadov-p><p class="whs115"><span
style="font-weight: bold;"><B>Use Global Output Enable(s)</B></span> -- Select
this option to allow the fitter to assign input pins used as output enable
control to dedicated global OE (GTS) pins of the device. If this option
is disabled, only pins identified with the BUFG=OE property in the design
(or UCF file) will be assigned to GTS device pins. By default, this option
is on. </p></li>
<li class=kadov-p><p class="whs116"><span
style="font-weight: bold;"><B>Use Global Set/Reset</B></span> -- Select this
option to allow the fitter to assign input pins used as register asynchronous
reset or preset control to the dedicated global set/reset (GSR) pin of
the device. If this option is disabled, only a pin identified with the
BUFG=SR property in the design (or UCF file) will be assigned to the GSR
device pin. By default, this option is on.</p></li>
<li class=kadov-p><p class="whs117"><span
style="font-weight: bold;"><B>Create Programmable Ground Pins on Unused I/O</B></span>
-- Select this option to indicate that you want all unused I/O pads to
be configured as ground pins. This can reduce ground bounce. By default,
this option is off.</p></li>
<li class=kadov-p><p class="whs118"><span
style="font-weight: bold;"><B>Macrocell Power Setting</B></span> -- Use this
option to control device power consumption. Select Low or Standard to
set the default power mode for the macrocells used to implement the design.
Select Timing Driven to automatically reduce power on paths covered by
timing specifications that can meet speed requirements while operating
in low power. The default is Standard, which results in highest speed.</p></li>
</ul>
<p class="whs119">Note: Any explicit power control (PWR_MODE)
properties in the design or constraints file take precedence over this
Macrocell Power Setting. </p>
<ul type="disc" class="whs120">
<li class=kadov-p><p class="whs121"><span
style="font-weight: bold;"><B>Enable FASTConnect/UIM Optimization (XC9500
only)</B></span> -- Enables optimization of the FASTConnect/UIM for XC9500
devices.</p></li>
<li class=kadov-h4><h4 class="whs122">Use
Local Feedback (XC9500 only)</h4></li>
</ul>
<p class="whs123">Select this option to enable the software
to use local macrocell feedback whenever possible. The local feedback
path, running from each macrocell output to an input of the same function
block, has shorter propagation delay than the global feedback path. The
fitter always tries to use local macrocell feedback (if possible) to satisfy
timing constraints. This option allows the fitter to use local feedback
to generally improve timing on remaining paths. Using local feedback can
speed up your design but could also make it difficult to maintain the
same timing after a design change. By default, this option is on.</p>
<!--(HR)============================================================-->
<hr class=whs4
style="margin-left: 40px; /*begin!kadov{{*/ float: aligncenter; /*}}end!kadov*/ "
align=center>
<p class="whs124"><b><span style="font-weight: bold;"><B>Note:
</B></span></b>To force the fitter to use local feedback, manually map both
the source and load functions into the same function block using the property
<span style="font-weight: bold;"><B><b>LOC=FB</b></B></span><span style="font-style: italic;"><I><i>nn</i></I></span>,
then apply a timespec across the path.&nbsp;</p>
<!--(HR)============================================================-->
<hr class=whs5
style="margin-left: 40px; /*begin!kadov{{*/ float: aligncenter; /*}}end!kadov*/ "
align=center>
<p class="whs125"><span><FONT SIZE=2 style="font-size:10pt;"><b style="font-weight: bold;">Note:
</b></FONT></span>The XC9536 device does not have local feedback.</p>
<!--(HR)============================================================-->
<hr class=whs6
style="margin-left: 40px; /*begin!kadov{{*/ float: aligncenter; /*}}end!kadov*/ "
align=center>
<ul type="disc" class="whs126">
<li class=kadov-h4><h4 class="whs127">Use
Pin Feedback (XC9500 only)</h4></li>
</ul>
<p class="whs128">Select this option to enable the software
to use I/O pin feedback whenever possible. The pin feedback path has slightly
shorter propagation delay than the global feedback path. If this option
is enabled, the software uses the pin feedback path instead of the global
feedback path for macrocell signals that do not drive 3-state outputs
or slew-rate-limited outputs, and where the associated I/O pin is not
used as input-only. By default, this option is on.</p>
</body>
</html>

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rootURL = "http://www.xilinx.com/";
prodURL = "xlnx/xil_prodcat_product.jsp?title=";
cpldURL = "CPLD+Products";
xbrURL = "coolrunner2_page";
xpla3URL = "xpla3_page";
xc9500URL = "xc9500_page";
xc9500xlURL = "xc9500xl_page";
xc9500xvURL = "xc9500xv_page";
marketURL= "esp";
supportURL = "http://www.support.xilinx.com/";
educationURL = "support/education-home.htm";
buyURL = "http://toolbox.xilinx.com/cgi-bin/xilinx.storefront";
contactURL = "company/contact.htm";
searchURL = "company/search.htm";
docURL = rootURL + "xlnx/xweb/xil_publications_display.jsp?" +
"iLanguageID=1" +
"&category=/Data+Sheets/CPLD+Device+Families/";
doc95URL = docURL + "XC9500";
doc95xlURL = docURL + "XC9500XL";
doc95xvURL = docURL + "XC9500XV";
docXpla3URL = docURL + "CoolRunner+XPLA3";
docXbrURL = docURL + "CoolRunner-II";
docCr2sURL = docURL + "CoolRunner-IIS";
var messages = new Array();
messages["fastinreg"] = "Direct Input Register";
messages["inreg"] = "Direct Input Register";
messages["fbnand"] = "Foldback NAND";
messages["fcnode"] = "FC node";
messages["LATCH"] = "Transparent latch";
messages["DFF"] = "D-flip-flop";
messages["DEFF"] = "D-flip-flop with clock enable";
messages["TFF"] = "T-flip-flop";
messages["TDFF"] = "Dual-edge-triggered T-flip-flop";
messages["DDFF"] = "Dual-edge-triggered flip-flop";
messages["DDEFF"] = "Dual-edge-triggered flip-flop with clock enable";

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<html><body><pre>
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
</pre></body></html>

20
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<html><body><pre>
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
KPR = Unused I/O with weak keeper (leave unconnected)
WPU = Unused I/O with weak pull up (leave unconnected)
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
VCCAUX = Power supply for JTAG pins
VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I
VCCIO-1.8 = I/O supply voltage for LVCMOS18
VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I
VREF = Reference voltage for indicated input standard
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
</pre></body></html>

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<html><body><pre>
Legend : NC = Not Connected, unbonded pin
PE = Port Enable pin
WPU = Unused with Internal Weak Pull Up
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
</pre></body></html>

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var specSig = new Array();
var pins = new Array();
var pinsAssign = new Array();
var prohibit = new Array();
var unusedStr = "WPU";
var gndStr = "GND";
var vccStr = "VCC";
var tdiStr = "TDI";
var tdoStr = "TDO";
var tmsStr = "TMS";
var tckStr = "TCK";
function showPin(pin) { parent.leftnav.showAppletPin(pin); }
function printPage() { window.print(); parent.leftnav.printAppletPkg(); }
function showEqn(signal) { parent.leftnav.showEqn(signal); }
function updatePin(type) {
with (document.options) {
switch (type) {
case 0:
if (inp.checked) parent.leftnav.document.options.inOn.value = 1;
else parent.leftnav.document.options.inOn.value = 0;
break;
case 1:
if (out.checked) parent.leftnav.document.options.outOn.value = 1;
else parent.leftnav.document.options.outOn.value = 0;
break;
case 2:
if (glb.checked) parent.leftnav.document.options.glbOn.value = 1;
else parent.leftnav.document.options.glbOn.value = 0;
break;
case 3:
if (isp.checked) parent.leftnav.document.options.ispOn.value = 1;
else parent.leftnav.document.options.ispOn.value = 0;
break;
case 4:
if (vcc.checked) parent.leftnav.document.options.vccOn.value = 1;
else parent.leftnav.document.options.vccOn.value = 0;
break;
case 5:
if (gnd.checked) parent.leftnav.document.options.gndOn.value = 1;
else parent.leftnav.document.options.gndOn.value = 0;
break;
case 6:
if (unuse.checked) parent.leftnav.document.options.unuseOn.value = 1;
else parent.leftnav.document.options.unuseOn.value = 0;
break;
}
}
parent.leftnav.showPinOut();
}
function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); }

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<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
<html>
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<head>
<title>Pin List</title>
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<h1>Pin List</h1>
<p class="whs1">The Pin List
page lists each pin of your design with its pin type and associated signal.
<!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Check boxes
at the top of the table allow you to select and deselect which pin types
you want displayed in the table (the default view will display all of
them).</p>
<p class="whs2"><span style="font-weight: bold;"><B>Note:</B></span>
<!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->There is
a <SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='legend.gif' x-maintain-ratio='TRUE' width='68' height='28' border='0'>");}
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{ document.write("<img src='legend.gif' x-maintain-ratio='TRUE' style='border: none; width: 68px; height: 28px; float: none;' width='68' height='28' border='0'>");}
//--></SCRIPT> button below the table. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Click
this button to open a new window describing all of the acronyms used in
the function block table. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You
can select either brief descriptions or more detailed descriptions by
clicking the &quot;Verbose&quot; button at the top of the window. </p>
<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Clicking
on the underscored pin numbers in the first column of the table will open
a new window displaying the pin layout diagram for the selected pin. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Rolling
your mouse over the colored pin will pop up a tooltip with the signal
name assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->the
I/O style, the slew rate, and/or any constraints assigned to the pin:
</FONT></span>
<p class="whs3"><SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' width='309' height='312' border='0'>");}
else
{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' style='border: none; width: 309px; height: 312px; float: none;' width='309' height='312' border='0'>");}
//--></SCRIPT></p>
<p class="whs4">Clicking any underscored signal in the
third column of the table will open a new window displaying the equations
for that particular signal.</p>
<p class="whs5">Clicking on the <SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' width='61' height='53' border='0'>");}
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{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' style='border: none; width: 61px; height: 53px; float: none;' width='61' height='53' border='0'>");}
//--></SCRIPT>button
at the top of the screen will open a new window with a graphical, top
view of all of the pins: <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
<p class="whs6"><SCRIPT LANGUAGE="JavaScript"><!--
if (navigator.appName=="Netscape")
{ document.write("<img src='pindiagram.gif' x-maintain-ratio='TRUE' width='312' height='318' border='0'>");}
else
{ document.write("<img src='pindiagram.gif' x-maintain-ratio='TRUE' style='border: none; width: 312px; height: 318px; float: none;' width='312' height='318' border='0'>");}
//--></SCRIPT></p>
<p class="whs7">They are color-coded as follows:</p>
<!--(Table)=========================================================-->
<table x-use-null-cells width="63.089%" cellspacing="0" class="whs8">
<col class="whs9">
<col class="whs10">
<tr valign=top>
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<p class="whs12">Color</td>
<td colspan="1" rowspan="1" width="56.431%" class="whs13">
<p class="whs14">Signal</td></tr>
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<p class="whs20">Aqua</td>
<td width="56.431%" class="whs21">
<p class="whs22">Bidirectional</td></tr>
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<td width="43.569%" class="whs23">
<p class="whs24">Blue</td>
<td width="56.431%" class="whs25">
<p class="whs26">Output</td></tr>
<tr valign=top>
<td width="43.569%" class="whs27">
<p class="whs28">Magenta</td>
<td width="56.431%" class="whs29">
<p class="whs30">Clock</td></tr>
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<td width="43.569%" class="whs31">
<p class="whs32">Red</td>
<td width="56.431%" class="whs33">
<p class="whs34">VCC</td></tr>
<tr valign=top>
<td width="43.569%" class="whs35">
<p class="whs36">Black</td>
<td width="56.431%" class="whs37">
<p class="whs38">GND</td></tr>
<tr valign=top>
<td width="43.569%" class="whs39">
<p class="whs40">Yellow</td>
<td width="56.431%" class="whs41">
<p class="whs42">TDO</td></tr>
<tr valign=top>
<td width="43.569%" class="whs43">
<p class="whs44">Gray</td>
<td width="56.431%" class="whs45">
<p class="whs46">TDI</td></tr>
<tr valign=top>
<td width="43.569%" class="whs47">
<p class="whs48">White</td>
<td width="56.431%" class="whs49">
<p class="whs50">Unused Pin</td></tr>
<tr valign=top>
<td width="43.569%" class="whs51">
<p class="whs52">Black Outline</td>
<td width="56.431%" class="whs53">
<p class="whs54">No available
Pad</td></tr>
</table>
<p class="whs55">As with the single pin display, rolling
your mouse over any colored pin will pop up a tooltip with the signal
name assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->the
I/O style, the slew rate, and/or any constraints assigned to the pin.</p>
</body>
</html>

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<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
<html>
<!--(==============================================================)-->
<!--(Document created with RoboEditor. )============================-->
<!--(==============================================================)-->
<head>
<title>Summary</title>
<!--(Meta)==========================================================-->
<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
<meta name=generator-major-version content=0.1>
<meta name=generator-minor-version content=1>
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<meta name=date content="05 24, 2002 11:22:55 AM">
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<!--(Body)==========================================================-->
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<h1>Summary</h1>
<p style="font-size: 10pt;"><span style="font-family: arial, sans-serif;">The
Summary section of the WebFITTER XML report contains several tables summarizing
the fitting results for your design.</span> </p>
<span style="font-family: arial, sans-serif; font-size: 10pt;">The general
Summary table contains the following: </span>
<ul style="list-style: disc;"
type=disc>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The
design name </span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The
fitting status </span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The
software version </span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The
device used, with a link to a PDF version of the device documentation</span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The
time and date of the fitter's completion</span></li>
</ul>
<span style="font-family: arial, sans-serif; font-size: 10pt;">The Resources
Summary table includes:</span><span style="font-size: 10pt;"> </span>
<ul style="list-style: disc;"
type=disc>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The
number and percentage of macrocells used </span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The
number and percentage of product terms used </span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The
number and percentage of registers used</span></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The
number and percentage of pins used <!--kadov_tag{{<spaces>}}-->&nbsp;</span><!--kadov_tag{{</spaces>}}--></li>
<li class=kadov-p
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;">The
number and percentage of function block inputs used</span></li>
</ul>
<span style="font-family: arial, sans-serif; font-size: 10pt;">The tables
that follow give more detailed summaries (when appropriate, depending
on your design and device) of the pin resources, macrocell resources,
global resources, and block resources utilized by the fitter, as well
as the macrocell power data for the design.</span>
</body>
</html>

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143
address_decoder_html/fit/tooltips.js
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/* Your are permitted to reuse this code as long as the following copyright
notice is not removed:
This HTML tip handling is copyright 1998 by insideDHTML.com, LLC. More information about this
code can be found at Inside Dynamic HTML: HTTP://www.insideDHTML.com
*/
// Support for all collection
var allSupport = document.all!=null;
function setupEventObject(e) {
// Map NS event object to IEs
if (e==null) return; // IE returns
window.event = e;
window.event.fromElement = e.target;
window.event.toElement = e.target;
window.event.srcElement = e.target;
window.event.x = e.x;
window.event.y = e.y;
// Route the event to the original element
// Necessary to make sure _tip is set.
window.event.srcElement.handleEvent(e);
}
function checkName(src) {
// Look for tooltip in IE
while ((src!=null) && (src._tip==null))
src = src.parentElement;
return src;
}
function getElement(elName) {
// Get an element from its ID
if (allSupport) return document.all[elName];
else return document.layers[elName];
}
function writeContents(el, tip) {
// Replace the contents of the tooltip
if (allSupport)
el.innerHTML = tip;
else {
// In NS, insert a table to work around
// stylesheet rendering bug.
// NS fails to apply style sheets when writing
// contents into a positioned element.
el.document.open();
el.document.write("<TABLE WIDTH=200 BORDER=1 bordercolor=black><TR><TD WIDTH=100% BGCOLOR=yellow>");
el.document.write(tip);
el.document.write("</TD></TR></TABLE>");
el.document.close();
}
}
function getOffset(el, which) {
// Function for IE to calculate position
// of an element.
var amount = el["offset"+which];
if (which=="Top") amount+=el.offsetHeight;
el = el.offsetParent;
while (el!=null) {
amount+=el["offset"+which];
el = el.offsetParent;
}
return amount;
}
function setPosition(el) {
// Set the position of an element
src = window.event.srcElement
if (allSupport) {
el.style.pixelTop = getOffset(src, "Top");
el.style.pixelLeft = getOffset(src, "Left");
}
else {
el.top = src.y + 20; //window.event.y + 15
el.left = src.x; //window.event.x
}
}
function setVisibility(el, bDisplay) {
// Hide or show to tip
if (bDisplay) {
if (allSupport) el.style.visibility = "visible";
else el.visibility = "show";
}
else {
if (allSupport) el.style.visibility = "hidden";
else el.visibility = "hidden";
}
}
function displayContents(tip) {
// Display the tooltip.
var el = getElement("tipBox");
writeContents(el, tip);
setPosition(el);
setVisibility(el, true);
}
function doMouseOver(e) {
// Mouse moves over an element
setupEventObject(e);
var el, tip;
if ((el = checkName(window.event.srcElement))!=null) {
if (!el._display) {
displayContents(el._tip);
el._display = true;
}
}
}
function doMouseOut(e) {
// Mouse leaves an element
setupEventObject(e);
el = checkName(window.event.srcElement);
var el, tip;
if ((el = checkName(window.event.srcElement))!=null) {
if (el._display) {
if ((el.contains==null) || (!el.contains(window.event.toElement))) {
setVisibility(getElement("tipBox"), false);
el._display = false;
}
}
}
}
function doLoad() {
// Do Loading
if ((window.document.captureEvents==null) && (!allSupport))
return; // Not IE4 or NS4
if (window.document.captureEvents!=null) // NS - capture events
window.document.captureEvents(Event.MOUSEOVER | Event.MOUSEOUT)
window.document.onmouseover = doMouseOver;
window.document.onmouseout = doMouseOut;
}
window.onload = doLoad;

28
address_decoder_html/fit/topnav.js
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function popWin(url) {
var win = window.open(url, 'win',
'location=yes,directories=yes,menubar=yes,toolbar=yes,status=yes,scrollbars=yes,resizable=yes,width=800,height=600');
win.focus();
}
function openTab(type, device) {
var url = rootURL;
switch (type) {
case 0: url = rootURL; break;
case 1:
if (device.indexOf('XC2') != -1) url += prodURL + xbrURL;
else if (device.indexOf('XCR3') != -1) url += prodURL + xpla3URL;
else if (device.indexOf('XV') != -1) url += prodURL + xc9500xvURL;
else if (device.indexOf('XL') != -1) url += prodURL + xc9500xlURL;
else url += prodURL + xc9500URL;
break;
case 2: url += marketURL; break;
case 3: url = supportURL; break;
case 4: url += educationURL; break;
case 5: url = buyURL; break;
case 6: url += contactURL; break;
case 7: url += searchURL; break;
default: url = rootURL;
}
popWin(url);
}

65
address_decoder_html/fit/unmapinputdoc.htm
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<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
<html>
<!--(==============================================================)-->
<!--(Document created with RoboEditor. )============================-->
<!--(==============================================================)-->
<head>
<title>unmapinputdoc</title>
<!--(Meta)==========================================================-->
<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
<meta name=generator-major-version content=0.1>
<meta name=generator-minor-version content=1>
<meta name=filetype content=kadov>
<meta name=filetype-version content=1>
<meta name=page-count content=1>
<meta name=layout-height content=353>
<meta name=layout-width content=615>
<meta name=date content="11 26, 2002 2:10:18 PM">
<style>
<!--
p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
--></style><script language="javascript" title="WebHelpInlineScript">
<!--
function reDo() {
if (innerWidth != origWidth || innerHeight != origHeight)
location.reload();
}
if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
origWidth = innerWidth;
origHeight = innerHeight;
onresize = reDo;
}
//-->
</script><style>
<!--
div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
p.WebHelpNavBar {text-align:right;}
-->
</style>
</head>
<!--(Body)==========================================================-->
<body>
<h1>Unmapped Inputs</h1>
<p class="whs1">This page shows
input signals which were either not mapped or <span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">not
routed.</FONT></span></p>
</body>
</html>

68
address_decoder_html/fit/unmaplogicdoc.htm
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@ -1,68 +0,0 @@
<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
<html>
<!--(==============================================================)-->
<!--(Document created with RoboEditor. )============================-->
<!--(==============================================================)-->
<head>
<title>unmaplogicdoc</title>
<!--(Meta)==========================================================-->
<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
<meta name=generator-major-version content=0.1>
<meta name=generator-minor-version content=1>
<meta name=filetype content=kadov>
<meta name=filetype-version content=1>
<meta name=page-count content=1>
<meta name=layout-height content=353>
<meta name=layout-width content=615>
<meta name=date content="11 26, 2002 2:04:45 PM">
<style>
<!--
p.whs1 {font-size: 22pt; font-weight: bold;}
p.whs2 {font-family: arial, sans-serif; font-size: 10pt; font-weight: normal;}
--></style><script language="javascript" title="WebHelpInlineScript">
<!--
function reDo() {
if (innerWidth != origWidth || innerHeight != origHeight)
location.reload();
}
if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
origWidth = innerWidth;
origHeight = innerHeight;
onresize = reDo;
}
//-->
</script><style>
<!--
div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
p.WebHelpNavBar {text-align:right;}
-->
</style>
</head>
<!--(Body)==========================================================-->
<body>
<p class="whs1">Unmapped Logic</p>
<p class="whs2">This page shows those equations whose
logic was either not placed or not <span style="font-family: arial, sans-serif;
font-size: 10pt;
font-weight: normal;"><FONT SIZE=2 style="font-size:10pt;">completely
placed in the specified device.</FONT></span></p>
</body>
</html>

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