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AppleIISd
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Linear addressing from Cn00

This commit is contained in:
freitz85 2017-10-23 22:42:27 +02:00
parent b0df142692
commit cf98c54e77
5 changed files with 675 additions and 635 deletions
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37
VHDL/AddressDecoder.vhd
View File

@ -41,17 +41,18 @@ entity AddressDecoder is
NRESET : in std_logic;
DATA_EN : out std_logic; -- to CPLD
NG : out std_logic; -- to bus transceiver
NOE : out std_logic); -- to EPROM
NOE : out std_logic;
LED : out std_logic); -- to EPROM
end AddressDecoder;
architecture Behavioral of AddressDecoder is
signal cfxx : std_logic; -- $C800 - $CFFF disable
signal noe_int : std_logic;
signal ndev_sel_int : std_logic;
signal nio_sel_int : std_logic;
signal nio_stb_int : std_logic;
signal ncs : std_logic; -- $C800 - $CFFF enabled
signal a_int : std_logic_vector (11 downto 8);
begin
@ -61,17 +62,27 @@ begin
-- only from the first rising edge of 7M when any select
-- line is low (Phi0 high) to the falling edge of Phi0
B(8) <= A(8) or not A(11);
B(9) <= A(9) or not A(11);
B(10) <= A(10) or not A(11);
DATA_EN <= RNW and not ndev_sel_int and PHI0;
NG <= (ndev_sel_int and noe_int) or not PHI0;
NOE <= noe_int or not PHI0;
noe_int <= not RNW or not ndev_sel_int
or (nio_sel_int and nio_stb_int)
or (nio_sel_int and ncs);
-- $C0xx to $C7xx is mapped to EEPROM bank 0
-- $C8xx to $CExx is mapped to banks 1 to 7
cfxx <= A(8) and A(9) and A(10) and not nio_stb_int;
LED <= ncs;
B(8) <= (a_int(11) and not a_int(8))
or (a_int(11) and a_int(10) and a_int(9));
B(9) <= (a_int(11) and not a_int(9) and a_int(8))
or (a_int(11) and a_int(9) and not a_int(8))
or (a_int(11) and a_int(10) and a_int(9));
B(10) <= (a_int(11) and a_int(10))
or (a_int(11) and a_int(9) and a_int(8));
DATA_EN <= RNW and not NDEV_SEL;
NG <= (ndev_sel_int and nio_sel_int and nio_stb_int)
or (ndev_sel_int and nio_sel_int and ncs)
or not PHI0;
NOE <= not RNW
or not NDEV_SEL
or (not NIO_STB and ncs);
cfxx <= a_int(8) and a_int(9) and a_int(10) and not nio_stb_int;
process(NRESET, nio_sel_int, cfxx)
begin
@ -88,10 +99,12 @@ begin
ndev_sel_int <= '1';
nio_sel_int <= '1';
nio_stb_int <= '1';
a_int <= "0000";
elsif rising_edge(CLK) then
ndev_sel_int <= NDEV_SEL;
nio_sel_int <= NIO_SEL;
nio_stb_int <= NIO_STB;
a_int <= A;
end if;
end process;

19
VHDL/AddressDecoder_Test.vhd
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@ -52,7 +52,8 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
NRESET : IN std_logic;
DATA_EN : OUT std_logic;
NG : OUT std_logic;
NOE : OUT std_logic
NOE : OUT std_logic;
LED : OUT std_logic
);
END COMPONENT;
@ -72,6 +73,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
signal DATA_EN : std_logic;
signal NG : std_logic;
signal NOE : std_logic;
signal LED : std_logic;
-- Clock period definitions
constant CLK_period : time := 142 ns;
@ -91,7 +93,8 @@ BEGIN
NRESET => NRESET,
DATA_EN => DATA_EN,
NG => NG,
NOE => NOE
NOE => NOE,
LED => LED
);
-- Clock process definitions
@ -127,7 +130,7 @@ BEGIN
-- insert stimulus here
-- C0nX access
A <= "0000"; -- must become "111"
A <= "0000"; -- must become "000"
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
wait until falling_edge(PHI0);
@ -135,7 +138,7 @@ BEGIN
wait until rising_edge(PHI0);
-- CnXX access
A <= "0100"; -- must become "111"
A <= "0100"; -- must become "000"
wait until rising_edge(PHI0);
NIO_SEL <= '0';
wait until falling_edge(PHI0);
@ -143,7 +146,7 @@ BEGIN
wait until rising_edge(PHI0);
-- C8xx access, selected
A <= "1000"; -- must become "000"
A <= "1000"; -- must become "001"
wait until rising_edge(PHI0);
NIO_STB <= '0';
wait until falling_edge(PHI0);
@ -151,7 +154,7 @@ BEGIN
wait until rising_edge(PHI0);
-- C9xx access, selected
A <= "1001"; -- must become "001"
A <= "1001"; -- must become "010"
wait until rising_edge(PHI0);
NIO_STB <= '0';
wait until falling_edge(PHI0);
@ -159,7 +162,7 @@ BEGIN
wait until rising_edge(PHI0);
-- CPLD access
A <= "0101"; -- must become "111"
A <= "0101"; -- must become "000"
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
wait until falling_edge(PHI0);
@ -175,7 +178,7 @@ BEGIN
wait until rising_edge(PHI0);
-- C8xx access, unselected
A <= "1000"; -- must become "000"
A <= "1000"; -- must become "001"
wait until rising_edge(PHI0);
NIO_STB <= '0';
wait until falling_edge(PHI0);

1188
VHDL/AppleIISd.jed
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File diff suppressed because it is too large Load Diff

26
VHDL/AppleIISd.vhd
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@ -67,9 +67,6 @@ architecture Behavioral of AppleIISd is
signal data_in : std_logic_vector (7 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal addr_low_int : std_logic_vector (1 downto 0);
signal wp_int : std_logic;
signal card_int : std_logic;
signal miso_int : std_logic;
signal data_en : std_logic;
@ -106,7 +103,8 @@ Port (
NRESET : in std_logic;
DATA_EN : out std_logic;
NG : out std_logic;
NOE : out std_logic
NOE : out std_logic;
LED : out std_logic
);
end component;
@ -120,12 +118,12 @@ begin
phi0 => PHI0,
ndev_sel => NDEV_SEL,
clk => CLK,
miso => miso_int,
miso => MISO,
mosi => MOSI,
sclk => SCLK,
nsel => NSEL,
wp => wp_int,
card => card_int,
wp => WP,
card => CARD,
led => LED
);
@ -142,21 +140,9 @@ begin
DATA_EN => data_en,
NOE => NOE,
NG => NG
--LED => LED
);
ctrl_latch: process(CLK, NRESET)
begin
if(NRESET = '0') then
wp_int <= '1';
card_int <= '1';
miso_int <= '1';
elsif falling_edge(CLK) then
wp_int <= WP;
card_int <= CARD;
miso_int <= MISO;
end if;
end process;
DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
-- synthesis translate_off

40
VHDL/AppleIISd_Test.vhd
View File

@ -190,6 +190,25 @@ BEGIN
wait for ADD_hold;
ADD_LOW <= (others => 'U');
-- select card
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '1');
RNW <= '0';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait for DATA_valid;
DATA <= X"00";
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
--wait for CLK_period;
ADD_LOW <= (others => 'U');
RNW <= '1';
DATA <= (others => 'Z');
-- send data
wait until falling_edge(PHI0);
wait for ADD_valid;
@ -208,9 +227,28 @@ BEGIN
ADD_LOW <= (others => 'U');
RNW <= '1';
DATA <= (others => 'Z');
wait for 20 us;
-- deselect card
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '1');
RNW <= '0';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait for DATA_valid;
DATA <= X"01";
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
--wait for CLK_period;
ADD_LOW <= (others => 'U');
RNW <= '1';
DATA <= (others => 'Z');
-- write ece
wait for 20 us;
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= "01";