4 Commits

Author	SHA1	Message	Date
freitz85	74c6b83b4e	Synthesis guards for debug signals	2017-10-10 21:58:22 +02:00
freitz85	2e4ebd9ac0	Test bench worst and best case timings	2017-10-10 21:22:18 +02:00
freitz85	8a6e7e647e	Test bench	2017-10-10 02:53:21 +02:00
freitz85	b888590d11	Top level in VHDL	2017-10-09 22:35:47 +02:00