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84 lines
3.5 KiB
Markdown
84 lines
3.5 KiB
Markdown
# AppleIISd
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SD card based ProFile replacement for enhanced Apple IIe and IIgs computers
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The **AppleIISd** is a SD card based replaced for the ProFile harddrive. In contrast to other SD card based devices, this card does not replace a Disk II drive. Data is saved directly onto the SD card, not via images on a FAT system, like on other cards. The SD card is accessable with [CiderPress](http://a2ciderpress.com/).
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A Xilinx CPLD is used as a SPI controller and translates, together with the ROM driver, SD card data to/from the Apple IIe. The VHDL source is based on [SPI65/B](http://www.6502.org/users/andre/spi65b) by André Fachat.
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The assembler sources are written for CC65. The [schematics](AppleIISd.pdf) are available as PDF.
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## Features
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* works with ProDOS and GS/OS
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* up to 64MB storage space (2x 65535 blocks)
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* ProDOS driver in ROM
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* Auto boot
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* Access LED
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* Card detect and write protect sensing
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* Skip boot when Open-Apple key is pressed
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## Requirements
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The AppleIISd requires an enhanced IIe or IIgs computer. The ROM code uses some 65c02 opcodes and will therefore not work on a II, II+ or unenhanced IIe. It has been tested in the following combinations:
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* Apple IIgs Rom 01, GS/OS 6.0.4
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* Apple IIgs Rom 01, Prodos 2.4.1
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* Apple IIgs Rom 01, Prodos 1.9
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* Apple IIe enhanced, 128k, Prodos 2.4.1
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* Apple IIe enhanced, 128k, Prodos 1.9
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* Apple IIe enhanced, 64k, Prodos 1.9
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When a 2732 type ROM is used, the binary image has to be programmed at offset 0x800, because A11 is always high for compatibility with 2716 type ROMs.
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## Building the sources
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Be sure to have the newest version of CC65 (V2.16) and some kind of Make instaled, then type one of the following comands:
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```
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make # generate binaries
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make OPTIONS=mapfile,listing # generate mapfile and listing, too
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make clean # delete binaries
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```
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Alternatively use the VisualStudio solution.
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## Timing
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The clock of the SPI bus *SCK* may be derived from either *Phi0* or the *7M* clock. Additionally, the divisor may be 2 to 8.
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The following measurements were taken with the divisor set to 2, resulting in *fSCK* of 500kHz and 3.5MHz. Reading of a byte requires that a dummy byte is sent on the bus, before the answer can be read. Therefore the measurement is the time between sending the byte and receiving the answer. The measurement for reading of a whole 512 byte block includes the SD card commands to do so.
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| Clock | Byte | Block | Image |
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| -----: | -----: | -----: | ------------------------------------------------: |
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| *Phi0* | 17.7µs | 28.8ms | [Byte](Images/Bus1.gif), [Block](Images/Spi1.png) |
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| *7M* | 3.9µs | 15ms | [Byte](Images/Bus2.gif), [Block](Images/Spi2.png) |
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This shows that the required to read a single byte can be reduced significantly by increasing *fSCK* (as one might have guessed). Reading at 500kHz actualy requires NOPs to be inserted (or checking the TC bit in the STATUS register), while reading at 3.5MHz can be done immediately.
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The time for reading a 512 byte block could *only* be halved, but there are for sure opportunities for optimization in the code surrounding the reading.
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```
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* single byte @ 500kHz
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LDA #$FF
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STA $C0C0
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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LDA $C0C0
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* single byte @ 3.5MHz
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LDA #$FF
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STA $C0C0
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LDA $C0C0
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```
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## TODOs
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* Much more testing
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* SRAM option (may never work, though)
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* Enable 4 or 6 volumes under GS/OS
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* Use 28 pin socket to support other EPROMS than 2716 and 2732
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## Known Bugs
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* Does not work with some Z80 cards present
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