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https://github.com/freitz85/AppleIISd.git
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143 lines
3.7 KiB
VHDL
143 lines
3.7 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 20:21:20 10/09/2017
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-- Design Name:
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-- Module Name: U:/AppleIISd/VHDL/AppleIISd_Test.vhd
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-- Project Name: AppleIISd
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: AppleIISd
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY AppleIISd_Test IS
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END AppleIISd_Test;
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ARCHITECTURE behavior OF AppleIISd_Test IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT AppleIISd
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PORT(
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data_in : IN std_logic_vector(7 downto 0);
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data_out : OUT std_logic_vector(7 downto 0);
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is_read : IN std_logic;
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reset : IN std_logic;
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addr : IN std_logic_vector(1 downto 0);
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phi0 : IN std_logic;
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selected : IN std_logic;
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clk : IN std_logic;
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miso : IN std_logic;
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mosi : OUT std_logic;
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sclk : OUT std_logic;
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nsel : OUT std_logic;
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wp : IN std_logic;
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card : IN std_logic;
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led : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal data_in : std_logic_vector(7 downto 0) := (others => '0');
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signal is_read : std_logic := '0';
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signal reset : std_logic := '0';
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signal addr : std_logic_vector(1 downto 0) := (others => '0');
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signal phi0 : std_logic := '1';
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signal selected : std_logic := '0';
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signal clk : std_logic := '0';
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signal miso : std_logic := '0';
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signal wp : std_logic := '0';
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signal card : std_logic := '0';
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--Outputs
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signal data_out : std_logic_vector(7 downto 0);
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signal mosi : std_logic;
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signal sclk : std_logic;
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signal nsel : std_logic;
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signal led : std_logic;
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-- Clock period definitions
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constant clk_period : time := 142 ns; -- 7MHz
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: AppleIISd PORT MAP (
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data_in => data_in,
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data_out => data_out,
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is_read => is_read,
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reset => reset,
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addr => addr,
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phi0 => phi0,
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selected => selected,
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clk => clk,
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miso => miso,
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mosi => mosi,
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sclk => sclk,
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nsel => nsel,
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wp => wp,
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card => card,
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led => led
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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phi0_process :process
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begin
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phi0 <= '1';
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wait for clk_period/14;
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phi0 <= '0';
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wait for clk_period/14;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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reset <= '1';
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wait for 100 ns;
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reset <= '0';
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wait for clk_period*10;
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-- insert stimulus here
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selected <= '1';
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data_in <= (others => '1');
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wait for clk_period * 7;
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selected <= '0';
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wait for clk_period * 10;
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wait;
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end process;
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END;
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