Apple-2-HW/GR8RAM
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GR8RAM/cpld/output_files/GR8RAM.sta.summary

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CPLD firmware compiles
2019-08-31 22:55:04 -04:00
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TimeQuest Timing Analyzer Summary
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Type : Setup 'C7M'
Recompiled just to be sure
2019-10-13 21:18:41 -04:00
Slack : -47.500
Fixed bugs in new PLD stuff
2019-10-20 22:41:24 -04:00
TNS : -2091.500
CPLD firmware compiles
2019-08-31 22:55:04 -04:00
Type : Hold 'C7M'
Slack : 5.000
TNS : 0.000
Type : Minimum Pulse Width 'C7M'
Slack : -4.500
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 15:07:38 -04:00
TNS : -486.000
CPLD firmware compiles
2019-08-31 22:55:04 -04:00
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