2021-03-19 06:56:20 +00:00
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|GR8RAM
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2021-03-19 10:45:31 +00:00
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C25M => Amux[0].CLK
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C25M => Amux[1].CLK
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C25M => Amux[2].CLK
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2021-03-19 06:56:20 +00:00
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C25M => nSWE~reg0.CLK
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C25M => nCAS~reg0.CLK
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C25M => nRAS~reg0.CLK
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C25M => nRCS~reg0.CLK
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C25M => RCKE~reg0.CLK
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2021-03-19 10:45:31 +00:00
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C25M => RefReqd.CLK
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C25M => PS[0].CLK
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C25M => PS[1].CLK
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C25M => PS[2].CLK
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2021-03-19 06:56:20 +00:00
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C25M => SDOE.CLK
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C25M => WRD[6].CLK
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C25M => WRD[7].CLK
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2021-03-19 10:59:22 +00:00
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C25M => DRDIn.CLK
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C25M => SetLim8M.CLK
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C25M => SetFW.CLK
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C25M => DRShift.CLK
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C25M => DRCLK.CLK
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C25M => ARShift.CLK
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C25M => ARCLK.CLK
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2021-03-19 20:38:48 +00:00
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C25M => SS[0].CLK
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C25M => SS[1].CLK
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2021-03-19 06:56:20 +00:00
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C25M => MOSIOE.CLK
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C25M => MOSIout.CLK
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C25M => FCKEN.CLK
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2021-03-19 10:45:31 +00:00
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C25M => FCS.CLK
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2021-03-19 06:56:20 +00:00
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C25M => FCK~reg0.CLK
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C25M => Addr[0].CLK
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C25M => Addr[1].CLK
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C25M => Addr[2].CLK
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C25M => Addr[3].CLK
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C25M => Addr[4].CLK
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C25M => Addr[5].CLK
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C25M => Addr[6].CLK
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C25M => Addr[7].CLK
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C25M => Addr[8].CLK
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C25M => Addr[9].CLK
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C25M => Addr[10].CLK
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C25M => Addr[11].CLK
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C25M => Addr[12].CLK
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C25M => Addr[13].CLK
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C25M => Addr[14].CLK
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C25M => Addr[15].CLK
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C25M => Addr[16].CLK
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C25M => Addr[17].CLK
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C25M => Addr[18].CLK
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C25M => Addr[19].CLK
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C25M => Addr[20].CLK
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C25M => Addr[21].CLK
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C25M => Addr[22].CLK
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C25M => Addr[23].CLK
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2021-03-19 10:45:31 +00:00
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C25M => REGEN.CLK
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C25M => IOROMEN.CLK
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2021-03-19 06:56:20 +00:00
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C25M => nWEcur.CLK
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C25M => RAcur[0].CLK
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C25M => RAcur[1].CLK
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C25M => RAcur[2].CLK
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C25M => RAcur[3].CLK
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C25M => RAcur[4].CLK
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C25M => RAcur[5].CLK
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C25M => RAcur[6].CLK
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C25M => RAcur[7].CLK
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C25M => RAcur[8].CLK
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C25M => RAcur[9].CLK
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C25M => RAcur[10].CLK
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C25M => RAcur[11].CLK
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C25M => RACr.CLK
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2021-03-19 10:45:31 +00:00
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C25M => IOSTRBr.CLK
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C25M => IOSELr.CLK
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2021-03-19 06:56:20 +00:00
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C25M => DEVSELr.CLK
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C25M => nRESout~reg0.CLK
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C25M => LS[0].CLK
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C25M => LS[1].CLK
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C25M => LS[2].CLK
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C25M => LS[3].CLK
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C25M => LS[4].CLK
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C25M => LS[5].CLK
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C25M => LS[6].CLK
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C25M => LS[7].CLK
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C25M => LS[8].CLK
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C25M => LS[9].CLK
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C25M => LS[10].CLK
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C25M => LS[11].CLK
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C25M => LS[12].CLK
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C25M => LS[13].CLK
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C25M => LS[14].CLK
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C25M => LS[15].CLK
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C25M => LS[16].CLK
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C25M => LS[17].CLK
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C25M => nRESr.CLK
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C25M => PHI0r2.CLK
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C25M => PHI0r1.CLK
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C25M => PHI0r0.CLK
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2021-03-19 10:45:31 +00:00
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C25M => nRESr0.CLK
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C25M => IOSTRBr0.CLK
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C25M => IOSELr0.CLK
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2021-03-19 06:56:20 +00:00
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C25M => DEVSELr0.CLK
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2021-03-19 10:45:31 +00:00
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PHI0 => comb.IN1
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2021-03-19 06:56:20 +00:00
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PHI0 => PHI0r0.DATAIN
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nRES => nRESr0.DATAIN
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2021-03-19 10:45:31 +00:00
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nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
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nIOSEL => comb.IN1
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nIOSEL => IOSELr0.DATAIN
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nDEVSEL => comb.IN1
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2021-03-19 06:56:20 +00:00
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nDEVSEL => DEVSELr0.DATAIN
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2021-03-19 10:45:31 +00:00
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nIOSTRB => comb.IN1
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nIOSTRB => IOSTRBr0.DATAIN
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2021-03-19 06:56:20 +00:00
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RA[0] => RAcur[0].DATAIN
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RA[1] => RAcur[1].DATAIN
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RA[2] => RAcur[2].DATAIN
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RA[3] => RAcur[3].DATAIN
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RA[4] => RAcur[4].DATAIN
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RA[5] => RAcur[5].DATAIN
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RA[6] => RAcur[6].DATAIN
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RA[7] => RAcur[7].DATAIN
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RA[8] => RAcur[8].DATAIN
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RA[9] => RAcur[9].DATAIN
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RA[10] => RAcur[10].DATAIN
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RA[11] => RAcur[11].DATAIN
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2021-03-19 18:23:33 +00:00
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RA[12] => Equal1.IN3
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RA[13] => Equal1.IN2
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RA[14] => Equal1.IN1
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RA[15] => Equal1.IN0
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2021-03-19 10:45:31 +00:00
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nWE => comb.IN1
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2021-03-19 06:56:20 +00:00
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nWE => nWEcur.DATAIN
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RAdir <= <VCC>
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RD[0] <> RD[0]
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RD[1] <> RD[1]
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RD[2] <> RD[2]
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RD[3] <> RD[3]
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RD[4] <> RD[4]
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RD[5] <> RD[5]
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RD[6] <> RD[6]
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RD[7] <> RD[7]
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2021-03-19 10:45:31 +00:00
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RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
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SBA[0] <= SBA.DB_MAX_OUTPUT_PORT_TYPE
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SBA[1] <= SBA.DB_MAX_OUTPUT_PORT_TYPE
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2021-03-19 20:38:48 +00:00
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SA[0] <= <GND>
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SA[1] <= <GND>
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SA[2] <= <GND>
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SA[3] <= <GND>
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SA[4] <= <GND>
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SA[5] <= <GND>
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SA[6] <= <GND>
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SA[7] <= <GND>
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SA[8] <= <GND>
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SA[9] <= <GND>
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SA[10] <= <GND>
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SA[11] <= <GND>
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2021-03-19 10:45:31 +00:00
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SA[12] <= SA.DB_MAX_OUTPUT_PORT_TYPE
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2021-03-19 06:56:20 +00:00
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nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
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nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
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nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
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nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
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2021-03-19 10:45:31 +00:00
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DQML <= DQML.DB_MAX_OUTPUT_PORT_TYPE
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DQMH <= DQMH.DB_MAX_OUTPUT_PORT_TYPE
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2021-03-19 06:56:20 +00:00
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RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SD[0] <> SD[0]
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SD[1] <> SD[1]
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SD[2] <> SD[2]
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SD[3] <> SD[3]
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SD[4] <> SD[4]
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SD[5] <> SD[5]
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SD[6] <> SD[6]
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SD[7] <> SD[7]
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nFCS <= FCS.DB_MAX_OUTPUT_PORT_TYPE
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FCK <= FCK~reg0.DB_MAX_OUTPUT_PORT_TYPE
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2021-03-19 10:45:31 +00:00
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MISO => WRD[7].DATAIN
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2021-03-19 06:56:20 +00:00
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MOSI <= MOSI.DB_MAX_OUTPUT_PORT_TYPE
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2021-03-19 10:59:22 +00:00
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|GR8RAM|UFM:UFM_inst
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arclk => arclk.IN1
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ardin => ardin.IN1
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arshft => arshft.IN1
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drclk => drclk.IN1
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drdin => drdin.IN1
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drshft => drshft.IN1
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erase => erase.IN1
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oscena => oscena.IN1
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program => program.IN1
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busy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.busy
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drdout <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.drdout
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osc <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.osc
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rtpbusy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.rtpbusy
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|GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component
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arclk => maxii_ufm_block1.ARCLK
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ardin => maxii_ufm_block1.ARDIN
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arshft => maxii_ufm_block1.ARSHFT
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busy <= maxii_ufm_block1.BUSY
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drclk => maxii_ufm_block1.DRCLK
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drdin => maxii_ufm_block1.DRDIN
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drdout <= maxii_ufm_block1.DRDOUT
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drshft => maxii_ufm_block1.DRSHFT
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erase => maxii_ufm_block1.ERASE
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osc <= maxii_ufm_block1.OSC
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oscena => maxii_ufm_block1.OSCENA
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program => maxii_ufm_block1.PROGRAM
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rtpbusy <= maxii_ufm_block1.BGPBUSY
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