ugh
This commit is contained in:
Zane Kaminski
parent
686fac229e
commit
72851cefc5
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@ -1,21 +1,21 @@
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Init sequence
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Init State SDRAM Flash Other
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Init State SDRAM Flash IS Other
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--------------------------------------------------------------------------------
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$000000-$0FFFBF Wait for Vcc Wait for Vcc
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$000000-$0FFFBF Wait for Vcc Wait for Vcc 0
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$000000 NOP CKE /CS hi, CLK lo
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...
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$0FFF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf
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$0FFF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf
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....
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$0FFFA0 NOP CKE /CS lo, CLK lo
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...
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$0FFFAF NOP CKE /CS lo, CLK lo
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$0FFFB0-$0FFFBF Init: Precharge Send read cmd ($03)
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$0FFFB0 PC all CLK lo, MOSI 0 (b7)
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$0FFFB0-$0FFFBF Init: Precharge Send read cmd ($03) 1
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$0FFFB0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFFB1 NOP CKE CLK hi
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$0FFFB2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFFB3 NOP CKE CLK hi
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$0FFFB3 PC all CLK hi
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$0FFFB4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFFB5 NOP CKE CLK hi
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$0FFFB6 NOP CKE CLK lo, MOSI 0 (b4)
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@ -23,118 +23,278 @@ $0FFFB7 NOP CKE CLK hi
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$0FFFB8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFFB9 NOP CKE CLK hi
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$0FFFBA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFFBB NOP CKE CLK hi
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$0FFFBB Load mode CLK hi
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$0FFFBC NOP CKE CLK lo, MOSI 1 (b1)
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$0FFFBD NOP CKE CLK hi
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$0FFFBE NOP CKE CLK lo, MOSI 1 (b0)
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$0FFFBF NOP CKE CLK hi
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$0FFFC0-$0FFFEF Init: mode & ref Send address ($000000)
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$0FFFC0 Load mode CLK lo, MOSI 0 (b23)
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$0FFFC0-$0FFFEF Init: mode & ref Send address ($000000) 2
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$0FFFC0 NOP CKE CLK lo, MOSI 0 (b23)
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$0FFFC1 NOP CKE CLK hi
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$0FFFC2 NOP CKE CLK lo, MOSI 0 (b22)
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$0FFFC3 NOP CKE CLK hi
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$0FFFC4 AREF CLK lo, MOSI Firmware[1] (b21)
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$0FFFC3 AREF CLK hi
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$0FFFC4 NOP CKE CLK lo, MOSI Firmware[1] (b21)
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$0FFFC5 NOP CKE CLK hi
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$0FFFC6 NOP CKE CLK lo, MOSI Firmware[0] (b20)
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$0FFFC7 NOP CKE CLK hi
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$0FFFC8 NOP CKE CLK lo, MOSI 0 (b19)
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$0FFFC9 NOP CKE CLK hi
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$0FFFCA NOP CKE CLK lo, MOSI 0 (b18)
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$0FFFCB NOP CKE CLK hi
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$0FFFCC AREF CLK lo, MOSI 0 (b17)
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$0FFFCB AREF CLK hi
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$0FFFCC NOP CKE CLK lo, MOSI 0 (b17)
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$0FFFCD NOP CKE CLK hi
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$0FFFCE NOP CKE CLK lo, MOSI 0 (b16)
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$0FFFCF NOP CKE CLK hi
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$0FFFD0 NOP CKE CLK lo, MOSI 0 (b15)
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$0FFFD1 NOP CKE CLK hi
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$0FFFD2 NOP CKE CLK lo, MOSI 0 (b14)
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$0FFFD3 NOP CKE CLK hi
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$0FFFD4 AREF CLK lo, MOSI 0 (b13)
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$0FFFD3 AREF CLK hi
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$0FFFD4 NOP CKE CLK lo, MOSI 0 (b13)
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$0FFFD5 NOP CKE CLK hi
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$0FFFD6 NOP CKE CLK lo, MOSI 0 (b12)
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$0FFFD7 NOP CKE CLK hi
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$0FFFD8 NOP CKE CLK lo, MOSI 0 (b11)
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$0FFFD9 NOP CKE CLK hi
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$0FFFDA NOP CKE CLK lo, MOSI 0 (b10)
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$0FFFDB NOP CKE CLK hi
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$0FFFDC AREF CLK lo, MOSI 0 (b9)
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$0FFFDB AREF CLK hi
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$0FFFDC NOP CKE CLK lo, MOSI 0 (b9)
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$0FFFDD NOP CKE CLK hi
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$0FFFDE NOP CKE CLK lo, MOSI 0 (b8)
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$0FFFDF NOP CKE CLK hi
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$0FFFE0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFFE1 NOP CKE CLK hi
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$0FFFE2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFFE3 NOP CKE CLK hi
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$0FFFE4 AREF CLK lo, MOSI 0 (b5)
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$0FFFE3 AREF CLK hi
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$0FFFE4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFFE5 NOP CKE CLK hi
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$0FFFE6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFFE7 NOP CKE CLK hi
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$0FFFE8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFFE9 NOP CKE CLK hi
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$0FFFEA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFFEB NOP CKE CLK hi
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$0FFFEC AREF CLK lo, MOSI 0 (b1)
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$0FFFEB AREF CLK hi
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$0FFFEC NOP CKE CLK lo, MOSI 0 (b1)
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$0FFFED NOP CKE CLK hi
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$0FFFEE NOP CKE CLK lo, MOSI 0 (b0)
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$0FFFEF NOP CKE CLK hi
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$0FFFF0-$0FFFFF Init: mode & ref 8 dummy clocks
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$0FFFF0-$0FFFFF Init: mode & ref 8 dummy clocks 2
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$0FFFF0 NOP CKE CLK lo, MOSIOE 0
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$0FFFF1 NOP CKE CLK hi
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$0FFFF2 NOP CKE CLK lo
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$0FFFF3 NOP CKE CLK hi
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$0FFFF4 AREF CLK lo
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$0FFFF3 AREF CLK hi
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$0FFFF4 NOP CKE CLK lo
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$0FFFF5 NOP CKE CLK hi
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$0FFFF6 NOP CKE CLK lo
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$0FFFF7 NOP CKE CLK hi
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$0FFFF8 NOP CKE CLK lo
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$0FFFF9 NOP CKE CLK hi
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$0FFFFA NOP CKE CLK lo
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$0FFFFB NOP CKE CLK hi
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$0FFFFC AREF CLK lo
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$0FFFFB AREF CLK hi
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$0FFFFC NOP CKE CLK lo
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$0FFFFD NOP CKE CLK hi
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$0FFFFE NOP CKE CLK lo
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$0FFFFF NOP CKE CLK hi
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Write ROM data Shift in read data
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$100000-$503FFF Write ROM data Shift in read data 3
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$100000 NOP CKE CLK lo
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$100001 NOP CKE CLK hi, get b7:6 of $000000
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$100002 NOP CKE CLK lo
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$100003 NOP CKE CLK hi, get b5:4 of $000000
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$100004 AREF CLK lo
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$100005 NOP CKE CLK hi, get b3:2 of $000000
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$100006 ACT CLK lo
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$100007 NOP CKE CLK hi, get b1:0 of $000000
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$100008 WR AP CLK lo
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$100003 AREF CLK hi, get b5:4 of $000000
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$100004 NOP CKE CLK lo
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$100005 ACT CLK hi, get b3:2 of $000000
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$100006 NOP CKE CLK lo
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$100007 WR AP CLK hi, get b1:0 of $000000
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$100008 NOP CKE CLK lo
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$100009 NOP CKE CLK hi, get b7:6 of $000001
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$10000A NOP CKE CLK lo
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$10000B NOP CKE CLK hi, get b5:4 of $000001
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$10000C AREF CLK lo
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$10000D NOP CKE CLK hi, get b3:2 of $000001
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$10000E ACT CLK lo
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$10000F NOP CKE CLK hi, get b1:0 of $000001
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$10000B AREF CLK hi, get b5:4 of $000001
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$10000C NOP CKE CLK lo
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$10000D ACT CLK hi, get b3:2 of $000001
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$10000E NOP CKE CLK lo
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$10000F WR AP CLK hi, get b1:0 of $000001
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...
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$507FF0 WR AP CLK lo
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$503FF0 NOP CKE CLK lo
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$503FF1 NOP CKE CLK hi, get b7:6 of $0807FE
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$503FF2 NOP CKE CLK lo
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$503FF3 NOP CKE CLK hi, get b5:4 of $0807FE
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$503FF4 AREF CLK lo
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$503FF5 NOP CKE CLK hi, get b3:2 of $0807FE
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$503FF6 ACT CLK lo
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$503FF7 NOP CKE CLK hi, get b1:0 of $0807FE
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$503FF8 WR AP CLK lo
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$503FF3 AREF CLK hi, get b5:4 of $0807FE
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$503FF4 NOP CKE CLK lo
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$503FF5 ACT CLK hi, get b3:2 of $0807FE
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$503FF6 NOP CKE CLK lo
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$503FF7 WR AP CLK hi, get b1:0 of $0807FE
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$503FF8 NOP CKE CLK lo
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$503FF9 NOP CKE CLK hi, get b7:6 of $0807FF
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$503FFA NOP CKE CLK lo
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$503FFB NOP CKE CLK hi, get b5:4 of $0807FF
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$503FFC AREF CLK lo
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$503FFD NOP CKE CLK hi, get b3:2 of $0807FF
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$503FFE ACT CLK lo
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$503FFF NOP CKE CLK hi, get b1:0 of $0807FF
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$504000 WR AP CLK lo, /CS hi
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$504001 NOP CKE CLK lo
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...
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$50400F NOP CKE CLK lo
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$504010 NOP CKE SDRAMActv <= InitActv && ~InitInterrupted
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$503FFB AREF CLK hi, get b5:4 of $0807FF
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$503FFC NOP CKE CLK lo
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$503FFD ACT CLK hi, get b3:2 of $0807FF
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$503FFE NOP CKE CLK lo
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$503FFF WR AP CLK hi, get b1:0 of $0807FF
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$504000 NOP CKE CLK lo, /CS hi 3
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$504001 NOP CKE CLK lo, /CS hi 3
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$504002 NOP CKE CLK lo, /CS hi 3 SDRAMActv <= InitActv && ~InitInterrupted
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...
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$5F5E0F flip 1hz, wrap
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$5F5E0F flip 1hz, wrap
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Init sequence
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Init State SDRAM Flash IS Other
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--------------------------------------------------------------------------------
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$00000-$0FFBF Nothing Nothing 0
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$00000 NOP CKE /CS hi, CLK lo
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...
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$0FF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf
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....
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$0FFA0 NOP CKE /CS lo, CLK lo
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...
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$0FFAF NOP CKE /CS lo, CLK lo
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$0FFB0-$0FFBF Init: Precharge Send read cmd ($03) 1
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$0FFB0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFB1 NOP CKE CLK hi
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$0FFB2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFB3 PC all CLK hi
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$0FFB4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFB5 NOP CKE CLK hi
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$0FFB6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFB7 NOP CKE CLK hi
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$0FFB8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFB9 NOP CKE CLK hi
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$0FFBA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFBB Load mode CLK hi
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$0FFBC NOP CKE CLK lo, MOSI 1 (b1)
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$0FFBD NOP CKE CLK hi
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$0FFBE NOP CKE CLK lo, MOSI 1 (b0)
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$0FFBF NOP CKE CLK hi
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$0FFC0-$0FFEF Init: mode & ref Send address ($000000) 2
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$0FFC0 NOP CKE CLK lo, MOSI 0 (b23)
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$0FFC1 NOP CKE CLK hi
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$0FFC2 NOP CKE CLK lo, MOSI 0 (b22)
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$0FFC3 AREF CLK hi
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$0FFC4 NOP CKE CLK lo, MOSI Firmware[1] (b21)
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$0FFC5 NOP CKE CLK hi
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$0FFC6 NOP CKE CLK lo, MOSI Firmware[0] (b20)
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$0FFC7 NOP CKE CLK hi
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$0FFC8 NOP CKE CLK lo, MOSI 0 (b19)
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$0FFC9 NOP CKE CLK hi
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$0FFCA NOP CKE CLK lo, MOSI 0 (b18)
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$0FFCB AREF CLK hi
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$0FFCC NOP CKE CLK lo, MOSI 0 (b17)
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$0FFCD NOP CKE CLK hi
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$0FFCE NOP CKE CLK lo, MOSI 0 (b16)
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$0FFCF NOP CKE CLK hi
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$0FFD0 NOP CKE CLK lo, MOSI 0 (b15)
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$0FFD1 NOP CKE CLK hi
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$0FFD2 NOP CKE CLK lo, MOSI 0 (b14)
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$0FFD3 AREF CLK hi
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$0FFD4 NOP CKE CLK lo, MOSI 0 (b13)
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$0FFD5 NOP CKE CLK hi
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$0FFD6 NOP CKE CLK lo, MOSI 0 (b12)
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$0FFD7 NOP CKE CLK hi
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$0FFD8 NOP CKE CLK lo, MOSI 0 (b11)
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$0FFD9 NOP CKE CLK hi
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$0FFDA NOP CKE CLK lo, MOSI 0 (b10)
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$0FFDB AREF CLK hi
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$0FFDC NOP CKE CLK lo, MOSI 0 (b9)
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$0FFDD NOP CKE CLK hi
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$0FFDE NOP CKE CLK lo, MOSI 0 (b8)
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$0FFDF NOP CKE CLK hi
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$0FFE0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFE1 NOP CKE CLK hi
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$0FFE2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFE3 AREF CLK hi
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$0FFE4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFE5 NOP CKE CLK hi
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$0FFE6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFE7 NOP CKE CLK hi
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$0FFE8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFE9 NOP CKE CLK hi
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$0FFEA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFEB AREF CLK hi
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$0FFEC NOP CKE CLK lo, MOSI 0 (b1)
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$0FFED NOP CKE CLK hi
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$0FFEE NOP CKE CLK lo, MOSI 0 (b0)
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$0FFEF NOP CKE CLK hi
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$0FFF0-$0FFFF Init: mode & ref 8 dummy clocks 2
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$0FFF0 NOP CKE CLK lo, MOSIOE 0
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$0FFF1 NOP CKE CLK hi
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$0FFF2 NOP CKE CLK lo
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$0FFF3 AREF CLK hi
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$0FFF4 NOP CKE CLK lo
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$0FFF5 NOP CKE CLK hi
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$0FFF6 NOP CKE CLK lo
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$0FFF7 NOP CKE CLK hi
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$0FFF8 NOP CKE CLK lo
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$0FFF9 NOP CKE CLK hi
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$0FFFA NOP CKE CLK lo
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$0FFFB AREF CLK hi
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$0FFFC NOP CKE CLK lo
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$0FFFD NOP CKE CLK hi
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$0FFFE NOP CKE CLK lo
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$0FFFF NOP CKE CLK hi
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$10000-$2FFFF Write ROM data Shift in read data 3
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$10000 NOP CKE CLK lo
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$10001 NOP CKE CLK hi, get b7:6 of $000000
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$10002 NOP CKE CLK lo
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$10003 AREF CLK hi, get b5:4 of $000000
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$10004 NOP CKE CLK lo
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$10005 ACT CLK hi, get b3:2 of $000000
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$10006 NOP CKE CLK lo
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$10007 WR AP CLK hi, get b1:0 of $000000
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$10008 NOP CKE CLK lo
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$10009 NOP CKE CLK hi, get b7:6 of $000001
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$1000A NOP CKE CLK lo
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$1000B AREF CLK hi, get b5:4 of $000001
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$1000C NOP CKE CLK lo
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$1000D ACT CLK hi, get b3:2 of $000001
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$1000E NOP CKE CLK lo
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$1000F WR AP CLK hi, get b1:0 of $000001
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...
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$2FFF0 NOP CKE CLK lo
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$2FFF1 NOP CKE CLK hi, get b7:6 of $003FFE
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$2FFF2 NOP CKE CLK lo
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$2FFF3 AREF CLK hi, get b5:4 of $003FFE
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$2FFF4 NOP CKE CLK lo
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$2FFF5 ACT CLK hi, get b3:2 of $003FFE
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$2FFF6 NOP CKE CLK lo
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$2FFF7 WR AP CLK hi, get b1:0 of $003FFE
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$2FFF8 NOP CKE CLK lo
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$2FFF9 NOP CKE CLK hi, get b7:6 of $003FFF
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$2FFFA NOP CKE CLK lo
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$2FFFB AREF CLK hi, get b5:4 of $003FFF
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$2FFFC NOP CKE CLK lo
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$2FFFD ACT CLK hi, get b3:2 of $003FFF
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$2FFFE NOP CKE CLK lo
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$2FFFF WR AP CLK hi, get b1:0 of $003FFF
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$30000 NOP CKE CLK lo, /CS hi 3
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$30001 NOP CKE CLK lo, /CS hi 3
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$30002 NOP CKE CLK lo, /CS hi 3 SDRAMActv <= InitActv && ~InitInterrupted
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@ -0,0 +1,139 @@
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UFM Load
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LState ARCLK ARShft DRCLK DRShft UFM
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--------------------------------------------------------------------------------
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$0000 0 1 0 0
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$0FBF 0 1 0 0
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...
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$0FC0 1 1 0 0
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$0FC1 1 1 0 0
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$0FC2 0 1 0 0
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$0FC3 0 1 0 0
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$0FC4 1 1 0 0
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$0FC5 1 1 0 0
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$0FC6 0 1 0 0
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$0FC7 0 1 0 0
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$0FC8 1 1 0 0
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$0FC9 1 1 0 0
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$0FCA 0 1 0 0
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$0FCB 0 1 0 0
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$0FCC 1 1 0 0
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$0FCD 1 1 0 0
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$0FCE 0 1 0 0
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$0FCF 0 1 0 0
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$0FD0 1 1 0 0
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$0FD1 1 1 0 0
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$0FD2 0 1 0 0
|
||||
$0FD3 0 1 0 0
|
||||
$0FD4 1 1 0 0
|
||||
$0FD5 1 1 0 0
|
||||
$0FD6 0 1 0 0
|
||||
$0FD7 0 1 0 0
|
||||
$0FD8 1 1 0 0
|
||||
$0FD9 1 1 0 0
|
||||
$0FDA 0 1 0 0
|
||||
$0FDB 0 1 0 0
|
||||
$0FDC 1 1 0 0
|
||||
$0FDD 1 1 0 0
|
||||
$0FDE 0 1 0 0
|
||||
$0FDF 0 1 0 0
|
||||
$0FE0 1 1 0 0
|
||||
$0FE1 1 1 0 0
|
||||
$0FE2 0 1 0 0
|
||||
$0FE3 0 1 0 0
|
||||
$0FE4 1 1 0 0
|
||||
$0FE5 1 1 0 0
|
||||
$0FE6 0 1 0 0
|
||||
$0FE7 0 1 0 0
|
||||
$0FE8 1 1 0 0
|
||||
$0FE9 1 1 0 0
|
||||
$0FEA 0 1 0 0
|
||||
$0FEB 0 1 0 0
|
||||
$0FEC 1 1 0 0
|
||||
$0FED 1 1 0 0
|
||||
$0FEE 0 1 0 0
|
||||
$0FEF 0 1 0 0
|
||||
$0FF0 1 1 0 0
|
||||
$0FF1 1 1 0 0
|
||||
$0FF2 0 1 0 0
|
||||
$0FF3 0 1 0 0
|
||||
$0FF4 1 1 0 0
|
||||
$0FF5 1 1 0 0
|
||||
$0FF6 0 1 0 0
|
||||
$0FF7 0 1 0 0
|
||||
$0FF8 1 1 0 0
|
||||
$0FF9 1 1 0 0
|
||||
$0FFA 0 1 0 0
|
||||
$0FFB 0 1 0 0
|
||||
$0FFC 1 1 0 0
|
||||
$0FFD 1 1 0 0
|
||||
$0FFE 0 1 0 0
|
||||
$0FFF 0 1 0 0
|
||||
|
||||
$1000 0 0 1 0 parallel load into DR
|
||||
$1001 0 0 1 0
|
||||
$1002 0 0 0 1
|
||||
$1003 0 0 0 1
|
||||
$1004 0 0 1 1 SetLoaded <= Dout
|
||||
$1005 0 0 1 1
|
||||
$1006 0 0 0 1
|
||||
$1007 0 0 0 1
|
||||
$1008 0 0 1 1 latch DR[14] (nSetFW[1])
|
||||
$1009 0 0 1 1
|
||||
$100A 0 0 0 1
|
||||
$100B 0 0 0 1
|
||||
$100C 0 0 1 1 latch DR[13] (nSetFW[0])
|
||||
$100D 0 0 1 1
|
||||
$100E 0 0 0 1
|
||||
$100F 0 0 0 1
|
||||
$1010 0 0 0 1 latch DR[12] (nSetLim8M)
|
||||
$1011 0 0 0 1
|
||||
$1012 0 0 0 1
|
||||
$1013 0 0 0 1
|
||||
$1014 0 0 0 1
|
||||
$1015 0 0 0 1
|
||||
$1016 0 0 0 1
|
||||
$1017 0 0 0 1
|
||||
$1018 0 0 0 1
|
||||
$1019 0 0 0 1
|
||||
$101A 0 0 0 1
|
||||
$101B 0 0 0 1
|
||||
$101C 1 0 0 1 Increment address
|
||||
$101D 1 0 0 1
|
||||
$101E 0 0 0 1
|
||||
$101F 0 0 0 1
|
||||
...
|
||||
$2FE0 0 0 1 0 parallel load into DR
|
||||
$2FE1 0 0 1 0
|
||||
$2FE2 0 0 0 1
|
||||
$2FE3 0 0 0 1
|
||||
$2FE4 0 0 1 1 SetLoaded <= Dout
|
||||
$2FE5 0 0 1 1
|
||||
$2FE6 0 0 0 1
|
||||
$2FE7 0 0 0 1
|
||||
$2FE8 0 0 1 1 latch DR[14] (nSetFW[1])
|
||||
$2FE9 0 0 1 1
|
||||
$2FEA 0 0 0 1
|
||||
$2FEB 0 0 0 1
|
||||
$2FEC 0 0 1 1 latch DR[13] (nSetFW[0])
|
||||
$2FED 0 0 1 1
|
||||
$2FEE 0 0 0 1
|
||||
$2FEF 0 0 0 1
|
||||
$2FF0 0 0 0 1 latch DR[12] (nSetLim8M)
|
||||
$2FF1 0 0 0 1
|
||||
$2FF2 0 0 0 1
|
||||
$2FF3 0 0 0 1
|
||||
$2FF4 0 0 0 1
|
||||
$2FF5 0 0 0 1
|
||||
$2FF6 0 0 0 1
|
||||
$2FF7 0 0 0 1
|
||||
$2FF8 0 0 0 1
|
||||
$2FF9 0 0 0 1
|
||||
$2FFA 0 0 0 1
|
||||
$2FFB 0 0 0 1
|
||||
$2FFC 1 0 0 1 Increment address
|
||||
$2FFD 1 0 0 1
|
||||
$2FFE 0 0 0 1
|
||||
$2FFF 0 0 0 1
|
||||
|
||||
$3000 0 0 0 0 Everything 0, set SetLoaded
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 13:41:40 March 15, 2021
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "13:41:40 March 15, 2021"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "GR8RAM"
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 13:41:40 March 15, 2021
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# GR8RAM_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "MAX II"
|
||||
set_global_assignment -name DEVICE EPM240T100C5
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:41:40 MARCH 15, 2021"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
|
||||
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name QIP_FILE UFM.qip
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
||||
807
cpld/GR8RAM.v
807
cpld/GR8RAM.v
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,3 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.0"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"]
|
||||
|
|
@ -0,0 +1,268 @@
|
|||
// megafunction wizard: %ALTUFM_NONE%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: ALTUFM_NONE
|
||||
|
||||
// ============================================================
|
||||
// File Name: UFM.v
|
||||
// Megafunction Name(s):
|
||||
// ALTUFM_NONE
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// maxii
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
|
||||
//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:39:SJ cbx_a_graycounter 2013:06:12:18:03:39:SJ cbx_altufm_none 2013:06:12:18:03:40:SJ cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_lpm_compare 2013:06:12:18:03:40:SJ cbx_lpm_counter 2013:06:12:18:03:40:SJ cbx_lpm_decode 2013:06:12:18:03:40:SJ cbx_lpm_mux 2013:06:12:18:03:40:SJ cbx_maxii 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ cbx_util_mgl 2013:06:12:18:03:40:SJ VERSION_END
|
||||
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
|
||||
// altera message_off 10463
|
||||
|
||||
|
||||
//synthesis_resources = maxii_ufm 1
|
||||
//synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
//synopsys translate_on
|
||||
module UFM_altufm_none_0ep
|
||||
(
|
||||
arclk,
|
||||
ardin,
|
||||
arshft,
|
||||
busy,
|
||||
drclk,
|
||||
drdin,
|
||||
drdout,
|
||||
drshft,
|
||||
erase,
|
||||
osc,
|
||||
oscena,
|
||||
program,
|
||||
rtpbusy) ;
|
||||
input arclk;
|
||||
input ardin;
|
||||
input arshft;
|
||||
output busy;
|
||||
input drclk;
|
||||
input drdin;
|
||||
output drdout;
|
||||
input drshft;
|
||||
input erase;
|
||||
output osc;
|
||||
input oscena;
|
||||
input program;
|
||||
output rtpbusy;
|
||||
|
||||
wire wire_maxii_ufm_block1_bgpbusy;
|
||||
wire wire_maxii_ufm_block1_busy;
|
||||
wire wire_maxii_ufm_block1_drdout;
|
||||
wire wire_maxii_ufm_block1_osc;
|
||||
wire ufm_arclk;
|
||||
wire ufm_ardin;
|
||||
wire ufm_arshft;
|
||||
wire ufm_bgpbusy;
|
||||
wire ufm_busy;
|
||||
wire ufm_drclk;
|
||||
wire ufm_drdin;
|
||||
wire ufm_drdout;
|
||||
wire ufm_drshft;
|
||||
wire ufm_erase;
|
||||
wire ufm_osc;
|
||||
wire ufm_oscena;
|
||||
wire ufm_program;
|
||||
|
||||
maxii_ufm maxii_ufm_block1
|
||||
(
|
||||
.arclk(ufm_arclk),
|
||||
.ardin(ufm_ardin),
|
||||
.arshft(ufm_arshft),
|
||||
.bgpbusy(wire_maxii_ufm_block1_bgpbusy),
|
||||
.busy(wire_maxii_ufm_block1_busy),
|
||||
.drclk(ufm_drclk),
|
||||
.drdin(ufm_drdin),
|
||||
.drdout(wire_maxii_ufm_block1_drdout),
|
||||
.drshft(ufm_drshft),
|
||||
.erase(ufm_erase),
|
||||
.osc(wire_maxii_ufm_block1_osc),
|
||||
.oscena(ufm_oscena),
|
||||
.program(ufm_program)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.ctrl_bgpbusy(1'b0),
|
||||
.devclrn(1'b1),
|
||||
.devpor(1'b1),
|
||||
.sbdin(1'b0),
|
||||
.sbdout()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
maxii_ufm_block1.address_width = 9,
|
||||
maxii_ufm_block1.erase_time = 500000000,
|
||||
maxii_ufm_block1.init_file = "none",
|
||||
maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem2 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem3 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem4 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem5 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem6 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem7 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem8 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.osc_sim_setting = 180000,
|
||||
maxii_ufm_block1.program_time = 1600000,
|
||||
maxii_ufm_block1.lpm_type = "maxii_ufm";
|
||||
assign
|
||||
busy = ufm_busy,
|
||||
drdout = ufm_drdout,
|
||||
osc = ufm_osc,
|
||||
rtpbusy = ufm_bgpbusy,
|
||||
ufm_arclk = arclk,
|
||||
ufm_ardin = ardin,
|
||||
ufm_arshft = arshft,
|
||||
ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy,
|
||||
ufm_busy = wire_maxii_ufm_block1_busy,
|
||||
ufm_drclk = drclk,
|
||||
ufm_drdin = drdin,
|
||||
ufm_drdout = wire_maxii_ufm_block1_drdout,
|
||||
ufm_drshft = drshft,
|
||||
ufm_erase = erase,
|
||||
ufm_osc = wire_maxii_ufm_block1_osc,
|
||||
ufm_oscena = oscena,
|
||||
ufm_program = program;
|
||||
endmodule //UFM_altufm_none_0ep
|
||||
//VALID FILE
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module UFM (
|
||||
arclk,
|
||||
ardin,
|
||||
arshft,
|
||||
drclk,
|
||||
drdin,
|
||||
drshft,
|
||||
erase,
|
||||
oscena,
|
||||
program,
|
||||
busy,
|
||||
drdout,
|
||||
osc,
|
||||
rtpbusy);
|
||||
|
||||
input arclk;
|
||||
input ardin;
|
||||
input arshft;
|
||||
input drclk;
|
||||
input drdin;
|
||||
input drshft;
|
||||
input erase;
|
||||
input oscena;
|
||||
input program;
|
||||
output busy;
|
||||
output drdout;
|
||||
output osc;
|
||||
output rtpbusy;
|
||||
|
||||
wire sub_wire0;
|
||||
wire sub_wire1;
|
||||
wire sub_wire2;
|
||||
wire sub_wire3;
|
||||
wire osc = sub_wire0;
|
||||
wire rtpbusy = sub_wire1;
|
||||
wire drdout = sub_wire2;
|
||||
wire busy = sub_wire3;
|
||||
|
||||
UFM_altufm_none_0ep UFM_altufm_none_0ep_component (
|
||||
.arshft (arshft),
|
||||
.drclk (drclk),
|
||||
.erase (erase),
|
||||
.program (program),
|
||||
.arclk (arclk),
|
||||
.drdin (drdin),
|
||||
.oscena (oscena),
|
||||
.ardin (ardin),
|
||||
.drshft (drshft),
|
||||
.osc (sub_wire0),
|
||||
.rtpbusy (sub_wire1),
|
||||
.drdout (sub_wire2),
|
||||
.busy (sub_wire3));
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
|
||||
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
|
||||
// Retrieval info: CONSTANT: LPM_FILE STRING "UNUSED"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
|
||||
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
|
||||
// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000"
|
||||
// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9"
|
||||
// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk"
|
||||
// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0
|
||||
// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin"
|
||||
// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0
|
||||
// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft"
|
||||
// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0
|
||||
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
|
||||
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
|
||||
// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk"
|
||||
// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0
|
||||
// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin"
|
||||
// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0
|
||||
// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout"
|
||||
// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0
|
||||
// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft"
|
||||
// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0
|
||||
// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase"
|
||||
// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0
|
||||
// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc"
|
||||
// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0
|
||||
// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena"
|
||||
// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0
|
||||
// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program"
|
||||
// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0
|
||||
// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy"
|
||||
// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE
|
||||
// Retrieval info: LIB_FILE: maxii
|
||||
Binary file not shown.
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|
|
@ -0,0 +1,6 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616056850427 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616056850443 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 18 04:40:50 2021 " "Processing started: Thu Mar 18 04:40:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616056850443 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616056850443 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616056850443 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616056851802 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616056851833 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616056852411 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 18 04:40:52 2021 " "Processing ended: Thu Mar 18 04:40:52 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616056852411 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616056852411 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616056852411 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616056852411 ""}
|
||||
Binary file not shown.
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0" ?>
|
||||
<LOG_ROOT>
|
||||
<PROJECT NAME="GR8RAM">
|
||||
</PROJECT>
|
||||
</LOG_ROOT>
|
||||
Binary file not shown.
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Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1 @@
|
|||
v1
|
||||
Binary file not shown.
|
|
@ -0,0 +1,3 @@
|
|||
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Version_Index = 302049280
|
||||
Creation_Time = Mon Mar 15 13:41:40 2021
|
||||
Binary file not shown.
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,233 @@
|
|||
|GR8RAM
|
||||
C25M => SA[0]~reg0.CLK
|
||||
C25M => SA[1]~reg0.CLK
|
||||
C25M => SA[2]~reg0.CLK
|
||||
C25M => SA[3]~reg0.CLK
|
||||
C25M => SA[4]~reg0.CLK
|
||||
C25M => SA[5]~reg0.CLK
|
||||
C25M => SA[6]~reg0.CLK
|
||||
C25M => SA[7]~reg0.CLK
|
||||
C25M => SA[8]~reg0.CLK
|
||||
C25M => SA[9]~reg0.CLK
|
||||
C25M => SA[10]~reg0.CLK
|
||||
C25M => SA[11]~reg0.CLK
|
||||
C25M => SA[12]~reg0.CLK
|
||||
C25M => SBA[0]~reg0.CLK
|
||||
C25M => SBA[1]~reg0.CLK
|
||||
C25M => DQML~reg0.CLK
|
||||
C25M => DQMH~reg0.CLK
|
||||
C25M => nSWE~reg0.CLK
|
||||
C25M => nCAS~reg0.CLK
|
||||
C25M => nRAS~reg0.CLK
|
||||
C25M => nRCS~reg0.CLK
|
||||
C25M => RCKE~reg0.CLK
|
||||
C25M => IS[0].CLK
|
||||
C25M => IS[1].CLK
|
||||
C25M => RefDone.CLK
|
||||
C25M => S[0].CLK
|
||||
C25M => S[1].CLK
|
||||
C25M => S[2].CLK
|
||||
C25M => S[3].CLK
|
||||
C25M => SDOE.CLK
|
||||
C25M => WRD[0].CLK
|
||||
C25M => WRD[1].CLK
|
||||
C25M => WRD[2].CLK
|
||||
C25M => WRD[3].CLK
|
||||
C25M => WRD[4].CLK
|
||||
C25M => WRD[5].CLK
|
||||
C25M => WRD[6].CLK
|
||||
C25M => WRD[7].CLK
|
||||
C25M => DRDIn.CLK
|
||||
C25M => SetLoaded.CLK
|
||||
C25M => SetLim8M.CLK
|
||||
C25M => SetFW[0].CLK
|
||||
C25M => SetFW[1].CLK
|
||||
C25M => DRShift.CLK
|
||||
C25M => DRCLK.CLK
|
||||
C25M => ARShift.CLK
|
||||
C25M => ARCLK.CLK
|
||||
C25M => MOSIOE.CLK
|
||||
C25M => MOSIout.CLK
|
||||
C25M => FCS.CLK
|
||||
C25M => FCKEN.CLK
|
||||
C25M => FCK~reg0.CLK
|
||||
C25M => Bank[1].CLK
|
||||
C25M => Addr[0].CLK
|
||||
C25M => Addr[1].CLK
|
||||
C25M => Addr[2].CLK
|
||||
C25M => Addr[3].CLK
|
||||
C25M => Addr[4].CLK
|
||||
C25M => Addr[5].CLK
|
||||
C25M => Addr[6].CLK
|
||||
C25M => Addr[7].CLK
|
||||
C25M => Addr[8].CLK
|
||||
C25M => Addr[9].CLK
|
||||
C25M => Addr[10].CLK
|
||||
C25M => Addr[11].CLK
|
||||
C25M => Addr[12].CLK
|
||||
C25M => Addr[13].CLK
|
||||
C25M => Addr[14].CLK
|
||||
C25M => Addr[15].CLK
|
||||
C25M => Addr[16].CLK
|
||||
C25M => Addr[17].CLK
|
||||
C25M => Addr[18].CLK
|
||||
C25M => Addr[19].CLK
|
||||
C25M => Addr[20].CLK
|
||||
C25M => Addr[21].CLK
|
||||
C25M => Addr[22].CLK
|
||||
C25M => Addr[23].CLK
|
||||
C25M => RAMSEL.CLK
|
||||
C25M => nWEcur.CLK
|
||||
C25M => RAcur[0].CLK
|
||||
C25M => RAcur[1].CLK
|
||||
C25M => RAcur[2].CLK
|
||||
C25M => RAcur[3].CLK
|
||||
C25M => RAcur[4].CLK
|
||||
C25M => RAcur[5].CLK
|
||||
C25M => RAcur[6].CLK
|
||||
C25M => RAcur[7].CLK
|
||||
C25M => RAcur[8].CLK
|
||||
C25M => RAcur[9].CLK
|
||||
C25M => RAcur[10].CLK
|
||||
C25M => RAcur[11].CLK
|
||||
C25M => RACr.CLK
|
||||
C25M => DEVSELr.CLK
|
||||
C25M => SDRAMActv.CLK
|
||||
C25M => InitActv.CLK
|
||||
C25M => CmdActv.CLK
|
||||
C25M => InitIntr.CLK
|
||||
C25M => nRESout~reg0.CLK
|
||||
C25M => LS[0].CLK
|
||||
C25M => LS[1].CLK
|
||||
C25M => LS[2].CLK
|
||||
C25M => LS[3].CLK
|
||||
C25M => LS[4].CLK
|
||||
C25M => LS[5].CLK
|
||||
C25M => LS[6].CLK
|
||||
C25M => LS[7].CLK
|
||||
C25M => LS[8].CLK
|
||||
C25M => LS[9].CLK
|
||||
C25M => LS[10].CLK
|
||||
C25M => LS[11].CLK
|
||||
C25M => LS[12].CLK
|
||||
C25M => LS[13].CLK
|
||||
C25M => LS[14].CLK
|
||||
C25M => LS[15].CLK
|
||||
C25M => LS[16].CLK
|
||||
C25M => LS[17].CLK
|
||||
C25M => nBODf.CLK
|
||||
C25M => nBODf0.CLK
|
||||
C25M => nRESr.CLK
|
||||
C25M => nBODr.CLK
|
||||
C25M => nRESr0.CLK
|
||||
C25M => nBODr0.CLK
|
||||
C25M => PHI0r2.CLK
|
||||
C25M => PHI0r1.CLK
|
||||
C25M => PHI0r0.CLK
|
||||
C25M => DEVSELr0.CLK
|
||||
PHI0 => PHI0r0.DATAIN
|
||||
nBOD => nBODr0.DATAIN
|
||||
nRES => nRESr0.DATAIN
|
||||
nIOSEL => ~NO_FANOUT~
|
||||
nDEVSEL => DEVSELr0.DATAIN
|
||||
nIOSTRB => ~NO_FANOUT~
|
||||
RA[0] => RAcur[0].DATAIN
|
||||
RA[1] => RAcur[1].DATAIN
|
||||
RA[2] => RAcur[2].DATAIN
|
||||
RA[3] => RAcur[3].DATAIN
|
||||
RA[4] => RAcur[4].DATAIN
|
||||
RA[5] => RAcur[5].DATAIN
|
||||
RA[6] => RAcur[6].DATAIN
|
||||
RA[7] => RAcur[7].DATAIN
|
||||
RA[8] => RAcur[8].DATAIN
|
||||
RA[9] => RAcur[9].DATAIN
|
||||
RA[10] => RAcur[10].DATAIN
|
||||
RA[11] => RAcur[11].DATAIN
|
||||
RA[12] => Equal3.IN3
|
||||
RA[13] => Equal3.IN2
|
||||
RA[14] => Equal3.IN1
|
||||
RA[15] => Equal3.IN0
|
||||
nWE => nWEcur.DATAIN
|
||||
RAdir <= <VCC>
|
||||
RD[0] <> RD[0]
|
||||
RD[1] <> RD[1]
|
||||
RD[2] <> RD[2]
|
||||
RD[3] <> RD[3]
|
||||
RD[4] <> RD[4]
|
||||
RD[5] <> RD[5]
|
||||
RD[6] <> RD[6]
|
||||
RD[7] <> RD[7]
|
||||
RDdir <= <VCC>
|
||||
DMAin => DMAout.DATAIN
|
||||
DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE
|
||||
INTin => INTout.DATAIN
|
||||
INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
|
||||
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SD[0] <> SD[0]
|
||||
SD[1] <> SD[1]
|
||||
SD[2] <> SD[2]
|
||||
SD[3] <> SD[3]
|
||||
SD[4] <> SD[4]
|
||||
SD[5] <> SD[5]
|
||||
SD[6] <> SD[6]
|
||||
SD[7] <> SD[7]
|
||||
nFCS <= FCS.DB_MAX_OUTPUT_PORT_TYPE
|
||||
FCK <= FCK~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
MISO => WRD.DATAB
|
||||
MOSI <= MOSI.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|GR8RAM|UFM:UFM_inst
|
||||
arclk => arclk.IN1
|
||||
ardin => ardin.IN1
|
||||
arshft => arshft.IN1
|
||||
drclk => drclk.IN1
|
||||
drdin => drdin.IN1
|
||||
drshft => drshft.IN1
|
||||
erase => erase.IN1
|
||||
oscena => oscena.IN1
|
||||
program => program.IN1
|
||||
busy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.busy
|
||||
drdout <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.drdout
|
||||
osc <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.osc
|
||||
rtpbusy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.rtpbusy
|
||||
|
||||
|
||||
|GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component
|
||||
arclk => maxii_ufm_block1.ARCLK
|
||||
ardin => maxii_ufm_block1.ARDIN
|
||||
arshft => maxii_ufm_block1.ARSHFT
|
||||
busy <= maxii_ufm_block1.BUSY
|
||||
drclk => maxii_ufm_block1.DRCLK
|
||||
drdin => maxii_ufm_block1.DRDIN
|
||||
drdout <= maxii_ufm_block1.DRDOUT
|
||||
drshft => maxii_ufm_block1.DRSHFT
|
||||
erase => maxii_ufm_block1.ERASE
|
||||
osc <= maxii_ufm_block1.OSC
|
||||
oscena => maxii_ufm_block1.OSCENA
|
||||
program => maxii_ufm_block1.PROGRAM
|
||||
rtpbusy <= maxii_ufm_block1.BGPBUSY
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,50 @@
|
|||
<TABLE>
|
||||
<TR bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >UFM_inst|UFM_altufm_none_0ep_component</TD>
|
||||
<TD >9</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >UFM_inst</TD>
|
||||
<TD >9</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >4</TD>
|
||||
<TD >2</TD>
|
||||
<TD >2</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
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|
|
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|
|||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; UFM_inst|UFM_altufm_none_0ep_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; UFM_inst ; 9 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
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|
|
@ -0,0 +1 @@
|
|||
v1
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616136944860 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 02:55:44 2021 " "Processing started: Fri Mar 19 02:55:44 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616136946282 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136946532 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136946548 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(126) " "Verilog HDL warning at gr8ram.v(126): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136946845 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(410) " "Verilog HDL warning at gr8ram.v(410): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136946845 ""}
|
||||
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(545) " "Verilog HDL Expression warning at gr8ram.v(545): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 545 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136946845 ""}
|
||||
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(558) " "Verilog HDL Expression warning at gr8ram.v(558): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 558 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136946845 ""}
|
||||
{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946860 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616136946860 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(275) " "Verilog HDL Implicit Net warning at gr8ram.v(275): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136946860 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(278) " "Verilog HDL Implicit Net warning at gr8ram.v(278): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136946860 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616136946892 ""}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "REGEN gr8ram.v(112) " "Verilog HDL or VHDL warning at gr8ram.v(112): object \"REGEN\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 112 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(127) " "Verilog HDL warning at gr8ram.v(127): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(280) " "Verilog HDL or VHDL warning at gr8ram.v(280): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 280 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(282) " "Verilog HDL or VHDL warning at gr8ram.v(282): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 282 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(39) " "Verilog HDL assignment warning at gr8ram.v(39): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(147) " "Verilog HDL assignment warning at gr8ram.v(147): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 147 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(154) " "Verilog HDL assignment warning at gr8ram.v(154): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(160) " "Verilog HDL assignment warning at gr8ram.v(160): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(426) " "Verilog HDL assignment warning at gr8ram.v(426): truncated value with size 32 to match size of target (4)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 426 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(547) " "Verilog HDL assignment warning at gr8ram.v(547): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 547 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(635) " "Verilog HDL assignment warning at gr8ram.v(635): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 635 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946938 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(127) " "Net \"RDout\" at gr8ram.v(127) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616136946938 "|GR8RAM"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616136947142 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616136947204 ""}
|
||||
{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 181 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616136948751 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616136948751 ""}
|
||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 88 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "RDdir VCC " "Pin \"RDdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RDdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "RCKE VCC " "Pin \"RCKE\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 448 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RCKE"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616136949454 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nIOSEL " "No output dependent on input pin \"nIOSEL\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136950063 "|GR8RAM|nIOSEL"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nIOSTRB " "No output dependent on input pin \"nIOSTRB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136950063 "|GR8RAM|nIOSTRB"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1616136950063 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "417 " "Implemented 417 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_LCELLS" "343 " "Implemented 343 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616136950095 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616136950095 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616136950376 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 02:55:50 2021 " "Processing ended: Fri Mar 19 02:55:50 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""}
|
||||
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|
@ -0,0 +1,4 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616136540772 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616136540788 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 02:49:00 2021 " "Processing started: Fri Mar 19 02:49:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616136540788 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616136540788 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp GR8RAM -c GR8RAM --netlist_type=sgate " "Command: quartus_rpp GR8RAM -c GR8RAM --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616136540788 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "202 " "Peak virtual memory: 202 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136541319 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 02:49:01 2021 " "Processing ended: Fri Mar 19 02:49:01 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136541319 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136541319 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136541319 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616136541319 ""}
|
||||
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|
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|
|||
FIT
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616056855068 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616056855083 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 18 04:40:54 2021 " "Processing started: Thu Mar 18 04:40:54 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616056855083 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616056855083 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616056855099 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616056855286 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616056856161 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616056856365 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616056856365 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616056856536 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616056856896 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616056857052 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616056857052 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616056857115 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616056857240 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.447 -415.877 C25M " " -8.447 -415.877 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.286 " "Worst-case hold slack is -16.286" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.286 -16.286 DRCLK " " -16.286 -16.286 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 ARCLK " " -16.276 -16.276 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.579 -1.579 C25M " " -1.579 -1.579 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616056857333 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616056857365 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616056857677 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616056857833 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616056857833 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 18 04:40:58 2021 " "Processing ended: Thu Mar 18 04:40:58 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""}
|
||||
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|
|
@ -0,0 +1,33 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616136912610 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 02:55:12 2021 " "Processing started: Fri Mar 19 02:55:12 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616136914344 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136914672 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136914672 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136914672 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136914672 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616136914672 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(126) " "Verilog HDL warning at gr8ram.v(126): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(410) " "Verilog HDL warning at gr8ram.v(410): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(545) " "Verilog HDL Expression warning at gr8ram.v(545): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 545 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(558) " "Verilog HDL Expression warning at gr8ram.v(558): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 558 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136914954 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(275) " "Verilog HDL Implicit Net warning at gr8ram.v(275): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(278) " "Verilog HDL Implicit Net warning at gr8ram.v(278): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616136914985 ""}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "REGEN gr8ram.v(112) " "Verilog HDL or VHDL warning at gr8ram.v(112): object \"REGEN\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 112 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(127) " "Verilog HDL warning at gr8ram.v(127): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(280) " "Verilog HDL or VHDL warning at gr8ram.v(280): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 280 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(282) " "Verilog HDL or VHDL warning at gr8ram.v(282): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 282 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(39) " "Verilog HDL assignment warning at gr8ram.v(39): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(147) " "Verilog HDL assignment warning at gr8ram.v(147): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 147 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(154) " "Verilog HDL assignment warning at gr8ram.v(154): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(160) " "Verilog HDL assignment warning at gr8ram.v(160): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(426) " "Verilog HDL assignment warning at gr8ram.v(426): truncated value with size 32 to match size of target (4)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 426 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(547) " "Verilog HDL assignment warning at gr8ram.v(547): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 547 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(635) " "Verilog HDL assignment warning at gr8ram.v(635): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 635 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(127) " "Net \"RDout\" at gr8ram.v(127) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
|
||||
{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "FCK gr8ram.v(190) " "Can't resolve multiple constant drivers for net \"FCK\" at gr8ram.v(190)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 190 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1616136915016 ""}
|
||||
{ "Error" "EVRFX_VDB_NET_ANOTHER_DRIVER" "gr8ram.v(187) " "Constant driver at gr8ram.v(187)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 187 0 0 } } } 0 10029 "Constant driver at %1!s!" 0 0 "Quartus II" 0 -1 1616136915016 ""}
|
||||
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Can't elaborate top-level user hierarchy" { } { } 0 12153 "Can't elaborate top-level user hierarchy" 0 0 "Quartus II" 0 -1 1616136915016 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616136915188 ""}
|
||||
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 17 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 3 errors, 17 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136915532 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 19 02:55:15 2021 " "Processing ended: Fri Mar 19 02:55:15 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""}
|
||||
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 17 s " "Quartus II Full Compilation was unsuccessful. 5 errors, 17 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136916625 ""}
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
ERASE_TIME=500000000
|
||||
INTENDED_DEVICE_FAMILY="MAX II"
|
||||
LPM_FILE=UNUSED
|
||||
LPM_HINT=UNUSED
|
||||
LPM_TYPE=altufm_none
|
||||
OSC_FREQUENCY=180000
|
||||
PORT_ARCLKENA=PORT_UNUSED
|
||||
PORT_DRCLKENA=PORT_UNUSED
|
||||
PROGRAM_TIME=1600000
|
||||
WIDTH_UFM_ADDRESS=9
|
||||
DEVICE_FAMILY="MAX II"
|
||||
CBX_AUTO_BLACKBOX=ALL
|
||||
arclk
|
||||
ardin
|
||||
arshft
|
||||
busy
|
||||
drclk
|
||||
drdin
|
||||
drdout
|
||||
drshft
|
||||
erase
|
||||
osc
|
||||
oscena
|
||||
program
|
||||
rtpbusy
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
This folder contains data for incremental compilation.
|
||||
|
||||
The compiled_partitions sub-folder contains previous compilation results for each partition.
|
||||
As long as this folder is preserved, incremental compilation results from earlier compiles
|
||||
can be re-used. To perform a clean compilation from source files for all partitions, both
|
||||
the db and incremental_db folder should be removed.
|
||||
|
||||
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
|
||||
As long as this folder is preserved, imported partitions will be automatically re-imported
|
||||
when the db or incremental_db/compiled_partitions folders are removed.
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Version_Index = 302049280
|
||||
Creation_Time = Thu Mar 18 03:51:58 2021
|
||||
Binary file not shown.
|
|
@ -0,0 +1,114 @@
|
|||
Assembler report for GR8RAM
|
||||
Thu Mar 18 04:40:52 2021
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof
|
||||
6. Assembler Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Thu Mar 18 04:40:52 2021 ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
+-----------------------+---------------------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------+
|
||||
; Assembler Settings ;
|
||||
+-----------------------------------------------------------------------------+-----------+---------------+
|
||||
; Option ; Setting ; Default Value ;
|
||||
+-----------------------------------------------------------------------------+-----------+---------------+
|
||||
; Use smart compilation ; Off ; Off ;
|
||||
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
||||
; Enable compact report table ; Off ; Off ;
|
||||
; Compression mode ; Off ; Off ;
|
||||
; Clock source for configuration device ; Internal ; Internal ;
|
||||
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
|
||||
; Divide clock frequency by ; 1 ; 1 ;
|
||||
; Auto user code ; On ; On ;
|
||||
; Security bit ; Off ; Off ;
|
||||
; Use configuration device ; On ; On ;
|
||||
; Configuration device ; Auto ; Auto ;
|
||||
; Configuration device auto user code ; Off ; Off ;
|
||||
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
|
||||
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
|
||||
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
|
||||
; Hexadecimal Output File start address ; 0 ; 0 ;
|
||||
; Hexadecimal Output File count direction ; Up ; Up ;
|
||||
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
|
||||
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
|
||||
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
|
||||
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
|
||||
; In-System Programming Default Clamp State ; Tri-state ; Tri-state ;
|
||||
+-----------------------------------------------------------------------------+-----------+---------------+
|
||||
|
||||
|
||||
+----------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+----------------------------------------------+
|
||||
; File Name ;
|
||||
+----------------------------------------------+
|
||||
; Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||
+----------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------+
|
||||
; Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||
+----------------+-------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+-------------------------------------------------------+
|
||||
; Device ; EPM240T100C5 ;
|
||||
; JTAG usercode ; 0x00178E81 ;
|
||||
; Checksum ; 0x001792F1 ;
|
||||
+----------------+-------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
; Assembler Messages ;
|
||||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Assembler
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Thu Mar 18 04:40:50 2021
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 293 megabytes
|
||||
Info: Processing ended: Thu Mar 18 04:40:52 2021
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
Fri Mar 19 02:49:01 2021
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,6 @@
|
|||
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176244): Moving registers into LUTs to improve timing and density
|
||||
Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00
|
||||
Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00
|
||||
Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
Fitter Status : Failed - Fri Mar 19 02:55:57 2021
|
||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : GR8RAM
|
||||
Top-level Entity Name : GR8RAM
|
||||
Family : MAX II
|
||||
Device : EPM240T100C5
|
||||
Timing Models : Final
|
||||
Total logic elements : 313 / 240 ( 130 % )
|
||||
Total pins : 73 / 80 ( 91 % )
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
Flow report for GR8RAM
|
||||
Fri Mar 19 02:55:57 2021
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Flow Summary
|
||||
3. Flow Settings
|
||||
4. Flow Non-Default Global Settings
|
||||
5. Flow Elapsed Time
|
||||
6. Flow OS Summary
|
||||
7. Flow Log
|
||||
8. Flow Messages
|
||||
9. Flow Suppressed Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+---------------------------+-------------------------------------------------+
|
||||
; Flow Status ; Flow Failed - Fri Mar 19 02:55:57 2021 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 313 / 240 ( 130 % ) ;
|
||||
; Total pins ; 73 / 80 ( 91 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+---------------------------+-------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
; Flow Settings ;
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 03/19/2021 02:55:46 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
+-------------------+---------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Non-Default Global Settings ;
|
||||
+---------------------------------------+--------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+---------------------------------------+--------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 44085571633675.161613694503328 ; -- ; -- ; -- ;
|
||||
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
|
||||
; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ;
|
||||
; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ;
|
||||
; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
|
||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
|
||||
+---------------------------------------+--------------------------------+---------------+-------------+------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Elapsed Time ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 301 MB ; 00:00:06 ;
|
||||
; Fitter ; 00:00:05 ; 1.0 ; 367 MB ; 00:00:05 ;
|
||||
; Total ; 00:00:11 ; -- ; -- ; 00:00:11 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------+
|
||||
; Flow OS Summary ;
|
||||
+----------------------+------------------+------------+------------+----------------+
|
||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||
+----------------------+------------------+------------+------------+----------------+
|
||||
; Analysis & Synthesis ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ;
|
||||
; Fitter ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ;
|
||||
+----------------------+------------------+------------+------------+----------------+
|
||||
|
||||
|
||||
------------
|
||||
; Flow Log ;
|
||||
------------
|
||||
quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
||||
quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="18569980bfd13b712cb1"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
|
||||
</file_info>
|
||||
</sld_project_info>
|
||||
|
|
@ -0,0 +1,353 @@
|
|||
Analysis & Synthesis report for GR8RAM
|
||||
Fri Mar 19 02:55:50 2021
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Analysis & Synthesis Summary
|
||||
3. Analysis & Synthesis Settings
|
||||
4. Parallel Compilation
|
||||
5. Analysis & Synthesis Source Files Read
|
||||
6. Analysis & Synthesis Resource Usage Summary
|
||||
7. Analysis & Synthesis Resource Utilization by Entity
|
||||
8. Analysis & Synthesis IP Cores Summary
|
||||
9. Registers Removed During Synthesis
|
||||
10. General Register Statistics
|
||||
11. Inverted Register Statistics
|
||||
12. Multiplexer Restructuring Statistics (Restructuring Performed)
|
||||
13. Port Connectivity Checks: "UFM:UFM_inst"
|
||||
14. Analysis & Synthesis Messages
|
||||
15. Analysis & Synthesis Suppressed Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+-------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Fri Mar 19 02:55:50 2021 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 343 ;
|
||||
; Total pins ; 73 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+-------------------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Settings ;
|
||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
||||
; Option ; Setting ; Default Value ;
|
||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
||||
; Device ; EPM240T100C5 ; ;
|
||||
; Top-level entity name ; GR8RAM ; GR8RAM ;
|
||||
; Family name ; MAX II ; Cyclone IV GX ;
|
||||
; Optimization Technique ; Area ; Balanced ;
|
||||
; Use smart compilation ; Off ; Off ;
|
||||
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
||||
; Enable compact report table ; Off ; Off ;
|
||||
; Restructure Multiplexers ; Auto ; Auto ;
|
||||
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
||||
; Preserve fewer node names ; On ; On ;
|
||||
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
|
||||
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
||||
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
||||
; State Machine Processing ; Auto ; Auto ;
|
||||
; Safe State Machine ; Off ; Off ;
|
||||
; Extract Verilog State Machines ; On ; On ;
|
||||
; Extract VHDL State Machines ; On ; On ;
|
||||
; Ignore Verilog initial constructs ; Off ; Off ;
|
||||
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
||||
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
||||
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
||||
; Infer RAMs from Raw Logic ; On ; On ;
|
||||
; Parallel Synthesis ; On ; On ;
|
||||
; NOT Gate Push-Back ; On ; On ;
|
||||
; Power-Up Don't Care ; On ; On ;
|
||||
; Remove Redundant Logic Cells ; Off ; Off ;
|
||||
; Remove Duplicate Registers ; On ; On ;
|
||||
; Ignore CARRY Buffers ; Off ; Off ;
|
||||
; Ignore CASCADE Buffers ; Off ; Off ;
|
||||
; Ignore GLOBAL Buffers ; Off ; Off ;
|
||||
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
||||
; Ignore LCELL Buffers ; Off ; Off ;
|
||||
; Ignore SOFT Buffers ; On ; On ;
|
||||
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
||||
; Carry Chain Length ; 70 ; 70 ;
|
||||
; Auto Carry Chains ; On ; On ;
|
||||
; Auto Open-Drain Pins ; On ; On ;
|
||||
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
|
||||
; Auto Shift Register Replacement ; Auto ; Auto ;
|
||||
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
|
||||
; Auto Clock Enable Replacement ; On ; On ;
|
||||
; Allow Synchronous Control Signals ; On ; On ;
|
||||
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
||||
; Auto Resource Sharing ; Off ; Off ;
|
||||
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
||||
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
||||
; Report Parameter Settings ; On ; On ;
|
||||
; Report Source Assignments ; On ; On ;
|
||||
; Report Connectivity Checks ; On ; On ;
|
||||
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
||||
; Synchronization Register Chain Length ; 2 ; 2 ;
|
||||
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
|
||||
; HDL message level ; Level2 ; Level2 ;
|
||||
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
||||
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
||||
; Clock MUX Protection ; On ; On ;
|
||||
; Block Design Naming ; Auto ; Auto ;
|
||||
; Synthesis Effort ; Auto ; Auto ;
|
||||
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
||||
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
|
||||
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
||||
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
||||
; Synthesis Seed ; 1 ; 1 ;
|
||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+-------------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+-------------+
|
||||
; Number detected on machine ; 2 ;
|
||||
; Maximum allowed ; 2 ;
|
||||
; ; ;
|
||||
; Average used ; 1.00 ;
|
||||
; Maximum used ; 1 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 0.0% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------------+-------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+------------------------------+-------------------------------+---------+
|
||||
; UFM.v ; yes ; User Wizard-Generated File ; Z:/Repos/GR8RAM/cpld/UFM.v ; ;
|
||||
; gr8ram.v ; yes ; Auto-Found Verilog HDL File ; Z:/Repos/GR8RAM/cpld/gr8ram.v ; ;
|
||||
+----------------------------------+-----------------+------------------------------+-------------------------------+---------+
|
||||
|
||||
|
||||
+-----------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Usage Summary ;
|
||||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Total logic elements ; 343 ;
|
||||
; -- Combinational with no register ; 220 ;
|
||||
; -- Register only ; 30 ;
|
||||
; -- Combinational with a register ; 93 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 198 ;
|
||||
; -- 3 input functions ; 43 ;
|
||||
; -- 2 input functions ; 66 ;
|
||||
; -- 1 input functions ; 5 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 306 ;
|
||||
; -- arithmetic mode ; 37 ;
|
||||
; -- qfbk mode ; 0 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 28 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 123 ;
|
||||
; Total logic cells in carry chains ; 41 ;
|
||||
; I/O pins ; 73 ;
|
||||
; UFM blocks ; 1 ;
|
||||
; Maximum fan-out node ; C25M ;
|
||||
; Maximum fan-out ; 123 ;
|
||||
; Total fan-out ; 1357 ;
|
||||
; Average fan-out ; 3.25 ;
|
||||
+---------------------------------------------+-------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
|
||||
; |GR8RAM ; 343 (343) ; 123 ; 1 ; 73 ; 0 ; 220 (220) ; 30 (30) ; 93 (93) ; 41 (41) ; 0 (0) ; |GR8RAM ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ;
|
||||
; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis IP Cores Summary ;
|
||||
+--------+--------------+---------+--------------+--------------+----------------------+----------------------------+
|
||||
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
|
||||
+--------+--------------+---------+--------------+--------------+----------------------+----------------------------+
|
||||
; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |GR8RAM|UFM:UFM_inst ; Z:/Repos/GR8RAM/cpld/UFM.v ;
|
||||
+--------+--------------+---------+--------------+--------------+----------------------+----------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Registers Removed During Synthesis ;
|
||||
+---------------------------------------+----------------------------------------+
|
||||
; Register name ; Reason for Removal ;
|
||||
+---------------------------------------+----------------------------------------+
|
||||
; DRDIn ; Stuck at GND due to stuck port data_in ;
|
||||
; nRESout~reg0 ; Merged with CmdActv ;
|
||||
; RCKE~reg0 ; Stuck at VCC due to stuck port data_in ;
|
||||
; Total Number of Removed Registers = 3 ; ;
|
||||
+---------------------------------------+----------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------+
|
||||
; General Register Statistics ;
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 123 ;
|
||||
; Number of registers using Synchronous Clear ; 24 ;
|
||||
; Number of registers using Synchronous Load ; 4 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 69 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
|
||||
+--------------------------------------------------+
|
||||
; Inverted Register Statistics ;
|
||||
+----------------------------------------+---------+
|
||||
; Inverted Register ; Fan out ;
|
||||
+----------------------------------------+---------+
|
||||
; nRCS~reg0 ; 3 ;
|
||||
; nRAS~reg0 ; 3 ;
|
||||
; nCAS~reg0 ; 3 ;
|
||||
; nSWE~reg0 ; 3 ;
|
||||
; DQML~reg0 ; 1 ;
|
||||
; DQMH~reg0 ; 1 ;
|
||||
; Total number of inverted registers = 6 ; ;
|
||||
+----------------------------------------+---------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|S[3] ;
|
||||
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|Addr[2] ;
|
||||
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|Addr[18] ;
|
||||
; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |GR8RAM|IS[1] ;
|
||||
; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[8] ;
|
||||
; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |GR8RAM|DRShift ;
|
||||
; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[23] ;
|
||||
; 13:1 ; 2 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |GR8RAM|SA[12]~reg0 ;
|
||||
; 17:1 ; 5 bits ; 55 LEs ; 30 LEs ; 25 LEs ; Yes ; |GR8RAM|SA[7]~reg0 ;
|
||||
; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[2]~reg0 ;
|
||||
; 20:1 ; 2 bits ; 26 LEs ; 8 LEs ; 18 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "UFM:UFM_inst" ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; ardin ; Input ; Info ; Stuck at GND ;
|
||||
; oscena ; Input ; Info ; Stuck at VCC ;
|
||||
; busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
; rtpbusy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
; Analysis & Synthesis Messages ;
|
||||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Analysis & Synthesis
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Fri Mar 19 02:55:44 2021
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
||||
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
||||
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
|
||||
Info (12023): Found entity 1: UFM_altufm_none_0ep
|
||||
Info (12023): Found entity 2: UFM
|
||||
Warning (10229): Verilog HDL Expression warning at gr8ram.v(545): truncated literal to match 1 bits
|
||||
Warning (10229): Verilog HDL Expression warning at gr8ram.v(558): truncated literal to match 1 bits
|
||||
Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
|
||||
Info (12023): Found entity 1: GR8RAM
|
||||
Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(275): created implicit net for "UFMB"
|
||||
Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(278): created implicit net for "RTPB"
|
||||
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
||||
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(112): object "REGEN" assigned a value but never read
|
||||
Warning (10858): Verilog HDL warning at gr8ram.v(127): object RDout used but never assigned
|
||||
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(280): object "UFMBr" assigned a value but never read
|
||||
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(282): object "RTPBr" assigned a value but never read
|
||||
Warning (10230): Verilog HDL assignment warning at gr8ram.v(39): truncated value with size 32 to match size of target (18)
|
||||
Warning (10230): Verilog HDL assignment warning at gr8ram.v(147): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at gr8ram.v(154): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at gr8ram.v(160): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at gr8ram.v(426): truncated value with size 32 to match size of target (4)
|
||||
Warning (10230): Verilog HDL assignment warning at gr8ram.v(547): truncated value with size 10 to match size of target (6)
|
||||
Warning (10230): Verilog HDL assignment warning at gr8ram.v(635): truncated value with size 10 to match size of target (6)
|
||||
Warning (10030): Net "RDout" at gr8ram.v(127) has no driver or initial value, using a default initial value '0'
|
||||
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst"
|
||||
Info (12128): Elaborating entity "UFM_altufm_none_0ep" for hierarchy "UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component"
|
||||
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "MOSI" to the node "WRD" into an OR gate
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "RAdir" is stuck at VCC
|
||||
Warning (13410): Pin "RDdir" is stuck at VCC
|
||||
Warning (13410): Pin "RCKE" is stuck at VCC
|
||||
Warning (21074): Design contains 2 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "nIOSEL"
|
||||
Warning (15610): No output dependent on input pin "nIOSTRB"
|
||||
Info (21057): Implemented 417 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 27 input pins
|
||||
Info (21059): Implemented 30 output pins
|
||||
Info (21060): Implemented 16 bidirectional pins
|
||||
Info (21061): Implemented 343 logic cells
|
||||
Info (21070): Implemented 1 User Flash Memory blocks
|
||||
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 26 warnings
|
||||
Info: Peak virtual memory: 301 megabytes
|
||||
Info: Processing ended: Fri Mar 19 02:55:50 2021
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info: Total CPU time (on all processors): 00:00:06
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Analysis & Synthesis Suppressed Messages ;
|
||||
+------------------------------------------+
|
||||
The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword
|
||||
Warning (10273): Verilog HDL warning at gr8ram.v(126): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at gr8ram.v(410): extended using "x" or "z"
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
Analysis & Synthesis Status : Successful - Fri Mar 19 02:55:50 2021
|
||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : GR8RAM
|
||||
Top-level Entity Name : GR8RAM
|
||||
Family : MAX II
|
||||
Total logic elements : 343
|
||||
Total pins : 73
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
Binary file not shown.
|
|
@ -0,0 +1,871 @@
|
|||
TimeQuest Timing Analyzer report for GR8RAM
|
||||
Thu Mar 18 04:40:58 2021
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. TimeQuest Timing Analyzer Summary
|
||||
3. Parallel Compilation
|
||||
4. Clocks
|
||||
5. Fmax Summary
|
||||
6. Setup Summary
|
||||
7. Hold Summary
|
||||
8. Recovery Summary
|
||||
9. Removal Summary
|
||||
10. Minimum Pulse Width Summary
|
||||
11. Setup: 'ARCLK'
|
||||
12. Setup: 'DRCLK'
|
||||
13. Setup: 'C25M'
|
||||
14. Hold: 'DRCLK'
|
||||
15. Hold: 'ARCLK'
|
||||
16. Hold: 'C25M'
|
||||
17. Minimum Pulse Width: 'ARCLK'
|
||||
18. Minimum Pulse Width: 'DRCLK'
|
||||
19. Minimum Pulse Width: 'C25M'
|
||||
20. Setup Times
|
||||
21. Hold Times
|
||||
22. Clock to Output Times
|
||||
23. Minimum Clock to Output Times
|
||||
24. Propagation Delay
|
||||
25. Minimum Propagation Delay
|
||||
26. Output Enable Times
|
||||
27. Minimum Output Enable Times
|
||||
28. Output Disable Times
|
||||
29. Minimum Output Disable Times
|
||||
30. Setup Transfers
|
||||
31. Hold Transfers
|
||||
32. Report TCCS
|
||||
33. Report RSKM
|
||||
34. Unconstrained Paths
|
||||
35. TimeQuest Timing Analyzer Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------+
|
||||
; TimeQuest Timing Analyzer Summary ;
|
||||
+--------------------+-------------------------------------------------------------------+
|
||||
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Device Family ; MAX II ;
|
||||
; Device Name ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Slow Model ;
|
||||
; Rise/Fall Delays ; Unavailable ;
|
||||
+--------------------+-------------------------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+-------------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+-------------+
|
||||
; Number detected on machine ; 2 ;
|
||||
; Maximum allowed ; 2 ;
|
||||
; ; ;
|
||||
; Average used ; 1.00 ;
|
||||
; Maximum used ; 2 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; < 0.1% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Clocks ;
|
||||
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
|
||||
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
|
||||
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
|
||||
; ARCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ;
|
||||
; C25M ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { C25M } ;
|
||||
; DRCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ;
|
||||
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
|
||||
|
||||
|
||||
+--------------------------------------------------+
|
||||
; Fmax Summary ;
|
||||
+------------+-----------------+------------+------+
|
||||
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||||
+------------+-----------------+------------+------+
|
||||
; 10.0 MHz ; 10.0 MHz ; ARCLK ; ;
|
||||
; 10.0 MHz ; 10.0 MHz ; DRCLK ; ;
|
||||
; 105.85 MHz ; 105.85 MHz ; C25M ; ;
|
||||
+------------+-----------------+------------+------+
|
||||
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||||
|
||||
|
||||
+---------------------------------+
|
||||
; Setup Summary ;
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; ARCLK ; -99.000 ; -99.000 ;
|
||||
; DRCLK ; -99.000 ; -99.000 ;
|
||||
; C25M ; -8.447 ; -415.877 ;
|
||||
+-------+---------+---------------+
|
||||
|
||||
|
||||
+---------------------------------+
|
||||
; Hold Summary ;
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; DRCLK ; -16.286 ; -16.286 ;
|
||||
; ARCLK ; -16.276 ; -16.276 ;
|
||||
; C25M ; -1.579 ; -1.579 ;
|
||||
+-------+---------+---------------+
|
||||
|
||||
|
||||
--------------------
|
||||
; Recovery Summary ;
|
||||
--------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-------------------
|
||||
; Removal Summary ;
|
||||
-------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
+---------------------------------+
|
||||
; Minimum Pulse Width Summary ;
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; ARCLK ; -29.500 ; -59.000 ;
|
||||
; DRCLK ; -29.500 ; -59.000 ;
|
||||
; C25M ; -2.289 ; -2.289 ;
|
||||
+-------+---------+---------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'ARCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -99.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ;
|
||||
; -22.724 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C25M ; ARCLK ; 1.000 ; -2.195 ; 1.529 ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'DRCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -99.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ;
|
||||
; -22.714 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; C25M ; DRCLK ; 1.000 ; -2.165 ; 1.549 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'C25M' ;
|
||||
+--------+-----------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+--------+-----------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
; -8.447 ; LS[6] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.114 ;
|
||||
; -8.446 ; LS[6] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.113 ;
|
||||
; -8.308 ; LS[8] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.975 ;
|
||||
; -8.237 ; LS[8] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.904 ;
|
||||
; -8.142 ; LS[8] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.809 ;
|
||||
; -8.013 ; LS[8] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.680 ;
|
||||
; -7.999 ; LS[0] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.666 ;
|
||||
; -7.991 ; LS[8] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.658 ;
|
||||
; -7.988 ; LS[6] ; nBODf0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.655 ;
|
||||
; -7.986 ; LS[8] ; LS[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.653 ;
|
||||
; -7.968 ; LS[12] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.635 ;
|
||||
; -7.952 ; LS[10] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.619 ;
|
||||
; -7.928 ; LS[0] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.595 ;
|
||||
; -7.902 ; LS[5] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.569 ;
|
||||
; -7.901 ; LS[5] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.568 ;
|
||||
; -7.897 ; LS[12] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.564 ;
|
||||
; -7.883 ; LS[3] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.550 ;
|
||||
; -7.881 ; LS[10] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.548 ;
|
||||
; -7.870 ; LS[22] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.537 ;
|
||||
; -7.847 ; LS[6] ; LS[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.514 ;
|
||||
; -7.846 ; LS[6] ; LS[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.513 ;
|
||||
; -7.846 ; LS[6] ; LS[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.513 ;
|
||||
; -7.844 ; LS[6] ; LS[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.511 ;
|
||||
; -7.842 ; LS[6] ; LS[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.509 ;
|
||||
; -7.841 ; LS[22] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.508 ;
|
||||
; -7.838 ; LS[22] ; SDRAMActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.505 ;
|
||||
; -7.835 ; LS[4] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.502 ;
|
||||
; -7.833 ; LS[0] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.500 ;
|
||||
; -7.832 ; LS[7] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.499 ;
|
||||
; -7.829 ; LS[6] ; LS[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.496 ;
|
||||
; -7.825 ; LS[8] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.492 ;
|
||||
; -7.812 ; LS[3] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.479 ;
|
||||
; -7.786 ; LS[10] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.453 ;
|
||||
; -7.778 ; LS[11] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.445 ;
|
||||
; -7.765 ; LS[6] ; nBODf ; C25M ; C25M ; 1.000 ; 0.000 ; 8.432 ;
|
||||
; -7.761 ; LS[7] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.428 ;
|
||||
; -7.755 ; LS[10] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.422 ;
|
||||
; -7.735 ; LS[6] ; LS[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.402 ;
|
||||
; -7.717 ; LS[3] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.384 ;
|
||||
; -7.709 ; LS[0] ; LS[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.376 ;
|
||||
; -7.707 ; LS[11] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.374 ;
|
||||
; -7.704 ; LS[0] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.371 ;
|
||||
; -7.685 ; LS[20] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.352 ;
|
||||
; -7.682 ; LS[0] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.349 ;
|
||||
; -7.677 ; LS[0] ; LS[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.344 ;
|
||||
; -7.673 ; LS[12] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.340 ;
|
||||
; -7.666 ; LS[7] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.333 ;
|
||||
; -7.657 ; LS[10] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.324 ;
|
||||
; -7.656 ; LS[20] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.323 ;
|
||||
; -7.656 ; LS[10] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.323 ;
|
||||
; -7.655 ; LS[5] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.322 ;
|
||||
; -7.653 ; LS[20] ; SDRAMActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.320 ;
|
||||
; -7.653 ; LS[10] ; SDRAMActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.320 ;
|
||||
; -7.651 ; LS[12] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.318 ;
|
||||
; -7.638 ; LS[6] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.305 ;
|
||||
; -7.635 ; LS[10] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.302 ;
|
||||
; -7.630 ; LS[10] ; LS[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.297 ;
|
||||
; -7.620 ; LS[0] ; LS[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.287 ;
|
||||
; -7.611 ; LS[6] ; nFCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.278 ;
|
||||
; -7.600 ; LS[8] ; LS[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.267 ;
|
||||
; -7.593 ; LS[3] ; LS[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.260 ;
|
||||
; -7.589 ; LS[17] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.256 ;
|
||||
; -7.588 ; LS[3] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.255 ;
|
||||
; -7.584 ; LS[5] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.251 ;
|
||||
; -7.584 ; LS[8] ; LS[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.251 ;
|
||||
; -7.566 ; LS[3] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.233 ;
|
||||
; -7.565 ; LS[2] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.232 ;
|
||||
; -7.562 ; LS[2] ; SDRAMActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.229 ;
|
||||
; -7.561 ; LS[3] ; LS[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.228 ;
|
||||
; -7.541 ; LS[2] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.208 ;
|
||||
; -7.540 ; LS[2] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.207 ;
|
||||
; -7.537 ; LS[7] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.204 ;
|
||||
; -7.529 ; LS[19] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.196 ;
|
||||
; -7.528 ; LS[10] ; nFCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.195 ;
|
||||
; -7.517 ; LS[0] ; LS[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.184 ;
|
||||
; -7.516 ; LS[0] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.183 ;
|
||||
; -7.515 ; LS[7] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.182 ;
|
||||
; -7.510 ; LS[7] ; LS[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.177 ;
|
||||
; -7.489 ; LS[5] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.156 ;
|
||||
; -7.485 ; LS[12] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.152 ;
|
||||
; -7.483 ; LS[11] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.150 ;
|
||||
; -7.474 ; LS[11] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.141 ;
|
||||
; -7.469 ; LS[10] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.136 ;
|
||||
; -7.461 ; LS[11] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.128 ;
|
||||
; -7.454 ; LS[13] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.121 ;
|
||||
; -7.451 ; LS[14] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.118 ;
|
||||
; -7.443 ; LS[5] ; nBODf0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.110 ;
|
||||
; -7.436 ; LS[12] ; LS[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.103 ;
|
||||
; -7.401 ; LS[3] ; LS[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.068 ;
|
||||
; -7.400 ; LS[3] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.067 ;
|
||||
; -7.394 ; LS[17] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.061 ;
|
||||
; -7.385 ; LS[11] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.052 ;
|
||||
; -7.383 ; LS[13] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.050 ;
|
||||
; -7.382 ; LS[11] ; SDRAMActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.049 ;
|
||||
; -7.380 ; LS[14] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.047 ;
|
||||
; -7.367 ; LS[16] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.034 ;
|
||||
; -7.365 ; LS[5] ; LS[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.032 ;
|
||||
; -7.363 ; LS[16] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.030 ;
|
||||
; -7.360 ; LS[5] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.027 ;
|
||||
; -7.349 ; LS[7] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.016 ;
|
||||
+--------+-----------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'DRCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -16.286 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; C25M ; DRCLK ; 0.000 ; -2.165 ; 1.549 ;
|
||||
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'ARCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -16.276 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C25M ; ARCLK ; 0.000 ; -2.195 ; 1.529 ;
|
||||
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'C25M' ;
|
||||
+--------+--------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+--------+--------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
; -1.579 ; ARCLK ; ARCLK ; ARCLK ; C25M ; 0.000 ; 3.348 ; 2.366 ;
|
||||
; -1.079 ; ARCLK ; ARCLK ; ARCLK ; C25M ; -0.500 ; 3.348 ; 2.366 ;
|
||||
; 1.374 ; nBODr0 ; nBODr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.595 ;
|
||||
; 1.382 ; nRESr0 ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.603 ;
|
||||
; 1.677 ; SDRAMActv ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 1.898 ;
|
||||
; 1.739 ; S[2] ; S[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.960 ;
|
||||
; 1.879 ; PHI0r0 ; PHI0r1 ; C25M ; C25M ; -0.500 ; 0.000 ; 1.600 ;
|
||||
; 1.907 ; UFMD[14] ; UFMD[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.128 ;
|
||||
; 1.908 ; UFMD[13] ; UFMD[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.129 ;
|
||||
; 2.005 ; S[1] ; S[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.226 ;
|
||||
; 2.014 ; S[1] ; S[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.235 ;
|
||||
; 2.127 ; InitIntr ; InitIntr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ;
|
||||
; 2.160 ; PHI0r2 ; S[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.381 ;
|
||||
; 2.165 ; PHI0r2 ; S[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.386 ;
|
||||
; 2.213 ; nFCS~reg0 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.434 ;
|
||||
; 2.285 ; SetLoaded ; SetLoaded ; C25M ; C25M ; 0.000 ; 0.000 ; 2.506 ;
|
||||
; 2.288 ; DEVSELr0 ; DEVSELr ; C25M ; C25M ; -0.500 ; 0.000 ; 2.009 ;
|
||||
; 2.290 ; SetLoaded ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 2.511 ;
|
||||
; 2.292 ; SetLoaded ; DRShift ; C25M ; C25M ; 0.000 ; 0.000 ; 2.513 ;
|
||||
; 2.299 ; MOSIOE ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.520 ;
|
||||
; 2.328 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.549 ;
|
||||
; 2.380 ; S[0] ; S[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.601 ;
|
||||
; 2.383 ; nWEcur ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.604 ;
|
||||
; 2.383 ; S[0] ; S[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.604 ;
|
||||
; 2.387 ; S[0] ; S[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.608 ;
|
||||
; 2.397 ; S[0] ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.618 ;
|
||||
; 2.523 ; DEVSELr ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 2.744 ;
|
||||
; 2.768 ; PHI0r2 ; nWEcur ; C25M ; C25M ; 0.000 ; 0.000 ; 2.989 ;
|
||||
; 2.770 ; nBODr ; nBODf0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.991 ;
|
||||
; 2.771 ; InitActv ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.992 ;
|
||||
; 2.771 ; InitActv ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.992 ;
|
||||
; 2.829 ; LS[4] ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.050 ;
|
||||
; 2.868 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.089 ;
|
||||
; 2.874 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.095 ;
|
||||
; 2.877 ; nRESout~reg0 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.098 ;
|
||||
; 2.896 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.117 ;
|
||||
; 2.903 ; InitActv ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.124 ;
|
||||
; 2.966 ; RAMSEL ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.187 ;
|
||||
; 3.035 ; RAcur[11] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.256 ;
|
||||
; 3.084 ; InitActv ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 3.305 ;
|
||||
; 3.091 ; nBODf ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 3.312 ;
|
||||
; 3.177 ; MOSIout ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.398 ;
|
||||
; 3.185 ; S[0] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.406 ;
|
||||
; 3.188 ; S[2] ; S[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.409 ;
|
||||
; 3.264 ; nBODf ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.485 ;
|
||||
; 3.266 ; S[2] ; S[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.487 ;
|
||||
; 3.281 ; RAMSEL ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.502 ;
|
||||
; 3.284 ; LS[1] ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.505 ;
|
||||
; 3.285 ; LS[1] ; ARCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.506 ;
|
||||
; 3.301 ; LS[0] ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 3.522 ;
|
||||
; 3.320 ; RAcur[0] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.541 ;
|
||||
; 3.342 ; LS[4] ; DRShift ; C25M ; C25M ; 0.000 ; 0.000 ; 3.563 ;
|
||||
; 3.352 ; LS[2] ; SetLoaded ; C25M ; C25M ; 0.000 ; 0.000 ; 3.573 ;
|
||||
; 3.377 ; LS[22] ; LS[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.598 ;
|
||||
; 3.389 ; InitIntr ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 3.610 ;
|
||||
; 3.392 ; InitIntr ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.613 ;
|
||||
; 3.429 ; nBODf ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 3.650 ;
|
||||
; 3.437 ; nBODf ; InitIntr ; C25M ; C25M ; 0.000 ; 0.000 ; 3.658 ;
|
||||
; 3.521 ; LS[0] ; InitIntr ; C25M ; C25M ; 0.000 ; 0.000 ; 3.742 ;
|
||||
; 3.523 ; S[2] ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.744 ;
|
||||
; 3.530 ; LS[21] ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.751 ;
|
||||
; 3.539 ; LS[20] ; LS[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.760 ;
|
||||
; 3.546 ; RAcur[10] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.767 ;
|
||||
; 3.552 ; S[1] ; S[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.773 ;
|
||||
; 3.559 ; PHI0r2 ; RACr ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ;
|
||||
; 3.559 ; PHI0r2 ; RAcur[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ;
|
||||
; 3.559 ; PHI0r2 ; RAcur[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ;
|
||||
; 3.559 ; PHI0r2 ; RAcur[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ;
|
||||
; 3.559 ; PHI0r2 ; RAcur[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ;
|
||||
; 3.559 ; PHI0r2 ; RAcur[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ;
|
||||
; 3.559 ; PHI0r2 ; RAcur[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ;
|
||||
; 3.559 ; PHI0r2 ; RAcur[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ;
|
||||
; 3.559 ; PHI0r2 ; RAcur[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ;
|
||||
; 3.588 ; SetLoaded ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.809 ;
|
||||
; 3.597 ; PHI0r1 ; S[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.818 ;
|
||||
; 3.602 ; PHI0r1 ; S[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.823 ;
|
||||
; 3.652 ; LS[13] ; LS[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.873 ;
|
||||
; 3.660 ; S[2] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.881 ;
|
||||
; 3.674 ; S[1] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.895 ;
|
||||
; 3.685 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.906 ;
|
||||
; 3.701 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.922 ;
|
||||
; 3.703 ; LS[1] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.924 ;
|
||||
; 3.708 ; S[1] ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.929 ;
|
||||
; 3.798 ; nRESout~reg0 ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 4.019 ;
|
||||
; 3.823 ; LS[4] ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 4.044 ;
|
||||
; 3.825 ; RAcur[8] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 4.046 ;
|
||||
; 3.874 ; S[2] ; nWEcur ; C25M ; C25M ; 0.000 ; 0.000 ; 4.095 ;
|
||||
; 3.925 ; LS[2] ; DRShift ; C25M ; C25M ; 0.000 ; 0.000 ; 4.146 ;
|
||||
; 3.965 ; LS[13] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 4.186 ;
|
||||
; 4.022 ; LS[0] ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 4.243 ;
|
||||
; 4.093 ; RAcur[9] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 4.314 ;
|
||||
; 4.116 ; nRESr ; S[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 4.337 ;
|
||||
; 4.157 ; LS[14] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 4.378 ;
|
||||
; 4.184 ; nRESout~reg0 ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 4.405 ;
|
||||
; 4.184 ; nRESout~reg0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 4.405 ;
|
||||
; 4.205 ; PHI0r1 ; nWEcur ; C25M ; C25M ; 0.000 ; 0.000 ; 4.426 ;
|
||||
; 4.209 ; LS[1] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 4.430 ;
|
||||
; 4.233 ; RACr ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 4.454 ;
|
||||
; 4.233 ; LS[3] ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 4.454 ;
|
||||
; 4.238 ; S[1] ; nWEcur ; C25M ; C25M ; 0.000 ; 0.000 ; 4.459 ;
|
||||
+--------+--------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Minimum Pulse Width: 'ARCLK' ;
|
||||
+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
|
||||
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
||||
+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
|
||||
; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ;
|
||||
; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; ARCLK|regout ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; ARCLK|regout ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_0ep_component|maxii_ufm_block1|arclk ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_0ep_component|maxii_ufm_block1|arclk ;
|
||||
+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Minimum Pulse Width: 'DRCLK' ;
|
||||
+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
|
||||
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
||||
+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
|
||||
; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ;
|
||||
; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; DRCLK|regout ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; DRCLK|regout ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_0ep_component|maxii_ufm_block1|drclk ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_0ep_component|maxii_ufm_block1|drclk ;
|
||||
+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------+
|
||||
; Minimum Pulse Width: 'C25M' ;
|
||||
+--------+--------------+----------------+------------------+-------+------------+-----------+
|
||||
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
||||
+--------+--------------+----------------+------------------+-------+------------+-----------+
|
||||
; -2.289 ; 1.000 ; 3.289 ; Port Rate ; C25M ; Rise ; C25M ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; ARCLK ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; ARCLK ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; ARShift ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; ARShift ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DEVSELr ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DEVSELr ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Fall ; DEVSELr0 ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Fall ; DEVSELr0 ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DRCLK ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DRCLK ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DRShift ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DRShift ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCK~reg0 ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCK~reg0 ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; InitActv ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; InitActv ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; InitIntr ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; InitIntr ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[0] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[0] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[10] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[10] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[11] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[11] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[12] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[12] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[13] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[13] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[14] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[14] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[15] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[15] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[16] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[16] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[17] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[17] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[18] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[18] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[19] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[19] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[1] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[1] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[20] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[20] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[21] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[21] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[22] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[22] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[2] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[2] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[3] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[3] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[4] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[4] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[5] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[5] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[6] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[6] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[7] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[7] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[8] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[8] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[9] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[9] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; MOSIOE ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; MOSIOE ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; MOSIout ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; MOSIout ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Fall ; PHI0r0 ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Fall ; PHI0r0 ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PHI0r1 ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PHI0r1 ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PHI0r2 ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PHI0r2 ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RACr ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RACr ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAMSEL ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAMSEL ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[0] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[0] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[10] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[10] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[11] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[11] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[1] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[1] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[2] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[2] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[3] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[3] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[8] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[8] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[9] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[9] ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; SDOE ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; SDOE ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; SDRAMActv ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; SDRAMActv ;
|
||||
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; S[0] ;
|
||||
+--------+--------------+----------------+------------------+-------+------------+-----------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Setup Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; MISO ; C25M ; 2.942 ; 2.942 ; Rise ; C25M ;
|
||||
; RA[*] ; C25M ; 3.501 ; 3.501 ; Rise ; C25M ;
|
||||
; RA[0] ; C25M ; 2.717 ; 2.717 ; Rise ; C25M ;
|
||||
; RA[1] ; C25M ; 1.838 ; 1.838 ; Rise ; C25M ;
|
||||
; RA[2] ; C25M ; 1.842 ; 1.842 ; Rise ; C25M ;
|
||||
; RA[3] ; C25M ; 2.604 ; 2.604 ; Rise ; C25M ;
|
||||
; RA[8] ; C25M ; 2.435 ; 2.435 ; Rise ; C25M ;
|
||||
; RA[9] ; C25M ; 2.467 ; 2.467 ; Rise ; C25M ;
|
||||
; RA[10] ; C25M ; 2.663 ; 2.663 ; Rise ; C25M ;
|
||||
; RA[11] ; C25M ; 2.353 ; 2.353 ; Rise ; C25M ;
|
||||
; RA[12] ; C25M ; 3.501 ; 3.501 ; Rise ; C25M ;
|
||||
; RA[13] ; C25M ; 3.219 ; 3.219 ; Rise ; C25M ;
|
||||
; RA[14] ; C25M ; 2.101 ; 2.101 ; Rise ; C25M ;
|
||||
; RA[15] ; C25M ; 3.148 ; 3.148 ; Rise ; C25M ;
|
||||
; RD[*] ; C25M ; 3.584 ; 3.584 ; Rise ; C25M ;
|
||||
; RD[0] ; C25M ; 2.094 ; 2.094 ; Rise ; C25M ;
|
||||
; RD[1] ; C25M ; 1.819 ; 1.819 ; Rise ; C25M ;
|
||||
; RD[2] ; C25M ; 2.431 ; 2.431 ; Rise ; C25M ;
|
||||
; RD[3] ; C25M ; 2.028 ; 2.028 ; Rise ; C25M ;
|
||||
; RD[4] ; C25M ; 1.817 ; 1.817 ; Rise ; C25M ;
|
||||
; RD[5] ; C25M ; 2.454 ; 2.454 ; Rise ; C25M ;
|
||||
; RD[6] ; C25M ; 3.584 ; 3.584 ; Rise ; C25M ;
|
||||
; RD[7] ; C25M ; 3.280 ; 3.280 ; Rise ; C25M ;
|
||||
; nBOD ; C25M ; 2.712 ; 2.712 ; Rise ; C25M ;
|
||||
; nRES ; C25M ; 2.707 ; 2.707 ; Rise ; C25M ;
|
||||
; nWE ; C25M ; 2.649 ; 2.649 ; Rise ; C25M ;
|
||||
; PHI0 ; C25M ; 2.420 ; 2.420 ; Fall ; C25M ;
|
||||
; nDEVSEL ; C25M ; 2.916 ; 2.916 ; Fall ; C25M ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------+
|
||||
; Hold Times ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
; MISO ; C25M ; -2.388 ; -2.388 ; Rise ; C25M ;
|
||||
; RA[*] ; C25M ; -1.284 ; -1.284 ; Rise ; C25M ;
|
||||
; RA[0] ; C25M ; -2.163 ; -2.163 ; Rise ; C25M ;
|
||||
; RA[1] ; C25M ; -1.284 ; -1.284 ; Rise ; C25M ;
|
||||
; RA[2] ; C25M ; -1.288 ; -1.288 ; Rise ; C25M ;
|
||||
; RA[3] ; C25M ; -2.050 ; -2.050 ; Rise ; C25M ;
|
||||
; RA[8] ; C25M ; -1.881 ; -1.881 ; Rise ; C25M ;
|
||||
; RA[9] ; C25M ; -1.913 ; -1.913 ; Rise ; C25M ;
|
||||
; RA[10] ; C25M ; -2.109 ; -2.109 ; Rise ; C25M ;
|
||||
; RA[11] ; C25M ; -1.799 ; -1.799 ; Rise ; C25M ;
|
||||
; RA[12] ; C25M ; -2.947 ; -2.947 ; Rise ; C25M ;
|
||||
; RA[13] ; C25M ; -2.665 ; -2.665 ; Rise ; C25M ;
|
||||
; RA[14] ; C25M ; -1.547 ; -1.547 ; Rise ; C25M ;
|
||||
; RA[15] ; C25M ; -2.594 ; -2.594 ; Rise ; C25M ;
|
||||
; RD[*] ; C25M ; -1.263 ; -1.263 ; Rise ; C25M ;
|
||||
; RD[0] ; C25M ; -1.540 ; -1.540 ; Rise ; C25M ;
|
||||
; RD[1] ; C25M ; -1.265 ; -1.265 ; Rise ; C25M ;
|
||||
; RD[2] ; C25M ; -1.877 ; -1.877 ; Rise ; C25M ;
|
||||
; RD[3] ; C25M ; -1.474 ; -1.474 ; Rise ; C25M ;
|
||||
; RD[4] ; C25M ; -1.263 ; -1.263 ; Rise ; C25M ;
|
||||
; RD[5] ; C25M ; -1.900 ; -1.900 ; Rise ; C25M ;
|
||||
; RD[6] ; C25M ; -3.030 ; -3.030 ; Rise ; C25M ;
|
||||
; RD[7] ; C25M ; -2.726 ; -2.726 ; Rise ; C25M ;
|
||||
; nBOD ; C25M ; -2.158 ; -2.158 ; Rise ; C25M ;
|
||||
; nRES ; C25M ; -2.153 ; -2.153 ; Rise ; C25M ;
|
||||
; nWE ; C25M ; -2.095 ; -2.095 ; Rise ; C25M ;
|
||||
; PHI0 ; C25M ; -1.866 ; -1.866 ; Fall ; C25M ;
|
||||
; nDEVSEL ; C25M ; -2.362 ; -2.362 ; Fall ; C25M ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Clock to Output Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; FCK ; C25M ; 8.081 ; 8.081 ; Rise ; C25M ;
|
||||
; MOSI ; C25M ; 8.599 ; 8.599 ; Rise ; C25M ;
|
||||
; SD[*] ; C25M ; 8.802 ; 8.802 ; Rise ; C25M ;
|
||||
; SD[0] ; C25M ; 6.853 ; 6.853 ; Rise ; C25M ;
|
||||
; SD[1] ; C25M ; 6.847 ; 6.847 ; Rise ; C25M ;
|
||||
; SD[2] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ;
|
||||
; SD[3] ; C25M ; 6.867 ; 6.867 ; Rise ; C25M ;
|
||||
; SD[4] ; C25M ; 6.848 ; 6.848 ; Rise ; C25M ;
|
||||
; SD[5] ; C25M ; 6.814 ; 6.814 ; Rise ; C25M ;
|
||||
; SD[6] ; C25M ; 8.802 ; 8.802 ; Rise ; C25M ;
|
||||
; SD[7] ; C25M ; 8.542 ; 8.542 ; Rise ; C25M ;
|
||||
; nFCS ; C25M ; 6.854 ; 6.854 ; Rise ; C25M ;
|
||||
; nRESout ; C25M ; 8.024 ; 8.024 ; Rise ; C25M ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Minimum Clock to Output Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; FCK ; C25M ; 8.081 ; 8.081 ; Rise ; C25M ;
|
||||
; MOSI ; C25M ; 8.599 ; 8.599 ; Rise ; C25M ;
|
||||
; SD[*] ; C25M ; 6.814 ; 6.814 ; Rise ; C25M ;
|
||||
; SD[0] ; C25M ; 6.853 ; 6.853 ; Rise ; C25M ;
|
||||
; SD[1] ; C25M ; 6.847 ; 6.847 ; Rise ; C25M ;
|
||||
; SD[2] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ;
|
||||
; SD[3] ; C25M ; 6.867 ; 6.867 ; Rise ; C25M ;
|
||||
; SD[4] ; C25M ; 6.848 ; 6.848 ; Rise ; C25M ;
|
||||
; SD[5] ; C25M ; 6.814 ; 6.814 ; Rise ; C25M ;
|
||||
; SD[6] ; C25M ; 8.802 ; 8.802 ; Rise ; C25M ;
|
||||
; SD[7] ; C25M ; 8.542 ; 8.542 ; Rise ; C25M ;
|
||||
; nFCS ; C25M ; 6.854 ; 6.854 ; Rise ; C25M ;
|
||||
; nRESout ; C25M ; 8.024 ; 8.024 ; Rise ; C25M ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+----------------------------------------------------+
|
||||
; Propagation Delay ;
|
||||
+------------+-------------+-------+----+----+-------+
|
||||
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
|
||||
+------------+-------------+-------+----+----+-------+
|
||||
; DMAin ; DMAout ; 8.003 ; ; ; 8.003 ;
|
||||
; INTin ; INTout ; 8.012 ; ; ; 8.012 ;
|
||||
+------------+-------------+-------+----+----+-------+
|
||||
|
||||
|
||||
+----------------------------------------------------+
|
||||
; Minimum Propagation Delay ;
|
||||
+------------+-------------+-------+----+----+-------+
|
||||
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
|
||||
+------------+-------------+-------+----+----+-------+
|
||||
; DMAin ; DMAout ; 8.003 ; ; ; 8.003 ;
|
||||
; INTin ; INTout ; 8.012 ; ; ; 8.012 ;
|
||||
+------------+-------------+-------+----+----+-------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
; Output Enable Times ;
|
||||
+-----------+------------+-------+------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+------+------------+-----------------+
|
||||
; MOSI ; C25M ; 6.350 ; ; Rise ; C25M ;
|
||||
; SD[*] ; C25M ; 7.768 ; ; Rise ; C25M ;
|
||||
; SD[0] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[1] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[2] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[3] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[4] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[5] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[6] ; C25M ; 7.768 ; ; Rise ; C25M ;
|
||||
; SD[7] ; C25M ; 7.768 ; ; Rise ; C25M ;
|
||||
+-----------+------------+-------+------+------------+-----------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
; Minimum Output Enable Times ;
|
||||
+-----------+------------+-------+------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+------+------------+-----------------+
|
||||
; MOSI ; C25M ; 6.350 ; ; Rise ; C25M ;
|
||||
; SD[*] ; C25M ; 7.768 ; ; Rise ; C25M ;
|
||||
; SD[0] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[1] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[2] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[3] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[4] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[5] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[6] ; C25M ; 7.768 ; ; Rise ; C25M ;
|
||||
; SD[7] ; C25M ; 7.768 ; ; Rise ; C25M ;
|
||||
+-----------+------------+-------+------+------------+-----------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------+
|
||||
; Output Disable Times ;
|
||||
+-----------+------------+-----------+-----------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-----------+-----------+------------+-----------------+
|
||||
; MOSI ; C25M ; 6.350 ; ; Rise ; C25M ;
|
||||
; SD[*] ; C25M ; 7.768 ; ; Rise ; C25M ;
|
||||
; SD[0] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[1] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[2] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[3] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[4] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[5] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[6] ; C25M ; 7.768 ; ; Rise ; C25M ;
|
||||
; SD[7] ; C25M ; 7.768 ; ; Rise ; C25M ;
|
||||
+-----------+------------+-----------+-----------+------------+-----------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------+
|
||||
; Minimum Output Disable Times ;
|
||||
+-----------+------------+-----------+-----------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-----------+-----------+------------+-----------------+
|
||||
; MOSI ; C25M ; 6.350 ; ; Rise ; C25M ;
|
||||
; SD[*] ; C25M ; 7.768 ; ; Rise ; C25M ;
|
||||
; SD[0] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[1] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[2] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[3] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[4] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[5] ; C25M ; 8.282 ; ; Rise ; C25M ;
|
||||
; SD[6] ; C25M ; 7.768 ; ; Rise ; C25M ;
|
||||
; SD[7] ; C25M ; 7.768 ; ; Rise ; C25M ;
|
||||
+-----------+------------+-----------+-----------+------------+-----------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; Setup Transfers ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C25M ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; ARCLK ; C25M ; 1 ; 1 ; 0 ; 0 ;
|
||||
; C25M ; C25M ; 1370 ; 2 ; 0 ; 0 ;
|
||||
; DRCLK ; C25M ; 3 ; 0 ; 0 ; 0 ;
|
||||
; C25M ; DRCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; Hold Transfers ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C25M ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; ARCLK ; C25M ; 1 ; 1 ; 0 ; 0 ;
|
||||
; C25M ; C25M ; 1370 ; 2 ; 0 ; 0 ;
|
||||
; DRCLK ; C25M ; 3 ; 0 ; 0 ; 0 ;
|
||||
; C25M ; DRCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||
|
||||
|
||||
---------------
|
||||
; Report TCCS ;
|
||||
---------------
|
||||
No dedicated SERDES Transmitter circuitry present in device or used in design
|
||||
|
||||
|
||||
---------------
|
||||
; Report RSKM ;
|
||||
---------------
|
||||
No dedicated SERDES Receiver circuitry present in device or used in design
|
||||
|
||||
|
||||
+------------------------------------------------+
|
||||
; Unconstrained Paths ;
|
||||
+---------------------------------+-------+------+
|
||||
; Property ; Setup ; Hold ;
|
||||
+---------------------------------+-------+------+
|
||||
; Illegal Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Input Ports ; 28 ; 28 ;
|
||||
; Unconstrained Input Port Paths ; 28 ; 28 ;
|
||||
; Unconstrained Output Ports ; 14 ; 14 ;
|
||||
; Unconstrained Output Port Paths ; 23 ; 23 ;
|
||||
+---------------------------------+-------+------+
|
||||
|
||||
|
||||
+------------------------------------+
|
||||
; TimeQuest Timing Analyzer Messages ;
|
||||
+------------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Thu Mar 18 04:40:54 2021
|
||||
Info: Command: quartus_sta GR8RAM -c GR8RAM
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
||||
Info (21077): Low junction temperature is 0 degrees C
|
||||
Info (21077): High junction temperature is 85 degrees C
|
||||
Info (306004): Started post-fitting delay annotation
|
||||
Info (306005): Delay annotation completed successfully
|
||||
Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||||
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||||
Info (332105): Deriving Clocks
|
||||
Info (332105): create_clock -period 1.000 -name DRCLK DRCLK
|
||||
Info (332105): create_clock -period 1.000 -name ARCLK ARCLK
|
||||
Info (332105): create_clock -period 1.000 -name C25M C25M
|
||||
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
||||
Critical Warning (332148): Timing requirements not met
|
||||
Info (332146): Worst-case setup slack is -99.000
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): -99.000 -99.000 ARCLK
|
||||
Info (332119): -99.000 -99.000 DRCLK
|
||||
Info (332119): -8.447 -415.877 C25M
|
||||
Info (332146): Worst-case hold slack is -16.286
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): -16.286 -16.286 DRCLK
|
||||
Info (332119): -16.276 -16.276 ARCLK
|
||||
Info (332119): -1.579 -1.579 C25M
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332146): Worst-case minimum pulse width slack is -29.500
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): -29.500 -59.000 ARCLK
|
||||
Info (332119): -29.500 -59.000 DRCLK
|
||||
Info (332119): -2.289 -2.289 C25M
|
||||
Info (332001): The selected device family is not supported by the report_metastability command.
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
|
||||
Info: Peak virtual memory: 286 megabytes
|
||||
Info: Processing ended: Thu Mar 18 04:40:58 2021
|
||||
Info: Elapsed time: 00:00:04
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
------------------------------------------------------------
|
||||
TimeQuest Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Setup 'ARCLK'
|
||||
Slack : -99.000
|
||||
TNS : -99.000
|
||||
|
||||
Type : Setup 'DRCLK'
|
||||
Slack : -99.000
|
||||
TNS : -99.000
|
||||
|
||||
Type : Setup 'C25M'
|
||||
Slack : -8.447
|
||||
TNS : -415.877
|
||||
|
||||
Type : Hold 'DRCLK'
|
||||
Slack : -16.286
|
||||
TNS : -16.286
|
||||
|
||||
Type : Hold 'ARCLK'
|
||||
Slack : -16.276
|
||||
TNS : -16.276
|
||||
|
||||
Type : Hold 'C25M'
|
||||
Slack : -1.579
|
||||
TNS : -1.579
|
||||
|
||||
Type : Minimum Pulse Width 'ARCLK'
|
||||
Slack : -29.500
|
||||
TNS : -59.000
|
||||
|
||||
Type : Minimum Pulse Width 'DRCLK'
|
||||
Slack : -29.500
|
||||
TNS : -59.000
|
||||
|
||||
Type : Minimum Pulse Width 'C25M'
|
||||
Slack : -2.289
|
||||
TNS : -2.289
|
||||
|
||||
------------------------------------------------------------
|
||||
Loading…
Reference in New Issue