Apple-2-HW/GR8RAM
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Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
EESchema Schematic File Version 4
Removed AVR-JTAG-10 connector footprint
2020-02-09 08:40:57 +00:00
EELAYER 30 0
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
EELAYER END
$Descr USLetter 11000 8500
encoding utf-8
Sheet 2 2
Title "GR8RAM"
New schematic revision
2019-10-13 05:40:49 +00:00
Date "2019-10-13"
Rev "0.9"
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Comp "Garrett's Workshop"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Notes 1500 1100 0 40 ~ 0
S7
Text Notes 6600 850 0 104 ~ 0
Video Access
Text Notes 8600 850 0 100 ~ 0
6502 CPU Access
Text Notes 5700 1100 0 40 ~ 0
S7
Wire Wire Line
5800 1000 5800 1100
Wire Wire Line
5500 1000 5800 1000
Wire Wire Line
5500 1100 5500 1000
Wire Wire Line
5200 1100 5500 1100
Wire Wire Line
6400 1000 6400 1100
Wire Wire Line
6100 1000 6400 1000
Wire Wire Line
6100 1100 6100 1000
Wire Wire Line
5800 1100 6100 1100
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
6100 1400 6150 1300
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
6100 1150 6150 1250
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
10300 1100 10300 1000
Wire Wire Line
10000 1100 10300 1100
Wire Wire Line
9700 1000 10000 1000
Wire Wire Line
9400 1100 9700 1100
Wire Wire Line
9100 1000 9400 1000
Wire Wire Line
9100 1100 9100 1000
Wire Wire Line
8800 1100 9100 1100
Wire Wire Line
8800 1000 8800 1100
Wire Wire Line
8500 1000 8800 1000
Wire Wire Line
8500 1100 8500 1000
Wire Wire Line
8200 1100 8500 1100
Wire Wire Line
8200 1000 8200 1100
Wire Wire Line
7900 1000 8200 1000
Wire Wire Line
7900 1100 7900 1000
Wire Wire Line
7600 1100 7900 1100
Wire Wire Line
7300 1100 7300 1000
Wire Wire Line
7000 1100 7300 1100
Wire Wire Line
7000 1000 7000 1100
Wire Wire Line
6700 1000 7000 1000
Wire Wire Line
6700 1100 6700 1000
Wire Wire Line
6400 1100 6700 1100
Wire Wire Line
7600 1000 7600 1100
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
10300 1550 10350 1450
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
7300 1000 7600 1000
Text Notes 6900 1100 0 40 ~ 0
S1
Text Notes 7500 1100 0 40 ~ 0
S2
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
10300 1400 10350 1300
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
8200 1300 8250 1400
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
10300 1150 10350 1250
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
8200 1250 8250 1150
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Text Notes 8100 1100 0 40 ~ 0
S3
Text Notes 8700 1100 0 40 ~ 0
S4
Text Notes 9300 1100 0 40 ~ 0
S5
Text Notes 9900 1100 0 40 ~ 0
S6
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
6150 1250 8200 1250
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Text Notes 5100 1100 0 40 ~ 0
S6
Text Notes 4500 1100 0 40 ~ 0
S5
Text Notes 3900 1100 0 40 ~ 0
S4
Text Notes 1800 850 0 104 ~ 0
Video Access
Text Notes 3300 1100 0 40 ~ 0
S3
Text Notes 800 1250 2 50 ~ 0
PHI0
Separated CSDBEN
2020-01-26 20:13:37 +00:00
Text Notes 3500 850 0 100 ~ 0
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
6502 CPU Access (long)
Text Notes 800 1400 2 50 ~ 0
PHI1
Text Notes 900 1100 0 40 ~ 0
S6
Text Notes 2700 1100 0 40 ~ 0
S2
Text Notes 2100 1100 0 40 ~ 0
S1
Wire Wire Line
2500 1000 2800 1000
Text Notes 800 1550 2 50 ~ 0
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
~DEVSEL~
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
1000 1100 1300 1100
Wire Wire Line
1000 1000 900 1000
Wire Wire Line
1000 1100 1000 1000
Wire Wire Line
2800 1000 2800 1100
Text Notes 800 1100 2 50 ~ 0
C7M
Wire Wire Line
1300 1100 1300 1000
Wire Wire Line
1300 1000 1600 1000
Wire Wire Line
1600 1000 1600 1100
Wire Wire Line
1600 1100 1900 1100
Wire Wire Line
1900 1100 1900 1000
Wire Wire Line
1900 1000 2200 1000
Wire Wire Line
2200 1000 2200 1100
Wire Wire Line
2200 1100 2500 1100
Wire Wire Line
2500 1100 2500 1000
Wire Wire Line
2800 1100 3100 1100
Wire Wire Line
3100 1100 3100 1000
Wire Wire Line
3100 1000 3400 1000
Wire Wire Line
3400 1000 3400 1100
Wire Wire Line
3400 1100 3700 1100
Wire Wire Line
3700 1100 3700 1000
Wire Wire Line
3700 1000 4000 1000
Wire Wire Line
4000 1000 4000 1100
Wire Wire Line
4000 1100 4300 1100
Wire Wire Line
4300 1100 4300 1000
Wire Wire Line
4300 1000 4600 1000
Wire Wire Line
4600 1100 4900 1100
Wire Wire Line
4900 1100 4900 1000
Wire Wire Line
4900 1000 5200 1000
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
10300 1000 10400 1000
Wire Wire Line
10350 1250 10400 1250
Wire Wire Line
10350 1300 10400 1300
Wire Wire Line
1350 1300 3400 1300
Wire Wire Line
1300 1400 1350 1300
Wire Wire Line
1350 1250 3400 1250
Wire Wire Line
1300 1150 1350 1250
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
900 1150 1300 1150
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
1300 1400 900 1400
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
3400 1300 3450 1400
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
3400 1250 3450 1150
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
3450 1400 6100 1400
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
3450 1150 6100 1150
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
9700 1100 9700 1000
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
1600 1850 1650 1750
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
1600 1750 1650 1850
Text Notes 800 1850 2 50 ~ 0
A
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
6400 1750 6450 1850
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
6400 1850 6450 1750
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
1600 1750 900 1750
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
900 1850 1600 1850
Wire Wire Line
6450 1850 10400 1850
Text Notes 800 2000 2 50 ~ 0
D (wr)
Wire Wire Line
4800 1900 6400 1900
Wire Wire Line
4800 2000 6400 2000
Wire Wire Line
9600 1900 9550 1950
Wire Wire Line
9600 2000 9550 1950
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
9600 1900 10400 1900
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
9600 2000 10400 2000
Text Notes 800 2150 2 50 ~ 0
D (rd)
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
5050 2050 5000 2100
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
5050 2150 5000 2100
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
6400 2050 6450 2100
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
6400 2150 6450 2100
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
5000 2100 1650 2100
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
5050 2050 6400 2050
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
5050 2150 6400 2150
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
1600 2050 1650 2100
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
1600 2150 1650 2100
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
1600 2050 900 2050
Wire Wire Line
1600 2150 900 2150
Wire Wire Line
9850 2050 10400 2050
Wire Wire Line
9850 2150 10400 2150
Wire Wire Line
6450 2100 9800 2100
Wire Wire Line
9850 2150 9800 2100
Wire Wire Line
9850 2050 9800 2100
Wire Wire Line
6450 1950 9550 1950
Wire Wire Line
6400 2000 6450 1950
Wire Wire Line
6400 1900 6450 1950
Wire Wire Line
6150 1300 8200 1300
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
1600 1900 900 1900
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
1600 2000 900 2000
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
1350 1450 1300 1550
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
900 1550 1300 1550
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
3400 1450 3450 1550
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
3850 1450 3900 1550
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
6350 1550 6400 1450
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
1350 1450 3400 1450
Wire Bus Line
7900 950 7900 2200
Wire Bus Line
9100 950 9100 2200
Wire Bus Line
9700 950 9700 2200
Wire Bus Line
7300 950 7300 2200
Wire Bus Line
6700 950 6700 2200
Wire Bus Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
5500 850 5500 2250
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Bus Line
3700 950 3700 2200
Wire Bus Line
4900 950 4900 2200
Wire Bus Line
3100 950 3100 2200
Wire Bus Line
1300 850 1300 2250
Wire Bus Line
1900 950 1900 2200
Wire Bus Line
2500 950 2500 2200
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
3400 1450 3850 1450
Wire Bus Line
3400 850 3400 2250
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
3400 1600 1350 1600
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
1350 1600 1300 1700
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
900 1700 1300 1700
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
8200 1600 8250 1700
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
10350 1600 10400 1600
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
10300 1700 10350 1600
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
5200 1000 5200 1100
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4600 1000 4600 1100
Text Notes 6300 1100 0 40 ~ 0
S7
Text Notes 2550 4900 0 200 ~ 0
Information here may be out of date,\nsuperseded by ./cpld/GR8RAM.v
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
1600 2000 1650 1950
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
1600 1900 1650 1950
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4750 1950 1650 1950
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4800 2000 4750 1950
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4800 1900 4750 1950
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
10000 1000 10000 1100
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
8850 2450 8800 2350
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
3100 2450 3150 2350
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
2550 2450 3100 2450
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
2500 2350 2550 2450
Text Notes 800 2450 2 50 ~ 0
~RAS~ rd
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4900 2450 4950 2350
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4050 2450 4000 2350
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4050 2450 4900 2450
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9700 2450 9750 2350
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
8850 2450 9700 2450
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9750 2350 10400 2350
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
900 2350 2500 2350
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
8250 1150 10300 1150
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9400 1000 9400 1100
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
900 3050 4300 3050
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
900 2950 4300 2950
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
900 3350 1300 3350
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
1000 3400 900 3400
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
1600 3500 1050 3500
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
1000 3400 1050 3500
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
1650 3400 2200 3400
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4650 3350 5500 3350
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
5550 3950 9700 3950
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
5550 3850 9700 3850
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
10300 3950 9750 3950
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9750 3850 10300 3850
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9450 3350 10300 3350
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9750 3050 10400 3050
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9750 2950 10400 2950
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9700 3050 9150 3050
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9150 2950 9700 2950
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9700 2950 9750 3050
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
10350 3250 10400 3250
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
10300 3350 10350 3250
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
10050 3500 10400 3500
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
10000 3400 10050 3500
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9450 3350 9400 3250
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
5250 3500 5800 3500
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7300 3250 7350 3350
Text Notes 800 3500 2 50 ~ 0
~CAS~ wr
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
2250 3500 2800 3500
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
2200 3400 2250 3500
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
2800 3500 2850 3400
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
1600 3500 1650 3400
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7600 3500 7050 3500
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7600 3500 7650 3400
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7000 3400 7050 3500
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
5200 3400 5250 3500
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
5800 3500 5850 3400
Wire Wire Line
4650 3350 4600 3250
Text Notes 800 3350 2 50 ~ 0
~RAS~ wr
Wire Wire Line
1300 3350 1350 3250
Wire Wire Line
7350 3350 7900 3350
Wire Wire Line
7900 3350 7950 3250
Wire Wire Line
2500 3250 2550 3350
Wire Wire Line
2550 3350 3100 3350
Wire Wire Line
3100 3350 3150 3250
Wire Wire Line
5500 3350 5550 3250
Wire Wire Line
10350 3950 10400 3950
Wire Wire Line
10350 3850 10400 3850
Wire Wire Line
1300 3950 900 3950
Wire Wire Line
1300 3850 900 3850
Wire Wire Line
1300 3850 1350 3950
Wire Wire Line
1300 3950 1350 3850
Wire Wire Line
10300 3850 10350 3950
Wire Wire Line
10300 3950 10350 3850
Wire Wire Line
4900 3950 4950 3850
Wire Wire Line
4900 3850 4950 3950
Wire Wire Line
9700 3850 9750 3950
Wire Wire Line
9700 3950 9750 3850
Wire Wire Line
5500 3950 5550 3850
Wire Wire Line
5500 3850 5550 3950
Text Notes 800 3950 2 50 ~ 0
RA wr
Wire Wire Line
9700 3050 9750 2950
Wire Wire Line
4300 3050 4350 2950
Wire Wire Line
4300 2950 4350 3050
Wire Wire Line
9100 2950 9150 3050
Wire Wire Line
9100 3050 9150 2950
Wire Wire Line
4900 3050 4950 2950
Wire Wire Line
4900 2950 4950 3050
Text Notes 800 3050 2 50 ~ 0
RA rd
Wire Wire Line
6100 2600 6150 2500
Wire Wire Line
2250 2600 2800 2600
Wire Wire Line
2200 2500 2250 2600
Wire Wire Line
2800 2600 2850 2500
Wire Wire Line
1300 2600 1350 2500
Wire Wire Line
7600 2600 7050 2600
Wire Wire Line
7600 2600 7650 2500
Wire Wire Line
7000 2500 7050 2600
Wire Wire Line
9400 2500 9450 2600
Wire Wire Line
4600 2500 4650 2600
Wire Wire Line
900 2600 1300 2600
Wire Wire Line
1350 2500 2200 2500
Wire Wire Line
4650 2600 6100 2600
Text Notes 800 2600 2 50 ~ 0
~CAS~ rd
Text Notes 800 2750 2 50 ~ 0
~CAS~r rd
Text Notes 800 2900 2 50 ~ 0
~CAS~f rd
Text Notes 800 3650 2 50 ~ 0
~CAS~r wr
Text Notes 800 3800 2 50 ~ 0
~CAS~f wr
Wire Wire Line
8250 1400 10300 1400
Wire Wire Line
8650 1450 8700 1550
Wire Wire Line
8200 1450 8250 1550
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
8250 1550 10300 1550
Wire Wire Line
10300 1550 10400 1550
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
6150 2500 7000 2500
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
5850 3400 7000 3400
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
5550 3250 7300 3250
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4950 2350 7300 2350
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7300 2350 7350 2450
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7350 2450 7900 2450
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7900 2450 7950 2350
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7650 2500 9400 2500
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7950 2350 8800 2350
CPLD firmware compiles
2019-09-01 02:55:04 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7650 3400 10000 3400
Clarifications and bugfixes, will try again
2019-09-02 05:42:07 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7950 3250 9400 3250
Clarifications and bugfixes, will try again
2019-09-02 05:42:07 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
3150 2350 4000 2350
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
2850 2500 4600 2500
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7300 2750 7350 2650
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
2500 2750 2550 2650
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9700 2650 9750 2750
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4900 2650 4950 2750
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
900 2750 2500 2750
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
5200 2900 5250 2800
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
2250 2900 2800 2900
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
2200 2800 2250 2900
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
2800 2900 2850 2800
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7600 2900 7050 2900
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7600 2900 7650 2800
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7000 2800 7050 2900
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9400 2800 9450 2900
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4600 2800 4650 2900
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
10000 2900 10050 2800
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4650 2900 5200 2900
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
9450 2900 10000 2900
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
7650 2800 9400 2800
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
2850 2800 4600 2800
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
900 2800 2200 2800
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4950 2750 7300 2750
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
2550 2650 4900 2650
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
5250 2800 7000 2800
Wire Wire Line
10050 2800 10400 2800
Wire Wire Line
9750 2750 10400 2750
Wire Wire Line
7350 2650 9700 2650
Wire Wire Line
2250 3800 2800 3800
Wire Wire Line
2200 3700 2250 3800
Wire Wire Line
2800 3800 2850 3700
Wire Wire Line
7600 3800 7050 3800
Wire Wire Line
7600 3800 7650 3700
Wire Wire Line
7000 3700 7050 3800
Wire Wire Line
900 3700 2200 3700
Wire Wire Line
5800 3800 5850 3700
Wire Wire Line
5200 3700 5250 3800
Wire Wire Line
5250 3800 5800 3800
Wire Wire Line
5850 3700 7000 3700
Wire Wire Line
2850 3700 5200 3700
Wire Wire Line
10000 3700 10050 3800
Wire Wire Line
10050 3800 10400 3800
Wire Wire Line
7650 3700 10000 3700
Wire Wire Line
900 3550 10400 3550
Wire Wire Line
2500 3250 1350 3250
Wire Wire Line
3150 3250 4600 3250
Wire Wire Line
2850 3400 5200 3400
Wire Wire Line
9450 2600 10300 2600
Wire Wire Line
10350 2500 10400 2500
Wire Wire Line
10300 2600 10350 2500
Wire Wire Line
4950 3850 5500 3850
Wire Wire Line
5500 3950 4950 3950
Wire Wire Line
1350 3850 4900 3850
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
1350 3950 4900 3950
New schematic revision
2019-10-13 05:40:49 +00:00
Wire Wire Line
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
4900 2950 4350 2950
Wire Wire Line
4350 3050 4900 3050
Wire Wire Line
4950 3050 9100 3050
Wire Wire Line
4950 2950 9100 2950
Wire Wire Line
8600 1450 8650 1550
Wire Wire Line
8550 1450 8600 1550
Wire Wire Line
8500 1450 8550 1550
Wire Wire Line
8450 1450 8500 1550
Wire Wire Line
8400 1450 8450 1550
Wire Wire Line
8300 1450 8350 1550
Wire Wire Line
8350 1450 8400 1550
Wire Wire Line
8250 1450 8300 1550
Wire Wire Line
3800 1450 3850 1550
Wire Wire Line
3750 1450 3800 1550
Wire Wire Line
3700 1450 3750 1550
Wire Wire Line
3650 1450 3700 1550
Wire Wire Line
3600 1450 3650 1550
Wire Wire Line
3550 1450 3600 1550
Wire Wire Line
3500 1450 3550 1550
Wire Wire Line
3450 1450 3500 1550
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
10350 1450 10400 1450
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
10350 1550 10400 1450
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
10350 1700 10400 1600
Text Notes 800 1700 2 50 ~ 0
PHI1d
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
6200 1550 6250 1450
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
6150 1550 6200 1450
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
6250 1550 6300 1450
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
6300 1550 6350 1450
Wire Bus Line
6100 850 6100 1550
Wire Bus Line
6100 1550 6100 2250
Wire Bus Line
8500 950 8500 2200
Wire Bus Line
8200 850 8200 2250
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
3450 1550 6350 1550
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
6150 1450 8650 1450
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
6100 1550 6150 1450
Wire Bus Line
4300 950 4300 2200
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
1650 1850 6400 1850
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
6300 1700 6350 1600
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
6350 1700 6400 1600
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
6400 1700 6450 1600
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
6500 1700 6550 1600
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 19:07:38 +00:00
Wire Wire Line
Separated CSDBEN
2020-01-26 20:13:37 +00:00
6550 1700 6600 1600
Wire Wire Line
6150 1700 6200 1600
Wire Wire Line
6600 1700 6650 1600
Wire Wire Line
6450 1750 10400 1750
Wire Wire Line
1650 1750 6400 1750
Wire Wire Line
3400 1600 3450 1700
Wire Bus Line
10300 1700 10300 2250
Wire Bus Line
10300 850 10300 1700
Wire Wire Line
6200 1700 6250 1600
Wire Wire Line
6250 1700 6300 1600
Wire Wire Line
3450 1700 6600 1700
Wire Wire Line
6450 1700 6500 1600
Wire Wire Line
6200 1600 8200 1600
Wire Wire Line
8250 1700 10400 1700
Submitted to JLCPCB
2019-07-30 21:11:31 +00:00
$EndSCHEMATC
Reference in New Issue Copy Permalink