Apple-2-HW
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GR8RAM
mirror of https://github.com/garrettsworkshop/GR8RAM.git
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This commit is contained in:
Zane Kaminski 2021-02-17 19:29:24 -05:00
parent e2a3901004
commit 0a649d68ac
26 changed files with 151558 additions and 153636 deletions
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3429
Docs.sch
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51
Documentation/Memory Map
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@ -1 +1,50 @@
Recovery
GR8RAM/LibraryCard Slinky memory map
-----------------------------
1 FF FFFF | |
. .. .... | LibCrd Sect. Cache (8 MB) |
1 80 0000 | |
-----------------------------
1 7F FFFF | |
. .. .... | reserved (6 MB) |
1 20 0000 | |
-----------------------------
1 1F FFFF | |
. .. .... | LibCrd registers (1 MB) |
1 10 0000 | |
-----------------------------
1 0F FFFF | |
. .. .... | 256x IOSTRB area (512 kB) |
1 08 0000 | |
-----------------------------
1 07 FFFF | |
. .. .... | 256x IOSEL area (512 kB) |
1 00 0000 | |
-----------------------------
0 FF 0000 | |
. .. .... | RAMFactor Memory (16 MB) |
0 00 0000 | |
-----------------------------
Library Card register space
-----------------------------
1 7F FFFF | |
. .. .... | reserved (768 kB) |
1 74 0000 | |
-----------------------------
1 73 FFFF | |
. .. .... | Response B (64 kB) |
1 73 0000 | |
-----------------------------
1 72 FFFF | |
. .. .... | Command B (64 kB) |
1 72 0000 | |
-----------------------------
1 71 FFFF | |
. .. .... | Response A (64 kB) |
1 71 0000 | |
-----------------------------
1 70 FFFF | |
. .. .... | Command A (64 kB) |
1 70 0000 | |
-----------------------------

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Documentation/Placement.pdf Normal file
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155
GR8RAM-cache.lib
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@ -246,28 +246,6 @@ X A 2 100 0 70 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_D_Small_ALT
#
DEF Device_D_Small_ALT D 0 10 N N 1 F N
F0 "D" -50 80 50 H V L CNN
F1 "Device_D_Small_ALT" -150 -80 50 H V L CNN
F2 "" 0 0 50 V I C CNN
F3 "" 0 0 50 V I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 0 -30 -40 -30 40 N
P 2 0 1 0 -30 0 30 0 N
P 4 0 1 0 30 -40 -30 0 30 40 30 -40 F
X K 1 -100 0 70 R 50 50 1 1 P
X A 2 100 0 70 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_D_Zener_Small_ALT
#
DEF Device_D_Zener_Small_ALT D 0 10 N N 1 F N
@ -384,42 +362,16 @@ X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GW_Logic_74125
# GW_Logic_741G125GW
#
DEF GW_Logic_74125 U 0 40 Y Y 1 F N
F0 "U" 0 450 50 H V C CNN
F1 "GW_Logic_74125" 0 -450 50 H V C CNN
F2 "stdpads:TSSOP-14_4.4x5mm_P0.65mm" 0 -500 50 H I C TNN
F3 "" 0 -50 60 H I C CNN
DRAW
S -200 400 200 -400 0 1 10 f
X 1~OE~ 1 -400 300 200 R 50 50 1 1 I
X 3~OE~ 10 400 -100 200 L 50 50 1 1 I
X 4Y 11 400 0 200 L 50 50 1 1 T
X 4A 12 400 100 200 L 50 50 1 1 I
X 4~OE~ 13 400 200 200 L 50 50 1 1 I
X Vcc 14 400 300 200 L 50 50 1 1 W
X 1A 2 -400 200 200 R 50 50 1 1 I
X 1Y 3 -400 100 200 R 50 50 1 1 T
X 2~OE~ 4 -400 0 200 R 50 50 1 1 I
X 2A 5 -400 -100 200 R 50 50 1 1 I
X 2Y 6 -400 -200 200 R 50 50 1 1 T
X GND 7 -400 -300 200 R 50 50 1 1 W
X 3Y 8 400 -300 200 L 50 50 1 1 T
X 3A 9 400 -200 200 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
# GW_Logic_741G04GW
#
DEF GW_Logic_741G04GW U 0 40 Y Y 1 F N
DEF GW_Logic_741G125GW U 0 40 Y Y 1 F N
F0 "U" 0 250 50 H V C CNN
F1 "GW_Logic_741G04GW" 0 -250 50 H V C CNN
F1 "GW_Logic_741G125GW" 0 -250 50 H V C CNN
F2 "stdpads:SOT-353" 0 -300 50 H I C TNN
F3 "" 0 -200 60 H I C CNN
DRAW
S 200 -200 -200 200 0 1 10 f
X NC 1 -350 100 150 R 50 50 1 1 N
X ~OE~ 1 -400 100 200 R 50 50 1 1 I
X A 2 -400 0 200 R 50 50 1 1 I
X GND 3 -400 -100 200 R 50 50 1 1 W
X Y 4 400 -100 200 L 50 50 1 1 O
@ -477,10 +429,10 @@ ENDDEF
#
# GW_PLD_EPM240T100
#
DEF GW_PLD_EPM240T100 U 0 40 Y Y 1 L N
DEF GW_PLD_EPM240T100 U 0 40 Y Y 1 F N
F0 "U" 0 50 50 H V C CNN
F1 "GW_PLD_EPM240T100" 0 -50 50 H V C CNN
F2 "Package_QFP:LQFP-100_14x14mm_P0.5mm" 0 -100 20 H I C CNN
F2 "stdpads:TQFP-100_14x14mm_P0.5mm" 0 -100 20 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
*QFP*P0.5mm*
@ -605,66 +557,6 @@ X Vin 3 -450 100 200 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_RAM_Flash-4Mx16-TSOP1-48
#
DEF GW_RAM_Flash-4Mx16-TSOP1-48 U 0 20 Y Y 1 F N
F0 "U" 0 1050 50 H V C CNN
F1 "GW_RAM_Flash-4Mx16-TSOP1-48" 0 0 50 V V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -300 1000 300 -1700 0 1 10 f
X GND 27 -500 -1600 200 R 50 50 0 0 W
X VCC 37 -500 900 200 R 50 50 0 0 W
X A15 1 -500 -800 200 R 50 50 1 1 I
X A20 10 -500 -1300 200 R 50 50 1 1 I
X ~WE~ 11 500 -1500 200 L 50 50 1 1 I L
X ~RESET~ 12 500 -800 200 L 50 50 1 1 I L
X A21 13 -500 -1400 200 R 50 50 1 1 I
X ~WP~ 14 500 -1100 200 L 50 50 1 1 I L
X ~BY~ 15 500 -1200 200 L 50 50 1 1 I L
X A18 16 -500 -1100 200 R 50 50 1 1 I
X A17 17 -500 -1000 200 R 50 50 1 1 I
X A7 18 -500 0 200 R 50 50 1 1 I
X A6 19 -500 100 200 R 50 50 1 1 I
X A14 2 -500 -700 200 R 50 50 1 1 I
X A5 20 -500 200 200 R 50 50 1 1 I
X A4 21 -500 300 200 R 50 50 1 1 I
X A3 22 -500 400 200 R 50 50 1 1 I
X A2 23 -500 500 200 R 50 50 1 1 I
X A1 24 -500 600 200 R 50 50 1 1 I
X A0 25 -500 700 200 R 50 50 1 1 I
X ~CS~ 26 500 -1400 200 L 50 50 1 1 I L
X ~OE~ 28 500 -1600 200 L 50 50 1 1 I L
X D0 29 500 900 200 L 50 50 1 1 B
X A13 3 -500 -600 200 R 50 50 1 1 I
X D8 30 500 100 200 L 50 50 1 1 B
X D1 31 500 800 200 L 50 50 1 1 B
X D9 32 500 0 200 L 50 50 1 1 B
X D2 33 500 700 200 L 50 50 1 1 B
X D10 34 500 -100 200 L 50 50 1 1 B
X D3 35 500 600 200 L 50 50 1 1 B
X D11 36 500 -200 200 L 50 50 1 1 B
X D4 38 500 500 200 L 50 50 1 1 B
X D12 39 500 -300 200 L 50 50 1 1 B
X A12 4 -500 -500 200 R 50 50 1 1 I
X D5 40 500 400 200 L 50 50 1 1 B
X D13 41 500 -400 200 L 50 50 1 1 B
X D6 42 500 300 200 L 50 50 1 1 B
X D14 43 500 -500 200 L 50 50 1 1 B
X D7 44 500 200 200 L 50 50 1 1 B
X D15/A22 45 500 -600 200 L 50 50 1 1 B
X GND 46 -500 -1600 200 R 50 50 1 1 W
X ~BYTE~ 47 500 -900 200 L 50 50 1 1 I L
X A16 48 -500 -900 200 R 50 50 1 1 I
X A11 5 -500 -400 200 R 50 50 1 1 I
X A10 6 -500 -300 200 R 50 50 1 1 I
X A9 7 -500 -200 200 R 50 50 1 1 I
X A8 8 -500 -100 200 R 50 50 1 1 I
X A19 9 -500 -1200 200 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# GW_RAM_SDRAM-16Mx16-TSOP2-54
#
DEF GW_RAM_SDRAM-16Mx16-TSOP2-54 U 0 40 Y Y 1 F N
@ -730,6 +622,26 @@ X VDDQ 9 -500 900 200 R 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# GW_RAM_SPIFlash-SO-8
#
DEF GW_RAM_SPIFlash-SO-8 U 0 40 Y Y 1 F N
F0 "U" 0 350 50 H V C CNN
F1 "GW_RAM_SPIFlash-SO-8" 0 -250 50 H V C CNN
F2 "stdpads:Hybrid_SPIFlash_SOIC-8_SOIC-16" 0 -300 50 H I C TNN
F3 "" 0 0 50 H I C TNN
DRAW
S -350 300 350 -200 0 1 10 f
X ~CS~ 1 -550 200 200 R 50 50 1 1 I
X DO/IO1 2 -550 100 200 R 50 50 1 1 B
X ~WP~/IO2 3 -550 0 200 R 50 50 1 1 B
X GND 4 -550 -100 200 R 50 50 1 1 W
X DI/IO0 5 550 -100 200 L 50 50 1 1 B
X CLK 6 550 0 200 L 50 50 1 1 I
X ~HLD~/IO3 7 550 100 200 L 50 50 1 1 B
X Vcc 8 550 200 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# Mechanical_Fiducial
#
DEF Mechanical_Fiducial FID 0 20 Y Y 1 F N
@ -745,6 +657,21 @@ C 0 0 50 0 1 20 f
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole
#
DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
F0 "H" 0 200 50 H V C CNN
F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*
$ENDFPLIST
DRAW
C 0 0 50 0 1 50 N
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole_Pad
#
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N

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GR8RAM.kicad_pcb
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22
GR8RAM.pro
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@ -1,4 +1,4 @@
update=Tuesday, September 29, 2020 at 09:10:17 PM
update=Wednesday, January 06, 2021 at 01:09:33 AM
version=1
last_client=kicad
[general]
@ -12,16 +12,6 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
@ -267,3 +257,13 @@ uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

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GR8RAM.sch
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885
cpld/GR8RAM.v
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@ -1,599 +1,374 @@
module GR8RAM(C25M, PHI1, nIOSEL, nDEVSEL, nIOSTRB,
RA, RB6, nRWE, nROE, nAOE, Adir, nRCS,
RD, nDOE, Ddir,
SBA, SA, nSCS, nRAS, nCAS, nSWE, DQML, DQMH, SCKE, SD,
nRST, nPreBOD,
module GR8RAM(C25M, PHI0, nPBOD, nBOD, nRES,
nIOSEL, nDEVSEL, nIOSTRB,
RA, nWEin, nWEout, Adir,
RD, Ddir,
DMAin, DMAout, INTin, INTout,
nIRQout, nINHout, nDMAout, nNMIout);
nDMA, nRDY, nNMI, nIRQ, nINH, nRESout
SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
nFCS, FCK, MISO, MOSI);
/* Clock inputs */
input C25M, PHI1;
wire PHI0 = ~PHI1;
/* Reset inputs */
input nRST, nPreBOD;
reg nRSTr0;
/* Clock signals */
input C25M, PHI0;
reg PHI0r1, PHI0r2, PHI0r3;
always @(negedge C25M) begin PHI0r1 <= PHI0; end
always @(posedge C25M) begin
nRSTr0 <= nRST;
PHI0r2 <= PHI0r1; PHI0r3 <= PHI0r2;
end
/* Select inputs */
/* Reset/brown-out detect inputs */
input nRES, nPBOD, nBOD;
reg PBODr1, PBODr2, BODr1, BODr2, RESr1, RESr2;
always @(negedge C25M) begin
PBODr1 <= ~nPBOD; BODr1 <= ~nBOD; RESr1 <= ~nRES;
end
always @(posedge C25M) begin
PBODr2 <= PBODr1; BODr2 <= BODr1; RESr2 <= RESr1;
end
/* Apple IO area select signals */
input nIOSEL, nDEVSEL, nIOSTRB;
/* Synchronized select inputs */
reg nDEVSELr0, nDEVSELr1;
reg nIOSELr0;
reg nIOSTRBr0;
always @(posedge C25M) begin
nDEVSELr0 <= nDEVSEL;
nDEVSELr1 <= nDEVSELr0;
nIOSELr0 <= nIOSEL;
nIOSTRBr0 <= nIOSTRB;
end
/* DEVSEL-based state counter */
wire [9:0] DEVSELe = {DEVSELer[9:1], nDEVSELr1 && ~nDEVSELr0 && nRSTr0}
reg [9:1] DEVSELer;
always @(posedge C25M) begin
DEVSELer[9:1] <= DEVSELe[8:0];
end
reg DEVSELr1, DEVSELr2;
always @(negedge C25M) begin DEVSELr1 <= ~nDEVSEL; end
always @(posedge C25M) begin DEVSELr2 <= DEVSELr1; end
/* Flash Control */
output nRCS = ~((~nIOSEL || (~nIOSTRB && IOROMEN)) && CSDBEN && nRST);
output nROE = ~nRWE;
/* 6502/Flash Data Bus */
inout RD = RDOE ? Rdout : 8'bZ;
wire RDOE = ~nDEVSEL && nRST;
wire RDout =
AddrLSelA ? Addr[7:0] :
AddrMSelA ? Addr[15:8] :
AddrHSelA ? Addr[23:16] :
DataSelA ? Addr==0 ? Data0[7:0] : Data[7:0] :
8'h57;
output nDOE = ~((~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN)) && CSDBEN && nRST);
output Ddir = ~nRWE;
/* Data bus / ROM chip select delay */
reg CSDBEN = 0;
always @(posedge C25M, negedge nRST) begin
if (~nRST) CSDBEN <= 1'b0;
else CSDBEN <= ~nDEVSELr0 || ~nIOSELr0 || ~nIOSTRBr0;
end
/* IOROMEN control */
wire IOROMEN = IOROMEN0 ^ IOROMEN1;
reg IOROMEN0 = 0;
reg IOROMEN1 = 0;
always @(negedge nIOSEL, negedge nRST) begin
if (~nRST) IOROMEN0 <= 1'b0; // On reset, set both to 0; 0 ^ 0 == 0
else IOROMEN0 <= ~IOROMEN1; // Enable; X ^ ~X == 1
end
always @(negedge nIOSTRB, negedge nRST) begin
if (~nRST) IOROMEN1 <= 1'b0; // On reset, set both to 0; 0 ^ 0 == 0
else if (RA[10:0] == 11'h7FF) IOROMEN1 <= IOROMEN0; // Disable; X^X==0
end
/* 6502/Flash Address Bus */
input [15:0] RA;
input nRWE;
output nAOE = 0;
output Adir = 1;
reg [3:0] RAr;
reg nRWEr;
always @(posedge nDEVSEL) begin
// Latch RA and nRWE at end of DEVSEL access
RAr[3:0] <= RA[3:0];
nRWEr <= nRWE;
end
/* Register Select Signals */
wire AddrLSelA = RA[3:0] == 4'h0;
wire AddrMSelA = RA[3:0] == 4'h1;
wire AddrHSelA = RA[3:0] == 4'h2;
wire DataSelA = RA[3:0] == 4'h3;
wire DMAAddrLSelA = RA[3:0] == 4'h4;
wire DMAAddrHSelA = RA[3:0] == 4'h5;
wire DMALenLSelA = RA[3:0] == 4'h6;
wire DMALenHSelA = RA[3:0] == 4'h7;
wire MagicSelA = RA[3:0] == 4'h8;
wire CfgSelA = RA[3:0] == 4'h9;
wire RAMMaskSelA = RA[3:0] == 4'hB;
wire BankHSelA = RA[3:0] == 4'hE;
wire BankLSelA = RA[3:0] == 4'hF;
/* SDRAM Address / Flash Bank Bus */
output [1:0] SBA = SAmux ? SBAreg[1:0] :
~nIOSTRB ? {
BankC8[4], // SBA0, Bank4
BankC8[2] // SBA1, Bank2
} : { // IOSEL
1'b1, // SBA0, Bank4
1'b1 // SBA1, Bank2
};
output [12:0] SA = SAmux ? SAreg[12:0] :
~nIOSTRB ? {
SAreg[0], // SA0
BankC8[11], // SA1, Bank11
BankC8[8], // SA2, Bank8
SAreg[3], // SA3
SAreg[4], // SA4
BankC8[7], // SA5, Bank7
SAreg[6], // SA6
BankC8[10], // SA7, Bank10
BankC8[9], // SA8, Bank9
BankC8[1], // SA9, Bank1
BankC8[0], // SA10, Bank0
BankC8[3], // SA11, Bank3
BankC8[5] ^ BankCX[5] // SA12, Bank5
} : { // IOSEL
SAreg[0], // SA0
1'b0, // SA1, Bank11
1'b0, // SA2, Bank8
SAreg[3], // SA3
SAreg[4], // SA4
1'b1, // SA5, Bank7
SAreg[6], // SA6
1'b0, // SA7, Bank10
1'b0, // SA8, Bank9
1'b1, // SA9, Bank1
1'b1, // SA10, Bank0
1'b1, // SA11, Bank3
BankCX[5] // SA12, Bank5
};
output RB6 = ~nIOSTRB ? BankC8[6] ^ BankCX[6] : BankCX[6];
reg SAmux = 1'b0;
reg [1:0] SBAreg;
reg [12:0] SAreg;
/* SDRAM Data Bus */
inout [7:0] SD = SDOE ? WRD : 8'bZ;
reg SDOE = 0;
reg [7:0] WRD = 0;
always @(posedge nDEVSEL) begin
WRD[7:0] <= RD[7:0];
if (nRSTr0 && DataSelA && ~nRWE && Addr==0) Data0[7:0] <= RD[7:0];
end
/* SDRAM Control Bus */
output reg nSCS = 1;
output reg nRAS = 1;
output reg nCAS = 1;
output reg nSWE = 1;
output reg DQML = 1;
output reg DQMH = 1;
output reg SCKE = 1;
/* INT/DMA in/out */
input DMAin;
input INTin;
/* DMA/IRQ daisy chain */
input DMAin, INTin;
output DMAout = DMAin;
output INTout = INTin;
/* IRQ, NMI, DMA, INH outputs (open-drain is external) */
output nIRQ = 1;
output nNMI = 1;
/* Apple open-drain outputs */
output nDMA = 1;
output nRDY = 1;
output nNMI = 1;
output nIRQ = 1;
output nINH = 1;
output nRESout = 0;
/* Refresh/Init Counter */
reg [19:0] Tick;
/* Apple address bus */
input [15:0] RA;
input nWEin;
output RAdir = 1;
output nWEout = 1;
reg [15:0] RAr1; reg nWEr1;
reg [15:0] RAr2; reg nWEr2;
reg [15:0] RAcur; reg nWEcur;
always @(negedge C25M) begin RAr1 <= RA; nWEr1 <= nWE; end
always @(posedge C25M) begin RAr2 <= RAr1; nWEr2 <= nWEr1; end
always @(posedge C25M) begin
Tick <= Tick+1;
if (S==0 && ~PHI0r2) begin
RAcur <= RAr2;
nWEcur <= nWER2;
end
end
reg InitDone = 0;
/* Apple select signals */
wire ROMSpecSEL = RAcur[15:12]==4'hC && RAcur[11:8]!=4'h0;
wire ROMSpecRD = ROMSpecSEL && nWE;
wire RAMSpecSEL = RAcur[15:12]==4'hC && RAcur[11:8]==4'h0 && RAcur[7] && RAcur[7:4]!=4'h8 && RAcur[3:0]==4'h3;
wire RAMSpecRD = RAMSpecSEL && nWE;
wire RAMSpecWR = RAMSpecSEL && ~nWE;
wire SpecRD = ROMSpecRD || RAMSpecRD;
reg RAMRD = 0, RAMWR = 0;
always @(posedge C25M) begin
if (Tick[19:0]==20'hFFFFF) InitDone <= 1'b1;
if (S==5) begin
RAMRD <= RAMSpecRD && DEVSELr2;
RAMWR <= RAMSpecWR && DEVSELr2;
end else if (S==0) begin
RAMRD <= 0;
RAMWR <= 0;
end
end
/* Apple data bus */
inout [7:0] RD = RDdir ? 8'bZ : RDout[7:0];
reg RDdir = 1;
reg [7:0] RDout;
/* SDRAM data bus */
inout [7:0] SD = SDOE ? RD[7:0] : 8'bZ;
reg SDOE = 0;
/* SDRAM address/command */
output reg [1:0] SBA;
output reg [12:0] SA;
output reg RCKE = 1;
output reg nRCS = 1;
output reg nRAS = 1;
output reg nCAS = 1;
output reg nSWE = 1;
output reg DQMH = 1;
output reg DQML = 1;
/* SPI flash */
output reg nFCS = 1;
output reg FCK = 0;
output reg MOSI = MOSIOE ? MOSIout : 1'bZ;
reg MOSIOE = 0;
reg MOSIout;
input MISO;
/* State counters */
reg [24:0] FS = 0;
always @(posedge C25M) begin FS <= FS+1; end
reg [2:0] S = 0;
always @(posedge C25M) begin
if (S==0 && PHI0r2 && ~PHI0r3 && ~RESr2 && ~BODr2) S <= 1;
else if (S==0) S <= 0;
else S <= S+1;
end
reg RefWake = 0;
/* Refresh state */
reg RefReady = 0;
reg RefDone = 0;
always @(posedge C25M) begin RefReady <= S==0; end
always @(posedge C25M) begin
if (FS[6:0]==7'h00) RefDone <= 0;
else (S==0 && RefReady && RCKE && ~(PHI0r2 && ~PHI0r3)) RefDone <= 1;
end
/* User-Accessible Registers */
reg [23:0] Addr = 0;
reg [7:0] Data = 0;
reg [7:0] Data0 = 0;
reg [11:0] BankC8 = 0; // Bits 9:8 are XORed with BankCX
reg [6:5] BankCX = 0; // Bank CX is init value
reg ExtBankEN = 0;
/* Slinky registers */
reg [24:0] Addr;
wire AddrHSpecSEL = RAcur[3:0]==4'h2;
wire AddrMSpecSEL = RAcur[3:0]==4'h1;
wire AddrLSpecSEL = RAcur[3:0]==4'h0;
always @(posedge C25M) begin
if (S==7 && DEVSELr2) begin
if (AddrHSpecSEL || AddrMSpecSEL || AddrLSpecSEL) begin
Addr[24] <= 1'b0;
end
/* Set/Increment Address Register */
always @(posedge C25M, negedge nRST) begin
if (~nRST) begin
Addr <= 0;
end else begin
if (DEVSELe[0] && ~nRWEr) begin // Write address register
if (RAr[3:0]==4'h0) begin // AddrL
Addr[7:0] <= WRD[7:0];
if (Addr[7] & ~WRD[7]) Addr[23:8] <= Addr[23:8]+1;
end else if (RAr[3:0]==4'h1) begin // AddrM
Addr[15:8] <= WRD[7:0];
if (Addr[15] & ~WRD[7]) Addr[23:16] <= Addr[23:16]+1;
end else if (RAr[3:0]==4'h2) begin // AddrH
Addr[23:16] <= WRD[7:0];
end
end else if (DEVSELe[2] && RAr[3:0]==4'h3) begin // R/W data
Addr[23:0] <= Addr[23:0]+1;
if (AddrHSpecSEL) begin
Addr[23:16] <= RD[7:0];
end else if (RAMRD || RAMWR ||
(AddrMSpecSEL && Addr[15] && ~RD[7]) ||
(AddrLSpecSEL && Addr[7] && ~RD[7] && Addr[15:8]==8'hFF)) begin
Addr[23:16] <= Addr[23:16]+1;
end
if (AddrMSpecSEL) begin
Addr[15:8] <= RD[7:0];
end else if (RAMRD || RAMWR ||
(AddrLSpecSEL && Addr[7] && ~RD[7])) begin
Addr[15:8] <= Addr[15:8]+1;
end
if (AddrLSpecSEL) begin
Addr[7:0] <= RD[7:0];
end else if (RAMRD || RAMWR) begin
Addr[7:0] <= Addr[7:0]+1;
end
end
end
/* Set bank */
always @(posedge nDEVSEL, negedge nRST) begin
if (~nRST) begin
BankC8 <= 0;
end else begin
if (~nRWE) begin
if (RAr[3:0]==4'hE && ExtBankEN) begin
BankC8[11:10] <= WRD[3:2];
BankC8[9:8] <= WRD[1:0] ^ BankCX[9:8];
end else if (RAr[3:0]==4'hF) begin
BankC8[7] <= WRD[7] & ExtBankEN;
BankC8[6:0] <= WRD[6:0];
end
end
end
end
/* Latch read data */
always @(posedge C25M) begin
if (DEVSELe[9]) Data[7:0] <= SDD[7:0];
end
/* SDRAM Control */
always @(posedge C25M) begin
if (~InitDone) begin
if (Tick[19:8]==12'hFFF) begin
if (Tick[3:0]==4'h8) begin
if (Tick[7:4]==4'h0) begin
// PC all
SCKE <= 1'b1;
nSCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b0;
DQML <= 1'b1;
DQMH <= 1'b1;
SAreg[10] <= 1'b1; // "all"
end else if (Tick[7:4]==4'h7) begin
// Load mode register
SCKE <= 1'b1;
nSCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nSWE <= 1'b0;
DQML <= 1'b1;
DQMH <= 1'b1;
SAreg[11] <= 1'b0; // Reserved in mode register
end else begin
// AREF
SCKE <= 1'b1;
nSCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nSWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end
end else begin
// NOP
SCKE <= 1'b1;
nSCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end
end else begin
// NOP ckdis
SCKE <= 1'b0;
nSCS <= 1'b1;
if (S==0) begin
if ((PHI0r2 && ~PHI0r3 && ~RESr2 && ~BODr2 && SpecRD) ||
(~RefReady && ~RefDone)) begin
// NOP cken
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end
// Mode register contents
SBAreg[1:0] <= 2'b00; // Reserved
SAreg[11] <= 1'b0; // Reserved
SAreg[9] <= 1'b1; // "1" for single write mode
SAreg[8] <= 1'b0; // Reserved
SAreg[7] <= 1'b0; // "0" for not test mode
SAreg[6:4] <= 3'b010; // "2" for CAS latency 2
SAreg[3] <= 1'b0; // "0" for sequential burst (not used)
SAreg[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
SAmux <= 1'b1;
RefDone <= 1'b0;
RefWake <= 1'b0;
end else if (DEVSELe[0] && RAr[3:0]==4'h3) begin
// NOP
SCKE <= ~nRWEr;
nSCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
SAmux <= 1'b1;
RefWake <= 1'b0;
end else if (DEVSELe[1] && RAr[3:0]==4'h3) begin
// ACT
SCKE <= ~nRWEr;
nSCS <= nRWEr;
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
// Row address
SBAreg[1:0] <= Addr[23:22];
SAreg[12] <= 1'b0;
SAreg[11:0] <= Addr[21:10];
SAmux <= 1'b1;
RefWake <= 1'b0;
end else if (DEVSELe[2] && RAr[3:0]==4'h3) begin
// WR/NOP
SCKE <= ~nRWEr;
nSCS <= nRWEr;
nRAS <= 1'b1;
nCAS <= 1'b0;
nSWE <= 1'b0;
DQML <= Addr[0];
DQMH <= ~Addr[0];
// Column address
SBAreg[1:0] <= Addr[23:22];
SAreg[12:11] <= 2'b00;
SAreg[9] <= 1'b0;
SAreg[8:0] <= Addr[9:1];
// Auto-precharge only if row will increment
SAreg[10] <= Addr[9:0]==10'h3FF;
SAmux <= 1'b1;
RefWake <= 1'b0;
end else if (DEVSELe[3] && RAr[3:0]==4'h3) begin
// NOP
SCKE <= ~nRWEr;
nSCS <= nRWEr;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
SAmux <= 1'b0;
RefWake <= 1'b0;
end else if (DEVSELe[4] && RAr[3:0]==4'h3) begin
// NOP (auto-precharge from previous write)
SCKE <= 1'b1;
nSCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
SAmux <= 1'b0;
RefWake <= 1'b0;
end else if (DEVSELe[5] && RAr[3:0]==4'h3) begin
// ACT only if WR AP just occurred / NOP
SCKE <= 1'b1;
nSCS <= ~nRWEr && ~SAreg[10];
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
// Row address
SBAreg[1:0] <= Addr[23:22];
SAreg[12] <= 1'b0;
SAreg[11:0] <= Addr[21:10];
SAmux <= 1'b1;
RefWake <= 1'b0;
end else if (DEVSELe[6] && RAr[3:0]==4'h3) begin
// RD
SCKE <= 1'b1;
nSCS <= 1'b0;
nRAS <= 1'b1;
nCAS <= 1'b0;
nSWE <= 1'b1;
DQML <= Addr[0];
DQMH <= ~Addr[0];
// Column address
SBAreg[1:0] <= Addr[23:22];
SAreg[12:11] <= 2'b00;
SAreg[10] <= 1'b1; // auto-precharge
SAreg[9] <= 1'b0;
SAreg[8:0] <= Addr[9:1];
SAmux <= 1'b1;
RefWake <= 1'b0;
end else if (DEVSELe[7] && RAr[3:0]==4'h3) begin
// NOP
SCKE <= 1'b1;
nSCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
SAmux <= 1'b0;
RefWake <= 1'b0;
end else begin
if (Tick[5] && ~RefDone) begin
if (~RefWake) begin
// NOP
SCKE <= 1'b1;
nSCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
RefWake <= 1'b1;
end else begin
// AREF
SCKE <= 1'b1;
nSCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nSWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
RefWake <= 1'b0;
RefDone <= 1'b1;
end
DQML <= 1'b1;
end else if (RefReady && ~RefDone && RCKE &&
~(PHI0r2 && ~PHI0r3)) begin
// AREF
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end else begin
// NOP ckdis
SCKE <= 1'b0;
nSCS <= 1'b1;
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (S==4'h1) begin
if (SpecRD) begin
// ACT
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
RefWake <= 1'b0;
if (Tick[5]) RefDone <= 1'b0;
if (RAMSpecRD) begin
RBA[1] <= Addr[24];
RBA[0] <= Addr[23];
RA[12:0] <= Addr[22:10];
end else begin
RBA[1] <= 1'b1;
RBA[0] <= 1'b0;
RA[12:10] <= 3'b000;
RA[9:2] <= Bank[7:0];
RA[1:0] <= RAcur[11:10];
end
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (S==4'h2) begin
if (SpecRD) begin
// RD auto-PC
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b1;
nCAS <= 1'b0;
nSWE <= 1'b1;
SAmux <= 1'b0;
end
end
/* UFM Interface */
reg ARCLK = 0; // UFM address register clock
// UFM address register data input tied to 0
reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
reg DRCLK = 0; // UFM data register clock
reg DRDIn = 0; // UFM data register input
reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
wire DRDOut; // UFM data output
// UFM oscillator always enabled
wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
.arclk (ARCLK),
.ardin (1'b0),
.arshft (ARShift),
.drclk (DRCLK),
.drdin (DRDIn),
.drshft (DRShift),
.erase (UFMErase),
.oscena (1'b1),
.program (UFMProgram),
.busy (UFMBusy),
.drdout (DRDOut),
.osc (UFMOsc),
.rtpbusy (RTPBusy));
reg UFMBr = 0; // UFMBusy registered to sync with C14M
reg RTPBr = 0; // RTPBusy registered to sync with C14M
reg [15:0] Cfg;
reg CfgLoaded = 0;
// Do nothing when Tick15:14==2'h0
// Get ready when Tick15:14==2'h1
// Zero AR
// Load Cfg when Tick15:14==2'h2
// Tick13:6 (256) - first half of UFM looked at
// Tick5:2 (16) - 16 bits loaded from UFM
// 0: set CfgLoaded if DRDout==1, otherwise shift DRDout into Cfg
// 1-14: continue shifting DRDout into Cfg[15:0]
// 15: shift last DRDout bit into Cfg[15:0] and increment AR
// Tick1:0 (4) - 1 bit shifted
// Do nothing when Tick15:14==2'h3
// Set CfgLoaded too
always @(posedge C25M) begin
if (~CfgLoaded) begin
if (Tick[15:14]==2'h0) begin
// Do nothing
ARShift <= 1;
ARCLK <= 0;
DRCLK <= 0;
end else if (Tick[15:14]==2'h1) begin
// Shift zeros into AR during first half
if (~Tick[13]) begin
ARShift <= 1;
ARCLK <= Tick[1];
end else begin
ARShift <= 0;
ARCLK <= 0;
A[12:11] <= 1'b0; // don't care
A[10] <= 1'b1; // auto-precharge
A[9] <= 1'b0; // don't care
if (RAMSpecRD) begin
RBA[1] <= Addr[24];
RBA[0] <= Addr[23];
RA[8:0] <= Addr[9:1];
DQMH <= ~Addr[0];
DQML <= Addr[0];
end else /* ROMSpecRD */ begin
RBA[1] <= 1'b1;
RBA[0] <= 1'b0;
RA[8:0] <= RAcur[9:1];
DQMH <= ~RAcur[0];
DQML <= RAcur[0];
end
// Load default config
Cfg[15:0] <= 16'hFFFF;
// Load indirect into DR at end
if (Tick[13:0]==14'h3FFC ||
Tick[13:0]==14'h3FFD ||
Tick[13:0]==14'h3FFE ||
Tick[13:0]==14'h3FFF || ) begin
DRCLK <= 1;
end else DRCLK <= 0;
end else if (Tick[15:14]==2'h2) begin
// Load 16 bits into Cfg register
if (Tick[5:2]==4'h0 && Tick[1:0]==0 && DRDout) begin
CfgLoaded <= 1;
end else if (Tick[1:0]==0) begin
Cfg[15:0] <= {Cfg[14:1], DRDout};
end
// Increment AR
if (Tick[5:2]==4'hE) begin
ARCLK <= 1;
end else begin
ARCLK <= 0;
end
// Load indirect into DR
if (Tick[5:2]==4'hF) begin
DRCLK <= 1;
end else begin
DRCLK <= 0;
end
ARShift <= 1'b0; // Only incrementing AR now
end else if (Tick[15:14]==2'h3) begin
// Do nothing
ARShift <= 1;
ARCLK <= 0;
DRCLK <= 0;
CfgLoaded <= 1; // in case setting at address 0xFF
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (S==4'h3) begin
if (SpecRD) begin
// NOP cken
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (S==4'h4) begin
if (RAMSpecWR) begin
// NOP cken
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (S==4'h5) begin
if (RAMSpecWR && DEVSELr2) begin
// ACT
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
DRShift <= 0; // Only reading DR during init, not writing UFM
DRDIn <= 0;
end else if (DEVSELe[0] && RAr[3:0]==4'h8) begin
end else begin
// Do nothing
ARShift <= 1;
ARCLK <= 0;
DRCLK <= 0;
DRShift <= 0;
DRDIn <= 0;
BA[1] <= Addr[24];
BA[0] <= Addr[23];
A[12:0] <= Addr[22:10];
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (s==4'h6) begin
if (RAMWR) begin
// WR auto-PC
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b1;
nCAS <= 1'b0;
nSWE <= 1'b0;
BA[1] <= Addr[24];
BA[0] <= Addr[23];
A[12:11] <= 1'b0; // don't care
A[10] <= 1'b1; // auto-precharge
A[9:0] <= Addr[9:0];
DQMH <= ~Addr[10];
DQML <= Addr[10];
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (S==4'h7) begin
if (RAMSpecWR) begin
// NOP cken
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end
end
always @(posedge nDEVSEL, negedge nRST) begin
if (~nRST)
end
endmodule

53
gerber/GR8RAM-BOM.csv
View File

@ -1,37 +1,38 @@
Reference, Quantity, Value, Footprint, Datasheet, LCSC Part
C38 C40 C39 C41 ,4,"10n","stdpads:C_0603","~","C57112"
C8 C10 C11 C1 C7 C2 C3 C4 C36 C37 C5 C6 ,12,"10u","stdpads:C_0805","~","C15850"
C9 C12 C13 C14 C15 C16 C17 C19 C20 C21 C22 C23 C18 C24 C25 C27 C28 C29 C30 C31 C26 C32 C33 C34 C35 ,25,"2u2","stdpads:C_0603","~","C23630"
D1 ,1,"M7","stdpads:D_SMA","~","C95872"
C38 C40 C41 ,3,"22n","stdpads:C_0603","~","C21122"
C39 ,1,"1n","stdpads:C_0603","~","C1588"
C8 C10 C11 C1 C7 C36 C37 C5 C6 C2 C3 C4 ,12,"10u","stdpads:C_0805","~","C15850"
C9 C31 C30 C44 C43 C42 C35 C34 C33 C32 C26 C28 C27 C25 C24 C18 C23 C22 C21 C20 C19 C16 C15 C14 C13 C12 C29 ,27,"2u2","stdpads:C_0603","~","C23630"
D2 ,1,"SMBJ5.0A","stdpads:D_SMB","~","C110528"
D3 ,1,"SS14","stdpads:D_SMA","~","C2480"
F1 ,1,"nSMD035-16V","stdpads:BelFuse_1206","~","C70072"
FB1 ,1,"GZ2012D601TF","stdpads:Murata_BLM21","~","C1017"
FID1 FID2 FID3 FID4 FID5 ,5,"Fiducial","stdpads:Fiducial","~"
D3 D1 ,2,"SS34","stdpads:D_SMA","~","C8678"
F1 ,1,"nSMD050-16V","stdpads:BelFuse_1206","~","C70075"
FB1 ,1,"GZ2012D101TF","stdpads:Murata_BLM21","~","C1015"
FID5 FID4 FID3 FID2 FID1 ,5,"Fiducial","stdpads:Fiducial","~"
H1 ,1," ","stdpads:PasteHole_1.1mm_PTH","~"
H5 H4 H3 H2 H6 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
H6 H2 H3 H4 H5 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
J1 ,1,"AppleIIBus","stdpads:AppleIIBus_Edge","~"
J2 ,1,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
J2 J5 ,2,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
J3 ,1,"DC in","stdpads:BOOMELE_DC-005_DC_5.5-2.0MM","~"
J4 ,1,"JTAG","Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical","~"
Q1 ,1,"AO3401A","stdpads:SOT-23","http://www.aosmd.com/pdfs/datasheet/AO3401A.pdf","C15127"
R1 R2 ,2,"DNP","stdpads:R_0805","~"
R10 R16 R2 R15 R4 ,5,"2k2","stdpads:R_0603","~","C4190"
R11 ,1,"330","stdpads:R_0603","~","C23138"
R12 ,1,"1k","stdpads:R_0805","~","C17513"
R13 ,1,"100","stdpads:R_0805","~","C17408"
R18 ,1,"22k","stdpads:R_0603","~","C31850"
R3 ,1,"3k0","stdpads:R_0603","~","C4211"
R4 R16 ,2,"2k2","stdpads:R_0603","~","C4190"
R7 R6 R11 R10 R17 R14 R15 ,7,"1k","stdpads:R_0603","~","C21190"
R8 R5 ,2,"1M","stdpads:R_0603","~","C22935"
R9 ,1,"3k6","stdpads:R_0603","~","C22980"
R13 ,1,"DNP","stdpads:R_0805","~"
R18 R28 R29 ,3,"22k","stdpads:R_0603","~","C31850"
R20 R21 R23 R24 R25 R26 R1 R22 R27 R31 ,10,"33","stdpads:R_0603","~","C23140"
R3 ,1,"2k7","stdpads:R_0603","~","C13167"
R6 R14 R19 R17 ,4,"1k","stdpads:R_0603","~","C21190"
R7 ,1,"820","stdpads:R_0603","~","C23253"
R8 R5 R30 ,3,"1M","stdpads:R_0603","~","C22935"
R9 ,1,"1k2","stdpads:R_0603","~","C22765"
RN2 RN3 RN1 ,3,"4x33","stdpads:R4_0402","~","C25501"
RN4 ,1,"4x10k","stdpads:R4_0402","~","C25725"
RN4 RN5 ,2,"4x10k","stdpads:R4_0402","~","C25725"
U1 ,1,"EPM240T100C5N","stdpads:TQFP-100_14x14mm_P0.5mm","https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf","C10041"
U13 ,1,"25M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","","C32526"
U14 U12 ,2,"74AHCT125","stdpads:TSSOP-14_4.4x5mm_P0.65mm","","C148198"
U16 ,1,"74LVC1G04GW","stdpads:SOT-353","","C10237"
U13 ,1,"25M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","","C669088"
U16 U11 U12 U15 U17 U18 U19 U20 U14 U22 ,10,"74LVC1G125GW","stdpads:SOT-353","","C12519"
U2 ,1,"W9825","stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm","","C62246"
U3 ,1,"MX29LV640EB","stdpads:TSOP-I-48_18.4x12mm_P0.5mm","http://ww1.microchip.com/downloads/en/DeviceDoc/25022B.pdf","C34469"
U5 U6 U9 U4 ,4,"74AHC245","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","","C5516"
U7 U10 ,2,"LM393","stdpads:SOIC-8_3.9mm","http://www.ti.com/lit/ds/symlink/lm393-n.pdf","C7955"
U8 ,1,"AP2125","stdpads:SOT-23","","C150715"
U3 ,1,"W25Q128JVSIQ","stdpads:SOIC-8_5.3mm","","C97521"
U5 U6 U9 U4 ,4,"74AHC245PW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","","C5516"
U7 U10 ,2,"LM393D","stdpads:SOIC-8_3.9mm","http://www.ti.com/lit/ds/symlink/lm393-n.pdf","C7955"
U8 ,1,"XC6206P332MR","stdpads:SOT-23","","C5446"
Can't render this file because it has a wrong number of fields in line 10.

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gerber/GR8RAM-B_SilkS.gbo
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@ -1,28 +1,35 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)*
G04 #@! TF.CreationDate,2020-10-17T17:20:31-04:00*
G04 #@! TF.ProjectId,GR8RAM,47523852-414d-42e6-9b69-6361645f7063,rev?*
G04 #@! TF.CreationDate,2021-02-17T19:07:14-05:00*
G04 #@! TF.ProjectId,GR8RAM,47523852-414d-42e6-9b69-6361645f7063,0.9*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Legend,Bot*
G04 #@! TF.FilePolarity,Positive*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (5.1.5-0-10_14)) date 2020-10-17 17:20:31*
G04 Created by KiCad (PCBNEW (5.1.5-0-10_14)) date 2021-02-17 19:07:14*
%MOMM*%
%LPD*%
G04 APERTURE LIST*
%ADD10C,0.100000*%
%ADD11R,1.952400X4.552400*%
%ADD12O,1.952400X4.552400*%
%ADD13O,4.552400X1.952400*%
%ADD14R,1.879600X1.879600*%
%ADD15O,1.879600X1.879600*%
%ADD16C,1.143000*%
%ADD10C,0.120000*%
%ADD11C,0.100000*%
%ADD12R,1.879600X1.879600*%
%ADD13O,1.879600X1.879600*%
%ADD14R,1.952400X4.552400*%
%ADD15O,1.952400X4.552400*%
%ADD16O,4.552400X1.952400*%
%ADD17C,2.527300*%
%ADD18C,2.152400*%
%ADD19C,1.448000*%
%ADD18C,0.939800*%
%ADD19C,1.143000*%
%ADD20C,2.152400*%
%ADD21C,1.448000*%
G04 APERTURE END LIST*
%LPC*%
D10*
X61341000Y-117983000D02*
X60706000Y-117983000D01*
X60706000Y-117983000D02*
X60706000Y-118618000D01*
%LPC*%
D11*
G36*
X139700000Y-139446000D02*
G01*
@ -33,15 +40,9 @@ X73660000Y-132080000D01*
X139700000Y-132080000D01*
X139700000Y-139446000D01*
G37*
D11*
X102800000Y-86500000D03*
D12*
X108800000Y-86500000D03*
D13*
X105300000Y-81700000D03*
D14*
X64135000Y-108204000D03*
D15*
D13*
X61595000Y-108204000D03*
X64135000Y-105664000D03*
X61595000Y-105664000D03*
@ -51,7 +52,32 @@ X64135000Y-100584000D03*
X61595000Y-100584000D03*
X64135000Y-98044000D03*
X61595000Y-98044000D03*
D14*
X102800000Y-86500000D03*
D15*
X108800000Y-86500000D03*
D16*
X105300000Y-81700000D03*
D17*
X65786000Y-121793000D03*
X65786000Y-116713000D03*
X60071000Y-116713000D03*
X60071000Y-121793000D03*
D18*
X61341000Y-119888000D03*
X62611000Y-119888000D03*
X63881000Y-119888000D03*
X65151000Y-119888000D03*
X66421000Y-119888000D03*
X66421000Y-118618000D03*
X65151000Y-118618000D03*
X63881000Y-118618000D03*
X62611000Y-118618000D03*
X61341000Y-118618000D03*
D19*
X60071000Y-119253000D03*
X67691000Y-118237000D03*
X67691000Y-120269000D03*
X67691000Y-118237000D03*
X67691000Y-120269000D03*
X60071000Y-119253000D03*
@ -60,7 +86,7 @@ X60071000Y-116713000D03*
X60071000Y-121793000D03*
X65786000Y-121793000D03*
X65786000Y-116713000D03*
D10*
D11*
G36*
X130000179Y-131537818D02*
G01*
@ -1861,11 +1887,11 @@ X136740900Y-131535800D01*
X137579100Y-131535800D01*
X137620179Y-131537818D01*
G37*
D18*
D20*
X140462000Y-129540000D03*
D19*
X48133000Y-98679000D03*
X58293000Y-85979000D03*
D21*
X48133000Y-96139000D03*
X57023000Y-84709000D03*
X143002000Y-127000000D03*
X48133000Y-127000000D03*
X140462000Y-82423000D03*

30
gerber/GR8RAM-Edge_Cuts.gm1
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@ -1,35 +1,35 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)*
G04 #@! TF.CreationDate,2020-10-17T17:20:31-04:00*
G04 #@! TF.ProjectId,GR8RAM,47523852-414d-42e6-9b69-6361645f7063,rev?*
G04 #@! TF.CreationDate,2021-02-17T19:07:14-05:00*
G04 #@! TF.ProjectId,GR8RAM,47523852-414d-42e6-9b69-6361645f7063,0.9*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Profile,NP*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (5.1.5-0-10_14)) date 2020-10-17 17:20:31*
G04 Created by KiCad (PCBNEW (5.1.5-0-10_14)) date 2021-02-17 19:07:14*
%MOMM*%
%LPD*%
G04 APERTURE LIST*
%ADD10C,0.150000*%
G04 APERTURE END LIST*
D10*
X57785000Y-80391000D02*
X46101001Y-92074999D01*
X57785000Y-80391000D02*
G75*
G02X59309000Y-79883000I1524000J-2032000D01*
G01*
X46101001Y-92074999D02*
G75*
G03X45593000Y-93599000I2031999J-1524001D01*
G01*
X48133000Y-132080000D02*
X73914000Y-132080000D01*
X61849000Y-79883000D02*
X59309000Y-79883000D02*
X143002000Y-79883000D01*
X143002000Y-79883000D02*
G75*
G02X145542000Y-82423000I0J-2540000D01*
G01*
X60325000Y-80391000D02*
X46101000Y-94615000D01*
X46101001Y-94614999D02*
G75*
G03X45593000Y-96139000I2031999J-1524001D01*
G01*
X60325000Y-80391000D02*
G75*
G02X61849000Y-79883000I1524000J-2032000D01*
G01*
X138938000Y-139700000D02*
X74422000Y-139700000D01*
X145542000Y-129540000D02*
@ -45,7 +45,7 @@ G01*
X73914000Y-132080000D02*
X73914000Y-139192000D01*
X45593000Y-129540000D02*
X45593000Y-96139000D01*
X45593000Y-93599000D01*
X48133000Y-132080000D02*
G75*
G02X45593000Y-129540000I0J2540000D01*

81303
gerber/GR8RAM-F_Cu.gtl
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gerber/GR8RAM-F_Mask.gts
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gerber/GR8RAM-F_SilkS.gto
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gerber/GR8RAM-In1_Cu.g2
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gerber/GR8RAM-bottom.pos
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@ -1,4 +1,4 @@
### Module positions - created on Saturday, October 17, 2020 at 05:20:25 PM ###
### Module positions - created on Wednesday, February 17, 2021 at 07:07:19 PM ###
### Printed by Pcbnew version kicad (5.1.5-0-10_14)
## Unit = mm, Angle = deg.
## Side : bottom

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gerber/GR8RAM-drl_map.ps
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gerber/GR8RAM-top-pos.csv
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@ -7,7 +7,7 @@ Ref,Val,Package,MidX,MidY,Rot,Side
"C6","10u","C_0805",142.250000,-93.600000,90.000000,top
"C7","10u","C_0805",142.600000,-103.550000,0.000000,top
"C8","10u","C_0805",142.600000,-105.550000,0.000000,top
"C9","2u2","C_0603",120.850000,-119.800000,270.000000,top
"C9","2u2","C_0603",118.700000,-117.450000,270.000000,top
"C10","10u","C_0805",134.850000,-105.550000,90.000000,top
"C11","10u","C_0805",132.350000,-105.550000,90.000000,top
"C12","2u2","C_0603",136.450000,-108.900000,90.000000,top
@ -15,8 +15,7 @@ Ref,Val,Package,MidX,MidY,Rot,Side
"C14","2u2","C_0603",85.800000,-119.800000,270.000000,top
"C15","2u2","C_0603",95.000000,-119.800000,270.000000,top
"C16","2u2","C_0603",104.200000,-119.800000,270.000000,top
"C17","2u2","C_0603",113.400000,-119.800000,270.000000,top
"C18","2u2","C_0603",76.250000,-114.650000,180.000000,top
"C18","2u2","C_0603",82.800000,-103.551000,90.000000,top
"C19","2u2","C_0603",84.350000,-98.000000,90.000000,top
"C20","2u2","C_0603",84.350000,-100.900000,90.000000,top
"C21","2u2","C_0603",90.800000,-111.100000,0.000000,top
@ -36,54 +35,78 @@ Ref,Val,Package,MidX,MidY,Rot,Side
"C35","2u2","C_0603",113.650000,-115.350000,180.000000,top
"C36","10u","C_0805",132.350000,-97.100000,180.000000,top
"C37","10u","C_0805",132.350000,-99.600000,180.000000,top
"C38","10n","C_0603",133.900000,-108.150000,0.000000,top
"C39","10n","C_0603",131.100000,-122.150000,180.000000,top
"C40","10n","C_0603",131.000000,-108.150000,0.000000,top
"C41","10n","C_0603",139.550000,-120.650000,180.000000,top
"D1","M7","D_SMA",142.000000,-99.050000,90.000000,top
"C38","22n","C_0603",131.100000,-122.150000,180.000000,top
"C39","1n","C_0603",133.900000,-108.150000,0.000000,top
"C40","22n","C_0603",131.000000,-108.150000,0.000000,top
"C41","22n","C_0603",139.550000,-120.650000,0.000000,top
"C42","2u2","C_0603",116.000000,-118.550000,270.000000,top
"C43","2u2","C_0603",121.600000,-118.550000,270.000000,top
"C44","2u2","C_0603",127.200000,-118.550000,270.000000,top
"D1","SS14","D_SMA",142.000000,-99.050000,90.000000,top
"D2","SMBJ5.0A","D_SMB",137.400000,-99.050000,270.000000,top
"D3","SS14","D_SMA",142.900000,-118.700000,270.000000,top
"F1","nSMD035-16V","BelFuse_1206",135.450000,-92.450000,0.000000,top
"FB1","GZ2012D601TF","Murata_BLM21",139.550000,-94.450000,0.000000,top
"F1","nSMD050-16V","BelFuse_1206",135.450000,-92.450000,0.000000,top
"FB1","GZ2012D101TF","Murata_BLM21",139.550000,-94.450000,0.000000,top
"FID1","Fiducial","Fiducial",143.002000,-82.423000,270.000000,top
"FID2","Fiducial","Fiducial",48.133000,-96.139000,90.000000,top
"FID3","Fiducial","Fiducial",60.071000,-84.201000,90.000000,top
"FID2","Fiducial","Fiducial",48.133000,-93.599000,90.000000,top
"FID3","Fiducial","Fiducial",58.801000,-82.931000,90.000000,top
"FID4","Fiducial","Fiducial",143.002000,-129.540000,0.000000,top
"FID5","Fiducial","Fiducial",48.133000,-129.540000,0.000000,top
"Q1","AO3401A","SOT-23",142.800000,-109.950000,270.000000,top
"R1","DNP","R_0805",133.096000,-127.889000,90.000000,top
"R2","DNP","R_0805",130.556000,-127.889000,90.000000,top
"R3","3k0","R_0603",133.900000,-122.150000,180.000000,top
"R1","33","R_0603",114.000000,-124.200000,180.000000,top
"R2","2k2","R_0603",128.950000,-113.700000,270.000000,top
"R3","2k7","R_0603",133.900000,-122.150000,180.000000,top
"R4","2k2","R_0603",133.900000,-109.600000,180.000000,top
"R5","1M","R_0603",131.100000,-120.650000,0.000000,top
"R6","1k","R_0603",133.900000,-111.050000,0.000000,top
"R7","1k","R_0603",133.900000,-120.650000,0.000000,top
"R7","820","R_0603",133.900000,-120.650000,0.000000,top
"R8","1M","R_0603",131.000000,-109.600000,180.000000,top
"R9","3k6","R_0603",128.850000,-110.250000,90.000000,top
"R10","1k","R_0603",131.000000,-111.050000,0.000000,top
"R11","1k","R_0603",128.850000,-107.450000,90.000000,top
"R9","1k2","R_0603",128.850000,-110.250000,90.000000,top
"R10","2k2","R_0603",131.000000,-111.050000,0.000000,top
"R11","330","R_0603",128.850000,-107.450000,90.000000,top
"R12","1k","R_0805",136.150000,-94.650000,180.000000,top
"R13","100","R_0805",139.550000,-92.450000,0.000000,top
"R13","DNP","R_0805",139.550000,-92.450000,0.000000,top
"R14","1k","R_0603",136.750000,-122.150000,180.000000,top
"R15","1k","R_0603",138.200000,-108.850000,90.000000,top
"R15","2k2","R_0603",138.200000,-108.850000,90.000000,top
"R16","2k2","R_0603",136.750000,-120.650000,0.000000,top
"R17","1k","R_0603",138.150000,-123.750000,180.000000,top
"R18","22k","R_0603",139.550000,-122.150000,180.000000,top
"R19","1k","R_0603",71.950000,-90.800000,90.000000,top
"R20","33","R_0603",125.200000,-124.200000,180.000000,top
"R21","33","R_0603",128.000000,-124.200000,180.000000,top
"R22","33","R_0603",116.800000,-124.200000,180.000000,top
"R23","33","R_0603",126.700000,-129.750000,180.000000,top
"R24","33","R_0603",122.400000,-124.200000,180.000000,top
"R25","33","R_0603",132.400000,-129.750000,180.000000,top
"R26","33","R_0603",129.550000,-129.750000,180.000000,top
"R27","33","R_0603",119.600000,-124.200000,180.000000,top
"R28","22k","R_0603",70.550000,-110.650000,0.000000,top
"R29","22k","R_0603",70.550000,-112.100000,180.000000,top
"R30","1M","R_0603",139.300000,-111.050000,0.000000,top
"R31","33","R_0603",80.950000,-108.500000,90.000000,top
"RN1","4x33","R4_0402",108.200000,-95.150000,0.000000,top
"RN2","4x33","R4_0402",108.450000,-106.250000,270.000000,top
"RN3","4x33","R4_0402",108.450000,-110.650000,270.000000,top
"RN4","4x10k","R4_0402",128.750000,-124.000000,0.000000,top
"RN4","4x10k","R4_0402",113.500000,-117.200000,0.000000,top
"RN5","4x10k","R4_0402",69.250000,-96.450000,90.000000,top
"U1","EPM240T100C5N","TQFP-100_14x14mm_P0.5mm",94.050000,-101.400000,270.000000,top
"U2","W9825","TSOP-II-54_22.2x10.16mm_P0.8mm",118.650000,-103.050000,180.000000,top
"U3","MX29LV640EB","TSOP-I-48_18.4x12mm_P0.5mm",76.750000,-103.050000,180.000000,top
"U4","74AHC245","TSSOP-20_4.4x6.5mm_P0.65mm",90.225000,-122.000000,0.000000,top
"U5","74AHC245","TSSOP-20_4.4x6.5mm_P0.65mm",108.625000,-122.000000,0.000000,top
"U6","74AHC245","TSSOP-20_4.4x6.5mm_P0.65mm",81.025000,-122.000000,0.000000,top
"U7","LM393","SOIC-8_3.9mm",132.457000,-115.824000,0.000000,top
"U8","AP2125","SOT-23",138.350000,-105.550000,180.000000,top
"U9","74AHC245","TSSOP-20_4.4x6.5mm_P0.65mm",99.425000,-122.000000,0.000000,top
"U10","LM393","SOIC-8_3.9mm",138.172000,-115.824000,0.000000,top
"U12","74AHCT125","TSSOP-14_4.4x5mm_P0.65mm",117.050000,-122.000000,0.000000,top
"U3","W25Q128JVSIQ","SOIC-8_5.3mm",79.121000,-100.711000,180.000000,top
"U4","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",90.225000,-122.000000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",108.625000,-122.000000,0.000000,top
"U6","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",81.025000,-122.000000,0.000000,top
"U7","LM393D","SOIC-8_3.9mm",132.457000,-115.824000,0.000000,top
"U8","XC6206P332MR","SOT-23",138.350000,-105.550000,180.000000,top
"U9","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",99.425000,-122.000000,0.000000,top
"U10","LM393D","SOIC-8_3.9mm",138.172000,-115.824000,0.000000,top
"U11","74LVC1G125GW","SOT-353",125.050000,-121.850000,90.000000,top
"U12","74LVC1G125GW","SOT-353",127.850000,-121.850000,90.000000,top
"U13","25M","Crystal_SMD_3225-4Pin_3.2x2.5mm",107.100000,-102.500000,0.000000,top
"U14","74AHCT125","TSSOP-14_4.4x5mm_P0.65mm",124.500000,-122.000000,0.000000,top
"U16","74LVC1G04GW","SOT-353",108.200000,-98.850000,270.000000,top
"U14","74LVC1G125GW","SOT-353",116.650000,-121.850000,90.000000,top
"U15","74LVC1G125GW","SOT-353",126.550000,-127.450000,90.000000,top
"U16","74LVC1G125GW","SOT-353",108.200000,-98.850000,270.000000,top
"U17","74LVC1G125GW","SOT-353",122.250000,-121.850000,90.000000,top
"U18","74LVC1G125GW","SOT-353",132.250000,-127.450000,90.000000,top
"U19","74LVC1G125GW","SOT-353",129.400000,-127.450000,90.000000,top
"U20","74LVC1G125GW","SOT-353",113.850000,-121.850000,90.000000,top
"U22","74LVC1G125GW","SOT-353",119.450000,-121.850000,90.000000,top

1 Ref Val Package MidX MidY Rot Side
7 C6 10u C_0805 142.250000 -93.600000 90.000000 top
8 C7 10u C_0805 142.600000 -103.550000 0.000000 top
9 C8 10u C_0805 142.600000 -105.550000 0.000000 top
10 C9 2u2 C_0603 120.850000 118.700000 -119.800000 -117.450000 270.000000 top
11 C10 10u C_0805 134.850000 -105.550000 90.000000 top
12 C11 10u C_0805 132.350000 -105.550000 90.000000 top
13 C12 2u2 C_0603 136.450000 -108.900000 90.000000 top
15 C14 2u2 C_0603 85.800000 -119.800000 270.000000 top
16 C15 2u2 C_0603 95.000000 -119.800000 270.000000 top
17 C16 2u2 C_0603 104.200000 -119.800000 270.000000 top
18 C17 C18 2u2 C_0603 113.400000 82.800000 -119.800000 -103.551000 270.000000 90.000000 top
C18 2u2 C_0603 76.250000 -114.650000 180.000000 top
19 C19 2u2 C_0603 84.350000 -98.000000 90.000000 top
20 C20 2u2 C_0603 84.350000 -100.900000 90.000000 top
21 C21 2u2 C_0603 90.800000 -111.100000 0.000000 top
35 C35 2u2 C_0603 113.650000 -115.350000 180.000000 top
36 C36 10u C_0805 132.350000 -97.100000 180.000000 top
37 C37 10u C_0805 132.350000 -99.600000 180.000000 top
38 C38 10n 22n C_0603 133.900000 131.100000 -108.150000 -122.150000 0.000000 180.000000 top
39 C39 10n 1n C_0603 131.100000 133.900000 -122.150000 -108.150000 180.000000 0.000000 top
40 C40 10n 22n C_0603 131.000000 -108.150000 0.000000 top
41 C41 10n 22n C_0603 139.550000 -120.650000 180.000000 0.000000 top
42 D1 C42 M7 2u2 D_SMA C_0603 142.000000 116.000000 -99.050000 -118.550000 90.000000 270.000000 top
43 C43 2u2 C_0603 121.600000 -118.550000 270.000000 top
44 C44 2u2 C_0603 127.200000 -118.550000 270.000000 top
45 D1 SS14 D_SMA 142.000000 -99.050000 90.000000 top
46 D2 SMBJ5.0A D_SMB 137.400000 -99.050000 270.000000 top
47 D3 SS14 D_SMA 142.900000 -118.700000 270.000000 top
48 F1 nSMD035-16V nSMD050-16V BelFuse_1206 135.450000 -92.450000 0.000000 top
49 FB1 GZ2012D601TF GZ2012D101TF Murata_BLM21 139.550000 -94.450000 0.000000 top
50 FID1 Fiducial Fiducial 143.002000 -82.423000 270.000000 top
51 FID2 Fiducial Fiducial 48.133000 -96.139000 -93.599000 90.000000 top
52 FID3 Fiducial Fiducial 60.071000 58.801000 -84.201000 -82.931000 90.000000 top
53 FID4 Fiducial Fiducial 143.002000 -129.540000 0.000000 top
54 FID5 Fiducial Fiducial 48.133000 -129.540000 0.000000 top
55 Q1 AO3401A SOT-23 142.800000 -109.950000 270.000000 top
56 R1 DNP 33 R_0805 R_0603 133.096000 114.000000 -127.889000 -124.200000 90.000000 180.000000 top
57 R2 DNP 2k2 R_0805 R_0603 130.556000 128.950000 -127.889000 -113.700000 90.000000 270.000000 top
58 R3 3k0 2k7 R_0603 133.900000 -122.150000 180.000000 top
59 R4 2k2 R_0603 133.900000 -109.600000 180.000000 top
60 R5 1M R_0603 131.100000 -120.650000 0.000000 top
61 R6 1k R_0603 133.900000 -111.050000 0.000000 top
62 R7 1k 820 R_0603 133.900000 -120.650000 0.000000 top
63 R8 1M R_0603 131.000000 -109.600000 180.000000 top
64 R9 3k6 1k2 R_0603 128.850000 -110.250000 90.000000 top
65 R10 1k 2k2 R_0603 131.000000 -111.050000 0.000000 top
66 R11 1k 330 R_0603 128.850000 -107.450000 90.000000 top
67 R12 1k R_0805 136.150000 -94.650000 180.000000 top
68 R13 100 DNP R_0805 139.550000 -92.450000 0.000000 top
69 R14 1k R_0603 136.750000 -122.150000 180.000000 top
70 R15 1k 2k2 R_0603 138.200000 -108.850000 90.000000 top
71 R16 2k2 R_0603 136.750000 -120.650000 0.000000 top
72 R17 1k R_0603 138.150000 -123.750000 180.000000 top
73 R18 22k R_0603 139.550000 -122.150000 180.000000 top
74 R19 1k R_0603 71.950000 -90.800000 90.000000 top
75 R20 33 R_0603 125.200000 -124.200000 180.000000 top
76 R21 33 R_0603 128.000000 -124.200000 180.000000 top
77 R22 33 R_0603 116.800000 -124.200000 180.000000 top
78 R23 33 R_0603 126.700000 -129.750000 180.000000 top
79 R24 33 R_0603 122.400000 -124.200000 180.000000 top
80 R25 33 R_0603 132.400000 -129.750000 180.000000 top
81 R26 33 R_0603 129.550000 -129.750000 180.000000 top
82 R27 33 R_0603 119.600000 -124.200000 180.000000 top
83 R28 22k R_0603 70.550000 -110.650000 0.000000 top
84 R29 22k R_0603 70.550000 -112.100000 180.000000 top
85 R30 1M R_0603 139.300000 -111.050000 0.000000 top
86 R31 33 R_0603 80.950000 -108.500000 90.000000 top
87 RN1 4x33 R4_0402 108.200000 -95.150000 0.000000 top
88 RN2 4x33 R4_0402 108.450000 -106.250000 270.000000 top
89 RN3 4x33 R4_0402 108.450000 -110.650000 270.000000 top
90 RN4 4x10k R4_0402 128.750000 113.500000 -124.000000 -117.200000 0.000000 top
91 RN5 4x10k R4_0402 69.250000 -96.450000 90.000000 top
92 U1 EPM240T100C5N TQFP-100_14x14mm_P0.5mm 94.050000 -101.400000 270.000000 top
93 U2 W9825 TSOP-II-54_22.2x10.16mm_P0.8mm 118.650000 -103.050000 180.000000 top
94 U3 MX29LV640EB W25Q128JVSIQ TSOP-I-48_18.4x12mm_P0.5mm SOIC-8_5.3mm 76.750000 79.121000 -103.050000 -100.711000 180.000000 top
95 U4 74AHC245 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 90.225000 -122.000000 0.000000 top
96 U5 74AHC245 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 108.625000 -122.000000 0.000000 top
97 U6 74AHC245 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 81.025000 -122.000000 0.000000 top
98 U7 LM393 LM393D SOIC-8_3.9mm 132.457000 -115.824000 0.000000 top
99 U8 AP2125 XC6206P332MR SOT-23 138.350000 -105.550000 180.000000 top
100 U9 74AHC245 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 99.425000 -122.000000 0.000000 top
101 U10 LM393 LM393D SOIC-8_3.9mm 138.172000 -115.824000 0.000000 top
102 U12 U11 74AHCT125 74LVC1G125GW TSSOP-14_4.4x5mm_P0.65mm SOT-353 117.050000 125.050000 -122.000000 -121.850000 0.000000 90.000000 top
103 U12 74LVC1G125GW SOT-353 127.850000 -121.850000 90.000000 top
104 U13 25M Crystal_SMD_3225-4Pin_3.2x2.5mm 107.100000 -102.500000 0.000000 top
105 U14 74AHCT125 74LVC1G125GW TSSOP-14_4.4x5mm_P0.65mm SOT-353 124.500000 116.650000 -122.000000 -121.850000 0.000000 90.000000 top
106 U16 U15 74LVC1G04GW 74LVC1G125GW SOT-353 108.200000 126.550000 -98.850000 -127.450000 270.000000 90.000000 top
107 U16 74LVC1G125GW SOT-353 108.200000 -98.850000 270.000000 top
108 U17 74LVC1G125GW SOT-353 122.250000 -121.850000 90.000000 top
109 U18 74LVC1G125GW SOT-353 132.250000 -127.450000 90.000000 top
110 U19 74LVC1G125GW SOT-353 129.400000 -127.450000 90.000000 top
111 U20 74LVC1G125GW SOT-353 113.850000 -121.850000 90.000000 top
112 U22 74LVC1G125GW SOT-353 119.450000 -121.850000 90.000000 top

91
gerber/GR8RAM-top.pos
View File

@ -1,4 +1,4 @@
### Module positions - created on Saturday, October 17, 2020 at 05:20:25 PM ###
### Module positions - created on Wednesday, February 17, 2021 at 07:07:19 PM ###
### Printed by Pcbnew version kicad (5.1.5-0-10_14)
## Unit = mm, Angle = deg.
## Side : top
@ -11,7 +11,7 @@ C5 10u C_0805 100.0000 -88.3500
C6 10u C_0805 142.2500 -93.6000 90.0000 top
C7 10u C_0805 142.6000 -103.5500 0.0000 top
C8 10u C_0805 142.6000 -105.5500 0.0000 top
C9 2u2 C_0603 120.8500 -119.8000 270.0000 top
C9 2u2 C_0603 118.7000 -117.4500 270.0000 top
C10 10u C_0805 134.8500 -105.5500 90.0000 top
C11 10u C_0805 132.3500 -105.5500 90.0000 top
C12 2u2 C_0603 136.4500 -108.9000 90.0000 top
@ -19,8 +19,7 @@ C13 2u2 C_0603 76.6000 -119.8000
C14 2u2 C_0603 85.8000 -119.8000 270.0000 top
C15 2u2 C_0603 95.0000 -119.8000 270.0000 top
C16 2u2 C_0603 104.2000 -119.8000 270.0000 top
C17 2u2 C_0603 113.4000 -119.8000 270.0000 top
C18 2u2 C_0603 76.2500 -114.6500 180.0000 top
C18 2u2 C_0603 82.8000 -103.5510 90.0000 top
C19 2u2 C_0603 84.3500 -98.0000 90.0000 top
C20 2u2 C_0603 84.3500 -100.9000 90.0000 top
C21 2u2 C_0603 90.8000 -111.1000 0.0000 top
@ -40,55 +39,79 @@ C34 2u2 C_0603 110.8500 -108.7000
C35 2u2 C_0603 113.6500 -115.3500 180.0000 top
C36 10u C_0805 132.3500 -97.1000 180.0000 top
C37 10u C_0805 132.3500 -99.6000 180.0000 top
C38 10n C_0603 133.9000 -108.1500 0.0000 top
C39 10n C_0603 131.1000 -122.1500 180.0000 top
C40 10n C_0603 131.0000 -108.1500 0.0000 top
C41 10n C_0603 139.5500 -120.6500 180.0000 top
D1 M7 D_SMA 142.0000 -99.0500 90.0000 top
C38 22n C_0603 131.1000 -122.1500 180.0000 top
C39 1n C_0603 133.9000 -108.1500 0.0000 top
C40 22n C_0603 131.0000 -108.1500 0.0000 top
C41 22n C_0603 139.5500 -120.6500 0.0000 top
C42 2u2 C_0603 116.0000 -118.5500 270.0000 top
C43 2u2 C_0603 121.6000 -118.5500 270.0000 top
C44 2u2 C_0603 127.2000 -118.5500 270.0000 top
D1 SS14 D_SMA 142.0000 -99.0500 90.0000 top
D2 SMBJ5.0A D_SMB 137.4000 -99.0500 270.0000 top
D3 SS14 D_SMA 142.9000 -118.7000 270.0000 top
F1 nSMD035-16V BelFuse_1206 135.4500 -92.4500 0.0000 top
FB1 GZ2012D601TF Murata_BLM21 139.5500 -94.4500 0.0000 top
F1 nSMD050-16V BelFuse_1206 135.4500 -92.4500 0.0000 top
FB1 GZ2012D101TF Murata_BLM21 139.5500 -94.4500 0.0000 top
FID1 Fiducial Fiducial 143.0020 -82.4230 270.0000 top
FID2 Fiducial Fiducial 48.1330 -96.1390 90.0000 top
FID3 Fiducial Fiducial 60.0710 -84.2010 90.0000 top
FID2 Fiducial Fiducial 48.1330 -93.5990 90.0000 top
FID3 Fiducial Fiducial 58.8010 -82.9310 90.0000 top
FID4 Fiducial Fiducial 143.0020 -129.5400 0.0000 top
FID5 Fiducial Fiducial 48.1330 -129.5400 0.0000 top
Q1 AO3401A SOT-23 142.8000 -109.9500 270.0000 top
R1 DNP R_0805 133.0960 -127.8890 90.0000 top
R2 DNP R_0805 130.5560 -127.8890 90.0000 top
R3 3k0 R_0603 133.9000 -122.1500 180.0000 top
R1 33 R_0603 114.0000 -124.2000 180.0000 top
R2 2k2 R_0603 128.9500 -113.7000 270.0000 top
R3 2k7 R_0603 133.9000 -122.1500 180.0000 top
R4 2k2 R_0603 133.9000 -109.6000 180.0000 top
R5 1M R_0603 131.1000 -120.6500 0.0000 top
R6 1k R_0603 133.9000 -111.0500 0.0000 top
R7 1k R_0603 133.9000 -120.6500 0.0000 top
R7 820 R_0603 133.9000 -120.6500 0.0000 top
R8 1M R_0603 131.0000 -109.6000 180.0000 top
R9 3k6 R_0603 128.8500 -110.2500 90.0000 top
R10 1k R_0603 131.0000 -111.0500 0.0000 top
R11 1k R_0603 128.8500 -107.4500 90.0000 top
R9 1k2 R_0603 128.8500 -110.2500 90.0000 top
R10 2k2 R_0603 131.0000 -111.0500 0.0000 top
R11 330 R_0603 128.8500 -107.4500 90.0000 top
R12 1k R_0805 136.1500 -94.6500 180.0000 top
R13 100 R_0805 139.5500 -92.4500 0.0000 top
R13 DNP R_0805 139.5500 -92.4500 0.0000 top
R14 1k R_0603 136.7500 -122.1500 180.0000 top
R15 1k R_0603 138.2000 -108.8500 90.0000 top
R15 2k2 R_0603 138.2000 -108.8500 90.0000 top
R16 2k2 R_0603 136.7500 -120.6500 0.0000 top
R17 1k R_0603 138.1500 -123.7500 180.0000 top
R18 22k R_0603 139.5500 -122.1500 180.0000 top
R19 1k R_0603 71.9500 -90.8000 90.0000 top
R20 33 R_0603 125.2000 -124.2000 180.0000 top
R21 33 R_0603 128.0000 -124.2000 180.0000 top
R22 33 R_0603 116.8000 -124.2000 180.0000 top
R23 33 R_0603 126.7000 -129.7500 180.0000 top
R24 33 R_0603 122.4000 -124.2000 180.0000 top
R25 33 R_0603 132.4000 -129.7500 180.0000 top
R26 33 R_0603 129.5500 -129.7500 180.0000 top
R27 33 R_0603 119.6000 -124.2000 180.0000 top
R28 22k R_0603 70.5500 -110.6500 0.0000 top
R29 22k R_0603 70.5500 -112.1000 180.0000 top
R30 1M R_0603 139.3000 -111.0500 0.0000 top
R31 33 R_0603 80.9500 -108.5000 90.0000 top
RN1 4x33 R4_0402 108.2000 -95.1500 0.0000 top
RN2 4x33 R4_0402 108.4500 -106.2500 270.0000 top
RN3 4x33 R4_0402 108.4500 -110.6500 270.0000 top
RN4 4x10k R4_0402 128.7500 -124.0000 0.0000 top
RN4 4x10k R4_0402 113.5000 -117.2000 0.0000 top
RN5 4x10k R4_0402 69.2500 -96.4500 90.0000 top
U1 EPM240T100C5N TQFP-100_14x14mm_P0.5mm 94.0500 -101.4000 270.0000 top
U2 W9825 TSOP-II-54_22.2x10.16mm_P0.8mm 118.6500 -103.0500 180.0000 top
U3 MX29LV640EB TSOP-I-48_18.4x12mm_P0.5mm 76.7500 -103.0500 180.0000 top
U4 74AHC245 TSSOP-20_4.4x6.5mm_P0.65mm 90.2250 -122.0000 0.0000 top
U5 74AHC245 TSSOP-20_4.4x6.5mm_P0.65mm 108.6250 -122.0000 0.0000 top
U6 74AHC245 TSSOP-20_4.4x6.5mm_P0.65mm 81.0250 -122.0000 0.0000 top
U7 LM393 SOIC-8_3.9mm 132.4570 -115.8240 0.0000 top
U8 AP2125 SOT-23 138.3500 -105.5500 180.0000 top
U9 74AHC245 TSSOP-20_4.4x6.5mm_P0.65mm 99.4250 -122.0000 0.0000 top
U10 LM393 SOIC-8_3.9mm 138.1720 -115.8240 0.0000 top
U12 74AHCT125 TSSOP-14_4.4x5mm_P0.65mm 117.0500 -122.0000 0.0000 top
U3 W25Q128JVSIQ SOIC-8_5.3mm 79.1210 -100.7110 180.0000 top
U4 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 90.2250 -122.0000 0.0000 top
U5 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 108.6250 -122.0000 0.0000 top
U6 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 81.0250 -122.0000 0.0000 top
U7 LM393D SOIC-8_3.9mm 132.4570 -115.8240 0.0000 top
U8 XC6206P332MR SOT-23 138.3500 -105.5500 180.0000 top
U9 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 99.4250 -122.0000 0.0000 top
U10 LM393D SOIC-8_3.9mm 138.1720 -115.8240 0.0000 top
U11 74LVC1G125GW SOT-353 125.0500 -121.8500 90.0000 top
U12 74LVC1G125GW SOT-353 127.8500 -121.8500 90.0000 top
U13 25M Crystal_SMD_3225-4Pin_3.2x2.5mm 107.1000 -102.5000 0.0000 top
U14 74AHCT125 TSSOP-14_4.4x5mm_P0.65mm 124.5000 -122.0000 0.0000 top
U16 74LVC1G04GW SOT-353 108.2000 -98.8500 270.0000 top
U14 74LVC1G125GW SOT-353 116.6500 -121.8500 90.0000 top
U15 74LVC1G125GW SOT-353 126.5500 -127.4500 90.0000 top
U16 74LVC1G125GW SOT-353 108.2000 -98.8500 270.0000 top
U17 74LVC1G125GW SOT-353 122.2500 -121.8500 90.0000 top
U18 74LVC1G125GW SOT-353 132.2500 -127.4500 90.0000 top
U19 74LVC1G125GW SOT-353 129.4000 -127.4500 90.0000 top
U20 74LVC1G125GW SOT-353 113.8500 -121.8500 90.0000 top
U22 74LVC1G125GW SOT-353 119.4500 -121.8500 90.0000 top
## End

549
gerber/GR8RAM.drl
View File

@ -1,7 +1,7 @@
M48
; DRILL file {KiCad (5.1.5-0-10_14)} date Saturday, October 17, 2020 at 05:20:31 PM
; DRILL file {KiCad (5.1.5-0-10_14)} date Wednesday, February 17, 2021 at 07:07:15 PM
; FORMAT={-:-/ absolute / inch / decimal}
; #@! TF.CreationDate,2020-10-17T17:20:31-04:00
; #@! TF.CreationDate,2021-02-17T19:07:15-05:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.1.5-0-10_14)
FMAT,2
INCH
@ -20,7 +20,7 @@ T11C0.0935
G90
G05
T1
X1.825Y-3.78
X1.825Y-3.68
X1.825Y-3.915
X1.825Y-4.115
X1.825Y-4.315
@ -29,13 +29,14 @@ X1.825Y-4.715
X1.825Y-4.915
X1.825Y-5.1
X1.895Y-5.17
X1.925Y-3.575
X1.925Y-4.015
X1.925Y-4.215
X1.925Y-4.415
X1.925Y-4.615
X1.925Y-4.815
X1.98Y-3.62
X1.985Y-3.765
X2.025Y-3.475
X2.025Y-3.715
X2.025Y-3.915
X2.025Y-4.115
X2.025Y-4.315
@ -44,213 +45,164 @@ X2.025Y-4.715
X2.025Y-4.915
X2.025Y-5.17
X2.12Y-5.04
X2.125Y-3.375
X2.125Y-3.615
X2.125Y-3.815
X2.125Y-4.015
X2.125Y-4.215
X2.125Y-4.415
X2.125Y-4.615
X2.125Y-4.815
X2.13Y-3.47
X2.13Y-3.62
X2.22Y-4.315
X2.2Y-3.485
X2.22Y-4.515
X2.22Y-4.715
X2.22Y-4.915
X2.2205Y-3.915
X2.2205Y-4.115
X2.2205Y-4.315
X2.225Y-3.275
X2.225Y-3.715
X2.225Y-3.915
X2.225Y-4.115
X2.225Y-5.17
X2.2598Y-4.3327
X2.2598Y-4.878
X2.275Y-3.325
X2.28Y-3.4
X2.2854Y-4.5354
X2.29Y-3.585
X2.313Y-4.876
X2.32Y-5.04
X2.325Y-3.815
X2.325Y-4.015
X2.345Y-3.475
X2.33Y-3.175
X2.345Y-3.5
X2.345Y-3.675
X2.36Y-3.32
X2.3701Y-4.2067
X2.3701Y-4.3209
X2.415Y-4.6375
X2.4225Y-4.91
X2.425Y-5.17
X2.43Y-3.175
X2.4331Y-4.8996
X2.435Y-4.4449
X2.445Y-3.375
X2.445Y-3.4
X2.445Y-3.575
X2.445Y-3.775
X2.465Y-4.7525
X2.4775Y-4.6075
X2.4843Y-4.5728
X2.495Y-4.6325
X2.5075Y-4.53
X2.52Y-5.04
X2.525Y-4.78
X2.525Y-4.79
X2.525Y-4.82
X2.545Y-3.3
X2.545Y-3.475
X2.545Y-3.5
X2.545Y-3.675
X2.5591Y-4.498
X2.59Y-4.185
X2.59Y-4.24
X2.6122Y-4.8996
X2.6025Y-4.91
X2.625Y-5.17
X2.626Y-3.9882
X2.626Y-4.376
X2.6299Y-3.9921
X2.6299Y-4.3327
X2.645Y-3.175
X2.645Y-3.175
X2.645Y-3.375
X2.645Y-3.41
X2.645Y-3.575
X2.645Y-3.775
X2.6654Y-4.5177
X2.6791Y-3.7972
X2.6909Y-4.3937
X2.6949Y-4.8169
X2.7028Y-4.0098
X2.7028Y-4.2953
X2.7028Y-4.3504
X2.72Y-5.04
X2.7303Y-4.6732
X2.725Y-4.615
X2.725Y-4.815
X2.745Y-3.3
X2.745Y-3.475
X2.7598Y-4.4606
X2.7657Y-4.4173
X2.7677Y-4.6555
X2.7953Y-4.1575
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X2.8051Y-4.6378
X2.8228Y-3.7579
X2.745Y-3.5
X2.745Y-3.675
X2.7461Y-3.7421
X2.7461Y-3.8524
X2.7461Y-4.3228
X2.7461Y-4.4469
X2.825Y-4.515
X2.825Y-4.715
X2.825Y-4.915
X2.825Y-5.17
X2.8346Y-4.3445
X2.8346Y-4.4035
X2.8346Y-4.4783
X2.8327Y-3.5138
X2.8366Y-4.3563
X2.8386Y-4.4134
X2.845Y-3.175
X2.845Y-3.175
X2.8504Y-4.5492
X2.8642Y-4.0433
X2.8661Y-4.6437
X2.874Y-4.4035
X2.876Y-4.3583
X2.8917Y-4.8346
X2.9055Y-4.1969
X2.9055Y-4.5709
X2.9134Y-4.4035
X2.9154Y-3.4921
X2.9173Y-4.6398
X2.9173Y-4.9705
X2.9193Y-4.8071
X2.9311Y-4.3189
X2.9331Y-3.6358
X2.9331Y-3.8957
X2.9409Y-4.5138
X2.845Y-3.41
X2.8661Y-3.6063
X2.925Y-4.615
X2.925Y-4.815
X2.945Y-3.3
X2.9488Y-4.7815
X2.9488Y-4.876
X2.9528Y-3.7106
X2.9528Y-4.4035
X2.9685Y-3.6004
X2.9724Y-4.3661
X2.9724Y-4.5472
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X5.345Y-3.475
X5.35Y-5.17
@ -675,10 +622,12 @@ X5.4055Y-4.3169
X5.439Y-4.9665
X5.445Y-3.175
X5.445Y-3.375
X5.445Y-3.575
X5.45Y-5.17
X5.4744Y-4.2539
X5.545Y-3.475
X5.5551Y-4.8504
X5.5846Y-4.4114
X5.63Y-3.175
X5.63Y-5.17
X5.645Y-3.375
@ -698,28 +647,24 @@ X5.7Y-4.875
X5.7Y-5.1
T2
X3.6378Y-4.374
X3.7874Y-4.374
X3.8012Y-4.2126
X4.3622Y-4.0335
X4.4449Y-3.6201
X5.0984Y-4.8091
X5.1398Y-4.4075
X5.1417Y-4.5256
X5.14Y-4.5225
X5.2874Y-4.7146
X5.2894Y-4.5945
X5.3209Y-4.6545
X5.3346Y-4.2579
X5.3346Y-4.315
X5.3346Y-4.372
X5.3642Y-4.5256
X5.365Y-4.5425
X5.3652Y-4.4065
X5.5157Y-4.5945
X5.5157Y-4.7126
X5.5463Y-4.6545
T3
X4.9783Y-4.311
X5.0177Y-4.0571
X5.0177Y-4.1161
X5.0177Y-4.0669
X5.0177Y-4.1063
T4
X2.89Y-5.06
X2.935Y-5.1
@ -727,8 +672,6 @@ X2.9764Y-4.7461
X3.0Y-5.1
X3.0157Y-4.6496
X3.045Y-5.05
X3.2815Y-3.9429
X3.3209Y-4.0394
X3.378Y-4.6496
X3.4823Y-3.6102
X3.5197Y-3.5709
@ -757,39 +700,31 @@ X4.3091Y-4.0689
X4.3642Y-4.1575
X4.3642Y-4.2126
X4.3642Y-4.3484
X4.4252Y-4.752
X4.4646Y-4.6496
X4.5Y-5.05
X4.545Y-5.1
X4.61Y-5.1
X4.69Y-5.1
X4.7185Y-4.752
X4.755Y-5.1
X4.7579Y-4.6476
X4.8Y-5.05
X4.9783Y-3.7441
X4.9783Y-4.0197
X4.9783Y-4.3661
X4.9783Y-4.5
X5.0177Y-3.6476
X5.0177Y-3.7067
X5.0177Y-4.2146
X5.0177Y-4.2736
X5.0177Y-4.4035
X5.0177Y-4.4626
X5.0177Y-3.6575
X5.0177Y-3.6969
X5.0177Y-4.2244
X5.0177Y-4.2638
X5.1358Y-3.8228
X5.1358Y-3.9213
X5.1614Y-4.122
X5.1614Y-4.189
X5.1772Y-3.7736
X5.1772Y-3.872
X5.1772Y-3.9705
X5.1614Y-4.1319
X5.1614Y-4.1791
X5.187Y-3.7736
X5.187Y-3.872
X5.187Y-3.9705
X5.2106Y-4.0807
X5.2441Y-3.7736
X5.2441Y-3.872
X5.2441Y-3.9705
X5.2598Y-4.122
X5.2598Y-4.189
X5.2343Y-3.7736
X5.2343Y-3.872
X5.2343Y-3.9705
X5.2598Y-4.1319
X5.2598Y-4.1791
X5.2854Y-3.7264
X5.2854Y-3.8228
X5.2854Y-3.9213
@ -801,7 +736,6 @@ X5.3583Y-4.1181
X5.3583Y-4.1929
X5.4Y-5.0
X5.445Y-5.05
X5.5846Y-4.4173
X5.6004Y-3.6102
X5.6476Y-4.2047
X5.6496Y-3.6516
@ -828,9 +762,12 @@ T9
X2.365Y-4.695
X2.665Y-4.655
X2.665Y-4.735
X2.365Y-4.695
X2.665Y-4.655
X2.665Y-4.735
T10
X1.895Y-3.885
X2.295Y-3.385
X1.895Y-3.785
X2.245Y-3.335
X5.63Y-5.0
X1.895Y-5.0
X5.53Y-3.245
@ -839,6 +776,10 @@ X2.365Y-4.595
X2.365Y-4.795
X2.59Y-4.595
X2.59Y-4.795
X2.365Y-4.595
X2.365Y-4.795
X2.59Y-4.595
X2.59Y-4.795
T6
G00X4.0472Y-3.4567
M15