mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-05-28 14:41:27 +00:00
375 lines
8.0 KiB
Verilog
Executable File
375 lines
8.0 KiB
Verilog
Executable File
module GR8RAM(C25M, PHI0, nPBOD, nBOD, nRES,
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nIOSEL, nDEVSEL, nIOSTRB,
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RA, nWEin, nWEout, Adir,
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RD, Ddir,
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DMAin, DMAout, INTin, INTout,
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nDMA, nRDY, nNMI, nIRQ, nINH, nRESout
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SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
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nFCS, FCK, MISO, MOSI);
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/* Clock signals */
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input C25M, PHI0;
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reg PHI0r1, PHI0r2, PHI0r3;
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always @(negedge C25M) begin PHI0r1 <= PHI0; end
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always @(posedge C25M) begin
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PHI0r2 <= PHI0r1; PHI0r3 <= PHI0r2;
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end
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/* Reset/brown-out detect inputs */
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input nRES, nPBOD, nBOD;
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reg PBODr1, PBODr2, BODr1, BODr2, RESr1, RESr2;
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always @(negedge C25M) begin
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PBODr1 <= ~nPBOD; BODr1 <= ~nBOD; RESr1 <= ~nRES;
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end
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always @(posedge C25M) begin
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PBODr2 <= PBODr1; BODr2 <= BODr1; RESr2 <= RESr1;
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end
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/* Apple IO area select signals */
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input nIOSEL, nDEVSEL, nIOSTRB;
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reg DEVSELr1, DEVSELr2;
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always @(negedge C25M) begin DEVSELr1 <= ~nDEVSEL; end
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always @(posedge C25M) begin DEVSELr2 <= DEVSELr1; end
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/* DMA/IRQ daisy chain */
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input DMAin, INTin;
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output DMAout = DMAin;
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output INTout = INTin;
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/* Apple open-drain outputs */
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output nDMA = 1;
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output nRDY = 1;
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output nNMI = 1;
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output nIRQ = 1;
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output nINH = 1;
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output nRESout = 0;
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/* Apple address bus */
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input [15:0] RA;
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input nWEin;
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output RAdir = 1;
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output nWEout = 1;
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reg [15:0] RAr1; reg nWEr1;
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reg [15:0] RAr2; reg nWEr2;
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reg [15:0] RAcur; reg nWEcur;
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always @(negedge C25M) begin RAr1 <= RA; nWEr1 <= nWE; end
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always @(posedge C25M) begin RAr2 <= RAr1; nWEr2 <= nWEr1; end
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always @(posedge C25M) begin
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if (S==0 && ~PHI0r2) begin
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RAcur <= RAr2;
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nWEcur <= nWER2;
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end
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end
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/* Apple select signals */
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wire ROMSpecSEL = RAcur[15:12]==4'hC && RAcur[11:8]!=4'h0;
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wire ROMSpecRD = ROMSpecSEL && nWE;
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wire RAMSpecSEL = RAcur[15:12]==4'hC && RAcur[11:8]==4'h0 && RAcur[7] && RAcur[7:4]!=4'h8 && RAcur[3:0]==4'h3;
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wire RAMSpecRD = RAMSpecSEL && nWE;
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wire RAMSpecWR = RAMSpecSEL && ~nWE;
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wire SpecRD = ROMSpecRD || RAMSpecRD;
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reg RAMRD = 0, RAMWR = 0;
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always @(posedge C25M) begin
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if (S==5) begin
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RAMRD <= RAMSpecRD && DEVSELr2;
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RAMWR <= RAMSpecWR && DEVSELr2;
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end else if (S==0) begin
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RAMRD <= 0;
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RAMWR <= 0;
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end
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end
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/* Apple data bus */
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inout [7:0] RD = RDdir ? 8'bZ : RDout[7:0];
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reg RDdir = 1;
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reg [7:0] RDout;
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/* SDRAM data bus */
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inout [7:0] SD = SDOE ? RD[7:0] : 8'bZ;
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reg SDOE = 0;
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/* SDRAM address/command */
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output reg [1:0] SBA;
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output reg [12:0] SA;
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output reg RCKE = 1;
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output reg nRCS = 1;
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output reg nRAS = 1;
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output reg nCAS = 1;
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output reg nSWE = 1;
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output reg DQMH = 1;
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output reg DQML = 1;
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/* SPI flash */
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output reg nFCS = 1;
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output reg FCK = 0;
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output reg MOSI = MOSIOE ? MOSIout : 1'bZ;
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reg MOSIOE = 0;
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reg MOSIout;
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input MISO;
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/* State counters */
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reg [24:0] FS = 0;
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always @(posedge C25M) begin FS <= FS+1; end
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reg [2:0] S = 0;
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always @(posedge C25M) begin
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if (S==0 && PHI0r2 && ~PHI0r3 && ~RESr2 && ~BODr2) S <= 1;
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else if (S==0) S <= 0;
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else S <= S+1;
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end
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/* Refresh state */
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reg RefReady = 0;
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reg RefDone = 0;
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always @(posedge C25M) begin RefReady <= S==0; end
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always @(posedge C25M) begin
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if (FS[6:0]==7'h00) RefDone <= 0;
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else (S==0 && RefReady && RCKE && ~(PHI0r2 && ~PHI0r3)) RefDone <= 1;
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end
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/* Slinky registers */
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reg [24:0] Addr;
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wire AddrHSpecSEL = RAcur[3:0]==4'h2;
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wire AddrMSpecSEL = RAcur[3:0]==4'h1;
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wire AddrLSpecSEL = RAcur[3:0]==4'h0;
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always @(posedge C25M) begin
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if (S==7 && DEVSELr2) begin
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if (AddrHSpecSEL || AddrMSpecSEL || AddrLSpecSEL) begin
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Addr[24] <= 1'b0;
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end
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if (AddrHSpecSEL) begin
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Addr[23:16] <= RD[7:0];
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end else if (RAMRD || RAMWR ||
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(AddrMSpecSEL && Addr[15] && ~RD[7]) ||
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(AddrLSpecSEL && Addr[7] && ~RD[7] && Addr[15:8]==8'hFF)) begin
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Addr[23:16] <= Addr[23:16]+1;
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end
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if (AddrMSpecSEL) begin
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Addr[15:8] <= RD[7:0];
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end else if (RAMRD || RAMWR ||
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(AddrLSpecSEL && Addr[7] && ~RD[7])) begin
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Addr[15:8] <= Addr[15:8]+1;
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end
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if (AddrLSpecSEL) begin
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Addr[7:0] <= RD[7:0];
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end else if (RAMRD || RAMWR) begin
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Addr[7:0] <= Addr[7:0]+1;
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end
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end
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end
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always @(posedge C25M) begin
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if (S==0) begin
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if ((PHI0r2 && ~PHI0r3 && ~RESr2 && ~BODr2 && SpecRD) ||
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(~RefReady && ~RefDone)) begin
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// NOP cken
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RCKE <= 1'b1;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end else if (RefReady && ~RefDone && RCKE &&
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~(PHI0r2 && ~PHI0r3)) begin
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// AREF
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RCKE <= 1'b1;
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nRCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end else begin
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// NOP ckdis
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end
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end else if (S==4'h1) begin
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if (SpecRD) begin
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// ACT
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RCKE <= 1'b1;
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nRCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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if (RAMSpecRD) begin
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RBA[1] <= Addr[24];
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RBA[0] <= Addr[23];
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RA[12:0] <= Addr[22:10];
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end else begin
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RBA[1] <= 1'b1;
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RBA[0] <= 1'b0;
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RA[12:10] <= 3'b000;
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RA[9:2] <= Bank[7:0];
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RA[1:0] <= RAcur[11:10];
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end
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end else begin
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// NOP ckdis
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end
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end else if (S==4'h2) begin
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if (SpecRD) begin
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// RD auto-PC
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RCKE <= 1'b1;
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nRCS <= 1'b0;
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nRAS <= 1'b1;
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nCAS <= 1'b0;
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nSWE <= 1'b1;
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A[12:11] <= 1'b0; // don't care
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A[10] <= 1'b1; // auto-precharge
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A[9] <= 1'b0; // don't care
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if (RAMSpecRD) begin
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RBA[1] <= Addr[24];
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RBA[0] <= Addr[23];
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RA[8:0] <= Addr[9:1];
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DQMH <= ~Addr[0];
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DQML <= Addr[0];
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end else /* ROMSpecRD */ begin
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RBA[1] <= 1'b1;
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RBA[0] <= 1'b0;
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RA[8:0] <= RAcur[9:1];
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DQMH <= ~RAcur[0];
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DQML <= RAcur[0];
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end
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end else begin
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// NOP ckdis
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end
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end else if (S==4'h3) begin
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if (SpecRD) begin
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// NOP cken
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RCKE <= 1'b1;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end else begin
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// NOP ckdis
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end
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end else if (S==4'h4) begin
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if (RAMSpecWR) begin
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// NOP cken
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RCKE <= 1'b1;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end else begin
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// NOP ckdis
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end
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end else if (S==4'h5) begin
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if (RAMSpecWR && DEVSELr2) begin
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// ACT
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RCKE <= 1'b1;
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nRCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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BA[1] <= Addr[24];
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BA[0] <= Addr[23];
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A[12:0] <= Addr[22:10];
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end else begin
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// NOP ckdis
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end
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end else if (s==4'h6) begin
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if (RAMWR) begin
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// WR auto-PC
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RCKE <= 1'b1;
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nRCS <= 1'b0;
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nRAS <= 1'b1;
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nCAS <= 1'b0;
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nSWE <= 1'b0;
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BA[1] <= Addr[24];
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BA[0] <= Addr[23];
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A[12:11] <= 1'b0; // don't care
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A[10] <= 1'b1; // auto-precharge
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A[9:0] <= Addr[9:0];
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DQMH <= ~Addr[10];
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DQML <= Addr[10];
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end else begin
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// NOP ckdis
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end
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end else if (S==4'h7) begin
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if (RAMSpecWR) begin
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// NOP cken
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RCKE <= 1'b1;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end else begin
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// NOP ckdis
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end
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end
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end
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endmodule
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