Apple-2-HW
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GR8RAM
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Trying again with RamFactor firmware

This commit is contained in:
Zane Kaminski 2019-09-02 20:56:37 -04:00
parent a73cbf10ef
commit 106df31f52
38 changed files with 321 additions and 323 deletions
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cpld/GR8RAM.qws
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cpld/GR8RAM.v
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@ -30,7 +30,8 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
input nWE; // 6502 R/W
output [10:0] RA; // DRAM/ROM address
assign RA[10:8] = ASel ? Addr[21:19] : Addr[10:8];
assign RA[7:0] = (~nIOSTRB & ~IOBank0) ? Bank+1 :
assign RA[7:0] = (~nIOSTRB & FullIOEN) ? Bank+1 :
(~nIOSTRB & ~FullIOEN) ? {7'b0000001, Bank[0]} :
(~ASel & nIOSEL & nIOSTRB) ? Addr[18:11] :
(ASel & nIOSEL & nIOSTRB) ? Addr[7:0] : 8'h00;
@ -42,7 +43,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
wire DOE = CSDBEN & nWE &
((~nDEVSEL & REGEN) | ~nIOSEL | (~nIOSTRB & IOROMEN));
wire [7:0] Dout = (nDEVSEL | RAMSELA) ? RD[7:0] :
AddrHSELA ? {4'b1111, Addr[19:16]} :
AddrHSELA ? {1'b1, Addr[22:16]} :
AddrMSELA ? Addr[15:8] :
AddrLSELA ? Addr[7:0] : 8'h00;
inout [7:0] D = DOE ? Dout : 8'bZ;
@ -97,7 +98,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
reg IOROMEN = 0; // IOSTRB ROM enable
reg CSDBEN = 0; // ROM CS, data bus driver gating
reg ASel = 0; // DRAM address multiplexer select
reg IOBank0 = 0;
reg FullIOEN = 0;
// Apple II Bus Compatibiltiy Rules:
// Synchronize to PHI0 or PHI1. (PHI1 here)
@ -121,7 +122,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
CSDBEN <= 1'b0;
Addr <= 23'h000000;
Bank <= 8'h00;
IOBank0 <= 1'b0;
FullIOEN <= 1'b0;
RAMSELreg <= 1'b0;
end else begin
// Synchronize state counter to S1 when just entering PHI1
@ -163,8 +164,8 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
// Set register during S6 if accessed.
if (S==6) begin
if (BankWR) Bank[7:0] <= D[7:0]; // Bank
if (SetWR) IOBank0 <= D[7:0] == 8'hE5;
if (AddrHWR) Addr[19:16] <= D[3:0]; // Addr hi
if (SetWR) FullIOEN <= D[7:0] == 8'hE5;
if (AddrHWR) Addr[22:16] <= D[6:0]; // Addr hi
if (AddrMWR) Addr[15:8] <= D[7:0]; // Addr mid
if (AddrLWR) Addr[7:0] <= D[7:0]; // Addr lo
end

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cpld/db/GR8RAM.asm.qmsg
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@ -1,5 +1,5 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567402893262 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402893262 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:41:32 2019 " "Processing started: Mon Sep 02 01:41:32 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402893262 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567402893262 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567402893262 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567402895340 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402895809 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:41:35 2019 " "Processing ended: Mon Sep 02 01:41:35 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402895809 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402895809 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402895809 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567402895809 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567472156106 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567472156106 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 20:55:55 2019 " "Processing started: Mon Sep 02 20:55:55 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567472156106 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567472156106 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567472156106 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567472157934 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567472158387 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 20:55:58 2019 " "Processing ended: Mon Sep 02 20:55:58 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567472158387 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567472158387 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567472158387 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567472158387 ""}

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cpld/db/GR8RAM.db_info
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@ -1,3 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Mon Sep 02 01:36:55 2019
Creation_Time = Mon Sep 02 20:55:35 2019

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cpld/db/GR8RAM.fit.qmsg
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@ -1,3 +1,3 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567402890980 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567402890996 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402891543 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:41:31 2019 " "Processing ended: Mon Sep 02 01:41:31 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402891543 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402891543 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402891543 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567402891543 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567472153965 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567472153981 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567472154481 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 20:55:54 2019 " "Processing ended: Mon Sep 02 20:55:54 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567472154481 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567472154481 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567472154481 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567472154481 ""}

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cpld/db/GR8RAM.hier_info
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@ -3,7 +3,7 @@ C7M => CASr.CLK
C7M => RASr.CLK
C7M => ASel.CLK
C7M => RAMSELreg.CLK
C7M => IOBank0.CLK
C7M => FullIOEN.CLK
C7M => Bank[0].CLK
C7M => Bank[1].CLK
C7M => Bank[2].CLK

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cpld/db/GR8RAM.map.qmsg
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@ -1,36 +1,36 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567402877574 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402877574 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:41:17 2019 " "Processing started: Mon Sep 02 01:41:17 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402877574 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567402877574 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567402877574 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567402881230 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(40) " "Verilog HDL warning at GR8RAM.v(40): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 40 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567402881340 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(48) " "Verilog HDL warning at GR8RAM.v(48): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 48 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567402881340 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(175) " "Verilog HDL information at GR8RAM.v(175): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 175 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567402881340 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567402881340 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567402881340 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567402881824 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(33) " "Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402881840 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402881840 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(135) " "Verilog HDL assignment warning at GR8RAM.v(135): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 135 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402881840 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 GR8RAM.v(159) " "Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (23)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402881840 "|GR8RAM"}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402882199 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567402882199 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402882199 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402882199 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567402882199 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402882699 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402882699 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402882699 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402882699 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567402882699 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402883012 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883012 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883012 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883012 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883012 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567402883012 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883277 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883637 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883652 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883934 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884215 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884230 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402884277 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add3 " "Instantiated megafunction \"lpm_add_sub:Add3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 23 " "Parameter \"LPM_WIDTH\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884277 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884277 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884277 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884277 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567402884277 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|addcore:adder\[2\] lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|addcore:adder\[2\]\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884293 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|look_add:look_ahead_unit lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884387 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|altshift:result_ext_latency_ffs lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884387 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "31 " "Ignored 31 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "31 " "Ignored 31 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567402884715 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567402884715 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567402884871 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567402884871 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567402884871 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567402885324 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567402885324 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567402885324 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567402885324 ""} { "Info" "ICUT_CUT_TM_MCELLS" "102 " "Implemented 102 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567402885324 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567402885324 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567402885605 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402885715 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:41:25 2019 " "Processing ended: Mon Sep 02 01:41:25 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402885715 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402885715 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402885715 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567402885715 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567472141027 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567472141042 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 20:55:40 2019 " "Processing started: Mon Sep 02 20:55:40 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567472141042 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567472141042 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567472141042 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567472144652 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(41) " "Verilog HDL warning at GR8RAM.v(41): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 41 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567472144777 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(49) " "Verilog HDL warning at GR8RAM.v(49): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 49 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567472144777 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(176) " "Verilog HDL information at GR8RAM.v(176): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 176 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567472144777 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567472144793 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567472144793 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567472145183 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(33) " "Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567472145183 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567472145183 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(136) " "Verilog HDL assignment warning at GR8RAM.v(136): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 136 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567472145183 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 GR8RAM.v(160) " "Verilog HDL assignment warning at GR8RAM.v(160): truncated value with size 32 to match size of target (23)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567472145199 "|GR8RAM"}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472145527 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567472145527 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472145543 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472145543 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567472145543 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472145949 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472145949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472145949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472145949 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567472145949 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472146261 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146261 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146261 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146261 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146261 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567472146261 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146480 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146699 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146715 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146980 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147199 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147199 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472147246 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add3 " "Instantiated megafunction \"lpm_add_sub:Add3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 23 " "Parameter \"LPM_WIDTH\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147246 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147246 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147246 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147246 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567472147246 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|addcore:adder\[2\] lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|addcore:adder\[2\]\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147246 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|look_add:look_ahead_unit lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147308 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|altshift:result_ext_latency_ffs lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147324 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "31 " "Ignored 31 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "31 " "Ignored 31 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567472147683 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567472147683 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567472147886 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567472147886 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567472147886 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567472148308 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567472148308 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567472148308 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567472148308 ""} { "Info" "ICUT_CUT_TM_MCELLS" "102 " "Implemented 102 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567472148308 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567472148308 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567472148605 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567472148777 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 20:55:48 2019 " "Processing ended: Mon Sep 02 20:55:48 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567472148777 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567472148777 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567472148777 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567472148777 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567402899152 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402899168 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:41:37 2019 " "Processing started: Mon Sep 02 01:41:37 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402899168 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567402899168 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567402899168 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567402899324 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567402901637 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567402901699 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567402901715 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567402901871 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567402902059 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567402902059 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902074 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902074 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902074 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567402902090 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567402902309 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.000 " "Worst-case setup slack is -47.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.000 -1763.000 C7M " " -47.000 -1763.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567402902371 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567402902402 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -432.000 C7M " " -4.500 -432.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902465 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567402902465 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567402902637 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567402902715 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567402902715 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "263 " "Peak virtual memory: 263 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402902934 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:41:42 2019 " "Processing ended: Mon Sep 02 01:41:42 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402902934 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402902934 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402902934 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567402902934 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567472162325 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567472162341 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 20:55:59 2019 " "Processing started: Mon Sep 02 20:55:59 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567472162341 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567472162341 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567472162341 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567472162450 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567472164700 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567472164731 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567472164731 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567472164872 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567472165013 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567472165013 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165028 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165028 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165028 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567472165044 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567472165185 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.000 " "Worst-case setup slack is -47.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165200 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165200 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.000 -1816.000 C7M " " -47.000 -1816.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165200 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165200 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567472165200 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165247 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567472165247 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567472165263 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567472165278 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -432.000 C7M " " -4.500 -432.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165294 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567472165294 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567472165435 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567472165497 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567472165497 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "263 " "Peak virtual memory: 263 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567472165685 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 20:56:05 2019 " "Processing ended: Mon Sep 02 20:56:05 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567472165685 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567472165685 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567472165685 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567472165685 ""}

BIN
cpld/db/GR8RAM.sta.rdb
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Binary file not shown.

BIN
cpld/db/GR8RAM.sta_cmp.15_slow.tdb
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Binary file not shown.

12
cpld/output_files/GR8RAM.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for GR8RAM
Mon Sep 02 01:41:35 2019
Mon Sep 02 20:55:58 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Mon Sep 02 01:41:35 2019 ;
; Assembler Status ; Successful - Mon Sep 02 20:55:58 2019 ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX7000S ;
@ -89,7 +89,7 @@ applicable agreement for further details.
+----------------+-------------------------------------------------------+
; Device ; EPM7128SLC84-15 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x00179BB7 ;
; Checksum ; 0x0017B008 ;
+----------------+-------------------------------------------------------+
@ -99,13 +99,13 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Mon Sep 02 01:41:32 2019
Info: Processing started: Mon Sep 02 20:55:55 2019
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 277 megabytes
Info: Processing ended: Mon Sep 02 01:41:35 2019
Info: Processing ended: Mon Sep 02 20:55:58 2019
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03
Info: Total CPU time (on all processors): 00:00:02

2
cpld/output_files/GR8RAM.done
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@ -1 +1 @@
Mon Sep 02 01:41:43 2019
Mon Sep 02 20:56:06 2019

357
cpld/output_files/GR8RAM.fit.rpt
View File

@ -1,5 +1,5 @@
Fitter report for GR8RAM
Mon Sep 02 01:41:31 2019
Mon Sep 02 20:55:54 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -53,7 +53,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Mon Sep 02 01:41:31 2019 ;
; Fitter Status ; Successful - Mon Sep 02 20:55:54 2019 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
@ -98,7 +98,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+------------------------------+--------------------+
; Logic cells ; 102 / 128 ( 80 % ) ;
; Registers ; 50 / 128 ( 39 % ) ;
; Number of pterms used ; 249 ;
; Number of pterms used ; 251 ;
; I/O pins ; 67 / 68 ( 99 % ) ;
; -- Clock pins ; 2 / 2 ( 100 % ) ;
; -- Dedicated input pins ; 2 / 2 ( 100 % ) ;
@ -106,11 +106,11 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; Global signals ; 2 ;
; Shareable expanders ; 0 / 128 ( 0 % ) ;
; Parallel expanders ; 0 / 120 ( 0 % ) ;
; Cells using turbo bit ; 56 / 128 ( 44 % ) ;
; Cells using turbo bit ; 57 / 128 ( 45 % ) ;
; Maximum fan-out ; 50 ;
; Highest non-global fan-out ; 48 ;
; Total fan-out ; 962 ;
; Average fan-out ; 5.69 ;
; Total fan-out ; 971 ;
; Average fan-out ; 5.75 ;
+------------------------------+--------------------+
@ -186,9 +186,9 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; D[1] ; 35 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
; D[2] ; 34 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
; D[3] ; 33 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
; D[4] ; 29 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
; D[5] ; 28 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
; D[6] ; 27 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
; D[4] ; 29 ; -- ; 3 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
; D[5] ; 28 ; -- ; 3 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
; D[6] ; 27 ; -- ; 3 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
; D[7] ; 25 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
; RD[0] ; 73 ; -- ; 8 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
; RD[1] ; 70 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
@ -346,15 +346,14 @@ Note: User assignments will override these defaults. The user specified values a
; A[1] ; PIN_76 ; 15 ; Clock enable ; no ; -- ; -- ;
; A[2] ; PIN_77 ; 15 ; Clock enable ; no ; -- ; -- ;
; A[3] ; PIN_79 ; 15 ; Clock enable ; no ; -- ; -- ;
; BankWR_MC ; LC103 ; 8 ; Clock enable ; no ; -- ; -- ;
; BankWR_MC ; LC111 ; 8 ; Clock enable ; no ; -- ; -- ;
; C7M ; PIN_83 ; 48 ; Clock ; yes ; On ; -- ;
; C7M_2 ; PIN_84 ; 3 ; Clock ; no ; -- ; -- ;
; PHI1b9_MC ; LC37 ; 6 ; Clock enable ; no ; -- ; -- ;
; RAMSELreg ; LC36 ; 24 ; Clock enable ; no ; -- ; -- ;
; REGEN ; LC84 ; 7 ; Clock enable ; no ; -- ; -- ;
; S[0] ; LC126 ; 46 ; Clock enable ; no ; -- ; -- ;
; S[1] ; LC114 ; 47 ; Clock enable ; no ; -- ; -- ;
; S[2] ; LC113 ; 48 ; Clock enable ; no ; -- ; -- ;
; REGEN ; LC106 ; 7 ; Clock enable ; no ; -- ; -- ;
; S[0] ; LC113 ; 46 ; Clock enable ; no ; -- ; -- ;
; S[1] ; LC121 ; 47 ; Clock enable ; no ; -- ; -- ;
; S[2] ; LC117 ; 48 ; Clock enable ; no ; -- ; -- ;
; nDEVSEL ; PIN_21 ; 16 ; Clock enable ; no ; -- ; -- ;
; nIOSEL ; PIN_74 ; 13 ; Clock enable ; no ; -- ; -- ;
; nRES ; PIN_1 ; 50 ; Async. clear ; yes ; On ; -- ;
@ -407,7 +406,7 @@ Note: User assignments will override these defaults. The user specified values a
; nWE ; 10 ;
; Addr[15] ; 10 ;
; Addr[16] ; 9 ;
; IOBank0 ; 8 ;
; FullIOEN ; 8 ;
; Addr[17] ; 8 ;
; Bank[0] ; 8 ;
; BankWR_MC ; 8 ;
@ -417,8 +416,12 @@ Note: User assignments will override these defaults. The user specified values a
; DOE~5 ; 8 ;
; Addr[18] ; 7 ;
; Bank[1] ; 7 ;
; AddrHWR_MC ; 7 ;
; RAMSEL_MC ; 7 ;
; REGEN ; 7 ;
; D[6]~6 ; 6 ;
; D[5]~5 ; 6 ;
; D[4]~4 ; 6 ;
; D[3]~3 ; 6 ;
; D[2]~2 ; 6 ;
; D[1]~1 ; 6 ;
@ -430,18 +433,14 @@ Note: User assignments will override these defaults. The user specified values a
; lpm_counter:Ref_rtl_0|dffs[0] ; 6 ;
; PHI1b9_MC ; 6 ;
; D[7]~7 ; 5 ;
; D[6]~6 ; 5 ;
; D[5]~5 ; 5 ;
; D[4]~4 ; 5 ;
; Addr[20] ; 5 ;
; Bank[3] ; 5 ;
; lpm_counter:Ref_rtl_0|dffs[1] ; 5 ;
; Addr[22] ; 4 ;
; Addr[21] ; 4 ;
; Bank[4] ; 4 ;
; Addr[20] ; 4 ;
; AddrHWR_MC ; 4 ;
; C7M_2 ; 3 ;
; Bank[5] ; 3 ;
; Addr[22] ; 3 ;
; Addr[21] ; 3 ;
; IOROMEN ; 3 ;
; CSDBEN ; 3 ;
; PHI0seen ; 3 ;
@ -466,24 +465,24 @@ Note: User assignments will override these defaults. The user specified values a
; A[5] ; 1 ;
; A[4] ; 1 ;
; ~VCC~0 ; 1 ;
; RA~110 ; 1 ;
; RA~103 ; 1 ;
; RA~96 ; 1 ;
; RA~89 ; 1 ;
; RA~82 ; 1 ;
; RA~81 ; 1 ;
; RA~75 ; 1 ;
; RA~70 ; 1 ;
; RA~120 ; 1 ;
; RA~108 ; 1 ;
; RA~101 ; 1 ;
; RA~94 ; 1 ;
; RA~87 ; 1 ;
; RA~80 ; 1 ;
; RA~79 ; 1 ;
; RA~73 ; 1 ;
; Bank[7] ; 1 ;
; comb~55 ; 1 ;
; comb~51 ; 1 ;
; RA~66 ; 1 ;
; RA~63 ; 1 ;
; RA~60 ; 1 ;
; comb~48 ; 1 ;
; comb~43 ; 1 ;
; comb~39 ; 1 ;
; RA~68 ; 1 ;
; RA~65 ; 1 ;
; RA~62 ; 1 ;
; comb~36 ; 1 ;
; RASf ; 1 ;
; RASr ; 1 ;
; comb~46 ; 1 ;
; comb~34 ; 1 ;
; PHI1b8_MC ; 1 ;
; PHI1b7_MC ; 1 ;
; PHI1b6_MC ; 1 ;
@ -491,7 +490,7 @@ Note: User assignments will override these defaults. The user specified values a
; PHI1b4_MC ; 1 ;
; PHI1b3_MC ; 1 ;
; PHI1b2_MC ; 1 ;
; comb~42 ; 1 ;
; comb~30 ; 1 ;
; PHI1b1_MC ; 1 ;
; C7M_2~1 ; 1 ;
; nWE~1 ; 1 ;
@ -504,14 +503,14 @@ Note: User assignments will override these defaults. The user specified values a
; D[2]~28 ; 1 ;
; D[1]~26 ; 1 ;
; D[0]~24 ; 1 ;
; Dout[7]~95 ; 1 ;
; Dout[6]~89 ; 1 ;
; Dout[5]~83 ; 1 ;
; Dout[4]~77 ; 1 ;
; Dout[3]~71 ; 1 ;
; Dout[2]~65 ; 1 ;
; Dout[1]~59 ; 1 ;
; Dout[0]~53 ; 1 ;
; Dout[7]~113 ; 1 ;
; Dout[6]~107 ; 1 ;
; Dout[5]~101 ; 1 ;
; Dout[4]~95 ; 1 ;
; Dout[3]~89 ; 1 ;
; Dout[2]~83 ; 1 ;
; Dout[1]~77 ; 1 ;
; Dout[0]~71 ; 1 ;
+-------------------------------+---------+
@ -521,28 +520,26 @@ Note: User assignments will override these defaults. The user specified values a
; Other Routing Resource Type ; Usage ;
+-----------------------------+--------------------+
; Output enables ; 2 / 6 ( 33 % ) ;
; PIA buffers ; 215 / 288 ( 75 % ) ;
; PIAs ; 238 / 288 ( 83 % ) ;
; PIA buffers ; 196 / 288 ( 68 % ) ;
; PIAs ; 221 / 288 ( 77 % ) ;
+-----------------------------+--------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 29.75) ; Number of LABs (Total = 8) ;
; LAB External Interconnects (Average = 27.63) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 0 ;
; 12 - 14 ; 0 ;
; 15 - 17 ; 0 ;
; 18 - 20 ; 0 ;
; 21 - 23 ; 1 ;
; 24 - 26 ; 0 ;
; 27 - 29 ; 2 ;
; 30 - 32 ; 3 ;
; 33 - 35 ; 2 ;
; 0 - 3 ; 0 ;
; 4 - 7 ; 0 ;
; 8 - 11 ; 0 ;
; 12 - 15 ; 1 ;
; 16 - 19 ; 0 ;
; 20 - 23 ; 0 ;
; 24 - 27 ; 2 ;
; 28 - 31 ; 4 ;
; 32 - 35 ; 0 ;
; 36 - 39 ; 1 ;
+-----------------------------------------------+-----------------------------+
@ -558,127 +555,127 @@ Note: User assignments will override these defaults. The user specified values a
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 7 ; 1 ;
; 8 ; 2 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 1 ;
; 13 ; 2 ;
; 14 ; 1 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
; 16 ; 1 ;
; 16 ; 4 ;
+-----------------------------------------+-----------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[2], S[1], S[0], Addr[1], Addr[0], RAMSELreg ; Dout[1]~59, Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~75 ;
; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[2], S[1], S[0], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[7]~95, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~110 ;
; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[3]~71, Addr[11], Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~70 ;
; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[2]~65, Addr[11], Addr[16], Addr[17], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], RA~66, Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ;
; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[2], S[1], S[0], Addr[0], RAMSELreg ; Dout[0]~53, Addr[0], Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~70 ;
; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[1]~59, Addr[11], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], RA~63, Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ;
; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[7]~95, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[15], RA~89 ;
; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[2], S[1], S[0], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[6]~89, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[6], Addr[14], Addr[15], RA~103 ;
; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[0]~53, Addr[11], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], RA~60, Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ;
; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[2], S[1], S[0], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[5]~83, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~96 ;
; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[2], S[1], S[0], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[2]~65, Addr[11], Addr[7], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~81 ;
; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[5]~83, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[13], Addr[14], Addr[15], RA~81 ;
; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[4]~77, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~75 ;
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[2], S[1], S[0], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[4]~77, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~89 ;
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[6]~89, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[14], Addr[15], RA~82 ;
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[2], S[1], S[0], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[3]~71, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~82 ;
; B ; LC24 ; C7M, nRES, D[3], BankWR_MC, S[2], S[1], S[0] ; RA~82, RA~89, RA~96, RA~103, RA~110 ;
; B ; LC32 ; C7M, nRES, Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[20], S[2], RAMSELreg, S[1], S[0] ; Addr[20], RA~63, Addr[21], Addr[22] ;
; B ; LC20 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[1], S[0], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[3]~71, Addr[19], RA~60, Addr[20], Addr[21], Addr[22] ;
; B ; LC19 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[1], S[0], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[2]~65, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~110 ;
; B ; LC23 ; C7M, nRES, D[2], BankWR_MC, S[2], S[1], S[0] ; RA~81, RA~82, RA~89, RA~96, RA~103, RA~110 ;
; B ; LC29 ; C7M, nRES, D[0], AddrHWR_MC, S[2], S[1], S[0], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[0]~53, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~96 ;
; B ; LC17 ; ; nINH ;
; B ; LC25 ; C7M, nRES, D[1], BankWR_MC, S[2], S[1], S[0] ; RA~75, RA~81, RA~82, RA~89, RA~96, RA~103, RA~110 ;
; B ; LC31 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[1], S[0], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[1]~59, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~103 ;
; B ; LC27 ; C7M, nRES, D[0], BankWR_MC, S[2], S[1], S[0] ; RA~70, RA~75, RA~81, RA~82, RA~89, RA~96, RA~103, RA~110 ;
; B ; LC26 ; C7M, nRES, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[22], S[2], RAMSELreg, S[1], S[0] ; Addr[22], comb~51, comb~55 ;
; B ; LC30 ; C7M, nRES, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[21], S[2], RAMSELreg, S[1], S[0] ; Addr[21], RA~66, Addr[22] ;
; C ; LC34 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1] ; comb~48 ;
; C ; LC36 ; C7M, nRES, S[2], S[1], S[0], RAMSEL_MC, RAMSELreg ; RAMSELreg, Addr[0], Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15] ;
; C ; LC46 ; PHI1in ; PHI1b1_MC ;
; C ; LC35 ; C7M_2 ; C7Mout ;
; C ; LC37 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, PHI1out, S[0], S[1], S[2] ;
; C ; LC38 ; RD[4], nDEVSEL, A[1], A[2], A[3], A[0], Addr[12], Addr[4] ; D[4] ;
; C ; LC40 ; RD[5], nDEVSEL, A[1], A[2], A[3], A[0], Addr[13], Addr[5] ; D[5] ;
; C ; LC43 ; RD[6], nDEVSEL, A[1], A[2], A[3], A[0], Addr[14], Addr[6] ; D[6] ;
; C ; LC45 ; RD[7], nDEVSEL, A[1], A[2], A[3], A[0], Addr[15], Addr[7] ; D[7] ;
; C ; LC39 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; C ; LC42 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; C ; LC41 ; nRES, S[2], S[1], S[0], nWE, C7M_2 ; comb~51, comb~55 ;
; C ; LC48 ; C7M, nRES, RAMSEL_MC, S[2], S[1] ; RA~60, RA~63, RA~66, RA~70, RA~75, RA~81, RA~82, RA~89, RA~96, RA~103, RA~110 ;
; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ;
; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ;
; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ;
; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ;
; D ; LC56 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ;
; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ;
; D ; LC52 ; PHI1b6_MC ; PHI1b8_MC ;
; D ; LC51 ; Addr[22], CASf, RAMSEL_MC, CASr ; nCAS1 ;
; D ; LC53 ; Addr[22], CASf, RAMSEL_MC, CASr ; nCAS0 ;
; D ; LC50 ; PHI1b7_MC ; PHI1b9_MC ;
; E ; LC67 ; nWE ; nROE ;
; E ; LC68 ; C7M, nRES, D[5], BankWR_MC, S[2], S[1], S[0] ; RA~96, RA~103, RA~110 ;
; E ; LC79 ; C7M, nRES, D[4], BankWR_MC, S[2], S[1], S[0] ; RA~89, RA~96, RA~103, RA~110 ;
; E ; LC69 ; Addr[20], ASel, Addr[9] ; RA[9] ;
; E ; LC77 ; IOBank0, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ;
; E ; LC73 ; IOBank0, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ;
; E ; LC75 ; IOBank0, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2] ; RA[2] ;
; E ; LC80 ; IOBank0, Bank[0], nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0] ; RA[0] ;
; E ; LC72 ; Addr[21], ASel, Addr[10] ; RA[10] ;
; F ; LC89 ; PHI1b0_MC ; PHI1b2_MC ;
; F ; LC95 ; PHI1b2_MC ; PHI1b4_MC ;
; F ; LC92 ; C7M, nRES, D[7], BankWR_MC, S[2], S[1], S[0] ; RA~110 ;
; F ; LC85 ; IOBank0, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ;
; F ; LC88 ; IOBank0, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ;
; F ; LC86 ; IOBank0, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ;
; F ; LC83 ; IOBank0, Bank[1], Bank[0], nIOSTRB, Addr[12], ASel, nIOSEL, Addr[1] ; RA[1] ;
; F ; LC93 ; RASr, RASf ; nRAS ;
; F ; LC84 ; C7M, nRES, nIOSEL, S[0], S[2], S[1] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, IOBank0 ;
; F ; LC91 ; Addr[19], ASel, Addr[8] ; RA[8] ;
; F ; LC82 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~46 ;
; F ; LC94 ; D[7] ; RD[7] ;
; F ; LC90 ; PHI1b4_MC ; PHI1b6_MC ;
; F ; LC96 ; PHI1b3_MC ; PHI1b5_MC ;
; F ; LC87 ; PHI1b1_MC ; PHI1b3_MC ;
; G ; LC105 ; D[3] ; RD[3] ;
; G ; LC101 ; D[4] ; RD[4] ;
; G ; LC97 ; D[5] ; RD[5] ;
; G ; LC98 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; ASel, RASr, RAMSELreg, CASr, RASf, comb~51, comb~55 ;
; G ; LC104 ; nDEVSEL, nIOSEL, nIOSTRB, nWE ; nRWE ;
; G ; LC112 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19] ;
; G ; LC111 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[11], Addr[8], Addr[9], Addr[10], Addr[12], Addr[13], Addr[14], Addr[15] ;
; G ; LC106 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[7], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6] ;
; G ; LC110 ; C7M, nRES, D[6], BankWR_MC, S[2], S[1], S[0] ; RA~103, RA~110 ;
; G ; LC99 ; D[6] ; RD[6] ;
; G ; LC102 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[2], S[1], S[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~70, RA~75, RA~81, RA~82, RA~89, RA~96, RA~103, RA~110 ;
; G ; LC107 ; D[2] ; RD[2] ;
; G ; LC109 ; D[1] ; RD[1] ;
; G ; LC103 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ;
; H ; LC120 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
; H ; LC115 ; D[0] ; RD[0] ;
; H ; LC116 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC127 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC124 ; PHI1b5_MC ; PHI1b7_MC ;
; H ; LC126 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[2], S[1] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ;
; H ; LC114 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ;
; H ; LC122 ; nRES, RAMSEL_MC, S[2], S[1], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], C7M_2 ; comb~48 ;
; H ; LC119 ; C7M, nRES, S[1], S[0], S[2], RAMSEL_MC, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0] ; comb~51, comb~55 ;
; H ; LC128 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC125 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC117 ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~46 ;
; H ; LC113 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[2]~83, Addr[16], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], RA~68, Addr[22], Addr[14], Addr[15] ;
; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[2], S[1], S[0], Addr[0], RAMSELreg ; Dout[0]~71, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~73 ;
; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[2], S[1], S[0], Addr[1], Addr[0], RAMSELreg ; Dout[1]~77, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~120 ;
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[2], S[1], S[0], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[4]~95, Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~87 ;
; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[2], S[1], S[0], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[5]~101, Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~94 ;
; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[2], S[1], S[0], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[2]~83, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~79 ;
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[2], S[1], S[0], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[3]~89, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~80 ;
; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[5]~101, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~79 ;
; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[4]~95, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~120 ;
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[6]~107, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[14], Addr[15], RA~80 ;
; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[3]~89, Addr[16], Addr[17], Addr[18], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~73 ;
; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[2], S[1], S[0], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[6]~107, Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~101 ;
; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[1]~77, Addr[16], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], RA~65, Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15] ;
; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[0]~71, Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], RA~62, Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15] ;
; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[2], S[1], S[0], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[7]~113, Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~108 ;
; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[7]~113, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[15], RA~87 ;
; B ; LC30 ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[1], S[0], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[4]~95, Addr[20], RA~65, Addr[21], Addr[22] ;
; B ; LC23 ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[1], S[0], Addr[22], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[6]~107, Addr[22], comb~39, comb~43 ;
; B ; LC31 ; C7M, nRES, D[0], AddrHWR_MC, S[2], S[1], S[0], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[0]~71, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~94 ;
; B ; LC20 ; C7M, nRES, D[3], BankWR_MC, S[2], S[1], S[0] ; RA~80, RA~87, RA~94, RA~101, RA~108 ;
; B ; LC24 ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[1], S[0], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[5]~101, Addr[21], RA~68, Addr[22] ;
; B ; LC26 ; C7M, nRES, D[5], BankWR_MC, S[2], S[1], S[0] ; RA~94, RA~101, RA~108 ;
; B ; LC25 ; C7M, nRES, D[4], BankWR_MC, S[2], S[1], S[0] ; RA~87, RA~94, RA~101, RA~108 ;
; B ; LC21 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[1], S[0], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[3]~89, Addr[19], RA~62, Addr[20], Addr[21], Addr[22] ;
; B ; LC32 ; C7M, nRES, D[2], BankWR_MC, S[2], S[1], S[0] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108 ;
; B ; LC29 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[1], S[0], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[2]~83, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~108 ;
; B ; LC27 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[1], S[0], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[1]~77, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~101 ;
; B ; LC28 ; C7M, nRES, D[1], BankWR_MC, S[2], S[1], S[0] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
; B ; LC19 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~34 ;
; B ; LC22 ; C7M, nRES, D[0], BankWR_MC, S[2], S[1], S[0] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
; B ; LC18 ; C7M, nRES, D[6], BankWR_MC, S[2], S[1], S[0] ; RA~101, RA~108 ;
; B ; LC17 ; ; nINH ;
; C ; LC38 ; RD[4], nDEVSEL, A[0], A[1], A[2], A[3], Addr[12], Addr[20], Addr[4] ; D[4] ;
; C ; LC43 ; RD[6], nDEVSEL, A[0], A[1], A[2], A[3], Addr[14], Addr[22], Addr[6] ; D[6] ;
; C ; LC45 ; RD[7], nDEVSEL, A[1], A[2], A[3], A[0], Addr[15], Addr[7] ; D[7] ;
; C ; LC36 ; PHI1in ; PHI1b1_MC ;
; C ; LC34 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; ASel, RASr, RAMSELreg, CASr, RASf, comb~39, comb~43 ;
; C ; LC35 ; C7M_2 ; C7Mout ;
; C ; LC40 ; RD[5], nDEVSEL, A[0], A[1], A[2], A[3], Addr[13], Addr[21], Addr[5] ; D[5] ;
; C ; LC37 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, PHI1out, S[0], S[1], S[2] ;
; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ;
; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ;
; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ;
; D ; LC53 ; Addr[22], CASf, RAMSEL_MC, CASr ; nCAS0 ;
; D ; LC51 ; Addr[22], CASf, RAMSEL_MC, CASr ; nCAS1 ;
; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ;
; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ;
; D ; LC56 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ;
; E ; LC74 ; PHI1b5_MC ; PHI1b7_MC ;
; E ; LC68 ; PHI1b6_MC ; PHI1b8_MC ;
; E ; LC79 ; PHI1b7_MC ; PHI1b9_MC ;
; E ; LC65 ; PHI1b2_MC ; PHI1b4_MC ;
; E ; LC69 ; Addr[20], ASel, Addr[9] ; RA[9] ;
; E ; LC72 ; Addr[21], ASel, Addr[10] ; RA[10] ;
; E ; LC67 ; nWE ; nROE ;
; E ; LC66 ; PHI1b0_MC ; PHI1b2_MC ;
; E ; LC70 ; PHI1b1_MC ; PHI1b3_MC ;
; E ; LC76 ; PHI1b3_MC ; PHI1b5_MC ;
; E ; LC80 ; Bank[0], FullIOEN, nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0] ; RA[0] ;
; E ; LC75 ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2] ; RA[2] ;
; E ; LC73 ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ;
; E ; LC77 ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ;
; E ; LC78 ; PHI1b4_MC ; PHI1b6_MC ;
; F ; LC86 ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ;
; F ; LC88 ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ;
; F ; LC85 ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ;
; F ; LC91 ; Addr[19], ASel, Addr[8] ; RA[8] ;
; F ; LC93 ; RASr, RASf ; nRAS ;
; F ; LC94 ; D[7] ; RD[7] ;
; F ; LC83 ; Addr[12], ASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0] ; RA[1] ;
; G ; LC109 ; D[1] ; RD[1] ;
; G ; LC102 ; C7M, nRES, D[7], BankWR_MC, S[2], S[1], S[0] ; RA~108 ;
; G ; LC110 ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~34 ;
; G ; LC103 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[2], S[1], S[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
; G ; LC100 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7] ;
; G ; LC98 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15] ;
; G ; LC107 ; D[2] ; RD[2] ;
; G ; LC104 ; nDEVSEL, nIOSEL, nIOSTRB, nWE ; nRWE ;
; G ; LC99 ; D[6] ; RD[6] ;
; G ; LC97 ; D[5] ; RD[5] ;
; G ; LC101 ; D[4] ; RD[4] ;
; G ; LC105 ; D[3] ; RD[3] ;
; G ; LC108 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22] ;
; G ; LC112 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
; G ; LC106 ; C7M, nRES, nIOSEL, S[0], S[2], S[1] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, FullIOEN ;
; G ; LC111 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ;
; H ; LC127 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC125 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC128 ; nRES, S[2], S[1], S[0], nWE, C7M_2 ; comb~39, comb~43 ;
; H ; LC117 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Bank[0], Addr[8], Addr[9], Bank[1], Addr[17], Addr[18], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Bank[5], Addr[21], Addr[22], Bank[6], Addr[14], Addr[15], Bank[7], FullIOEN ;
; H ; LC115 ; D[0] ; RD[0] ;
; H ; LC119 ; C7M, nRES, S[1], S[0], S[2], RAMSEL_MC, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0] ; comb~39, comb~43 ;
; H ; LC116 ; nRES, RAMSEL_MC, S[2], S[1], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], C7M_2 ; comb~36 ;
; H ; LC120 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1] ; comb~36 ;
; H ; LC114 ; C7M, nRES, RAMSEL_MC, S[2], S[1] ; RA~62, RA~65, RA~68, RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
; H ; LC124 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC123 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; H ; LC126 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC118 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; H ; LC113 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[2], S[1] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Bank[0], Addr[8], Addr[9], Bank[1], Addr[17], Addr[18], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Bank[5], Addr[21], Addr[22], Bank[6], Addr[14], Addr[15], Bank[7], FullIOEN ;
; H ; LC121 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Bank[0], Addr[8], Addr[9], Bank[1], Addr[17], Addr[18], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Bank[5], Addr[21], Addr[22], Bank[6], Addr[14], Addr[15], Bank[7], FullIOEN ;
; H ; LC122 ; C7M, nRES, S[2], S[1], S[0], RAMSEL_MC, RAMSELreg ; RAMSELreg, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15] ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------+
@ -703,8 +700,8 @@ Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM"
Info: Quartus II 32-bit Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 287 megabytes
Info: Processing ended: Mon Sep 02 01:41:31 2019
Info: Elapsed time: 00:00:05
Info: Processing ended: Mon Sep 02 20:55:54 2019
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:04

2
cpld/output_files/GR8RAM.fit.summary
View File

@ -1,4 +1,4 @@
Fitter Status : Successful - Mon Sep 02 01:41:31 2019
Fitter Status : Successful - Mon Sep 02 20:55:54 2019
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM

16
cpld/output_files/GR8RAM.flow.rpt
View File

@ -1,5 +1,5 @@
Flow report for GR8RAM
Mon Sep 02 01:41:42 2019
Mon Sep 02 20:56:05 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -40,7 +40,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------+-------------------------------------------------+
; Flow Status ; Successful - Mon Sep 02 01:41:35 2019 ;
; Flow Status ; Successful - Mon Sep 02 20:55:58 2019 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
@ -57,7 +57,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/02/2019 01:41:21 ;
; Start date & time ; 09/02/2019 20:55:44 ;
; Main task ; Compilation ;
; Revision Name ; GR8RAM ;
+-------------------+---------------------+
@ -71,7 +71,7 @@ applicable agreement for further details.
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ;
; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 52238299365.156740288102732 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 52238299365.156747214401988 ; -- ; -- ; -- ;
; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ;
; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ;
; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ;
@ -98,10 +98,10 @@ applicable agreement for further details.
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:08 ; 1.0 ; 303 MB ; 00:00:08 ;
; Fitter ; 00:00:05 ; 1.0 ; 287 MB ; 00:00:04 ;
; Assembler ; 00:00:03 ; 1.0 ; 275 MB ; 00:00:03 ;
; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 263 MB ; 00:00:05 ;
; Total ; 00:00:21 ; -- ; -- ; 00:00:20 ;
; Fitter ; 00:00:04 ; 1.0 ; 287 MB ; 00:00:04 ;
; Assembler ; 00:00:03 ; 1.0 ; 275 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:06 ; 1.0 ; 263 MB ; 00:00:05 ;
; Total ; 00:00:21 ; -- ; -- ; 00:00:19 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+

2
cpld/output_files/GR8RAM.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="94a5ca8ad1222b1b1963"/>
<hash md5_digest_80b="4117e9f02d3732265fc4"/>
</project>
<file_info>
<file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>

18
cpld/output_files/GR8RAM.map.rpt
View File

@ -1,5 +1,5 @@
Analysis & Synthesis report for GR8RAM
Mon Sep 02 01:41:25 2019
Mon Sep 02 20:55:48 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -42,7 +42,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Sep 02 01:41:25 2019 ;
; Analysis & Synthesis Status ; Successful - Mon Sep 02 20:55:48 2019 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
@ -156,8 +156,8 @@ applicable agreement for further details.
; I/O pins ; 63 ;
; Maximum fan-out node ; nRES ;
; Maximum fan-out ; 50 ;
; Total fan-out ; 962 ;
; Average fan-out ; 5.83 ;
; Total fan-out ; 971 ;
; Average fan-out ; 5.88 ;
+----------------------+----------------------+
@ -260,16 +260,16 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Mon Sep 02 01:41:17 2019
Info: Processing started: Mon Sep 02 20:55:40 2019
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
Info (12023): Found entity 1: GR8RAM
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(135): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (23)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(136): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(160): truncated value with size 32 to match size of target (23)
Info (19000): Inferred 1 megafunctions from design logic
Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0"
Info (278001): Inferred 2 megafunctions from design logic
@ -323,7 +323,7 @@ Info (21057): Implemented 165 device resources after synthesis - the final resou
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 14 warnings
Info: Peak virtual memory: 303 megabytes
Info: Processing ended: Mon Sep 02 01:41:25 2019
Info: Processing ended: Mon Sep 02 20:55:48 2019
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:08

6
cpld/output_files/GR8RAM.map.smsg
View File

@ -1,3 +1,3 @@
Warning (10273): Verilog HDL warning at GR8RAM.v(40): extended using "x" or "z"
Warning (10273): Verilog HDL warning at GR8RAM.v(48): extended using "x" or "z"
Warning (10268): Verilog HDL information at GR8RAM.v(175): always construct contains both blocking and non-blocking assignments
Warning (10273): Verilog HDL warning at GR8RAM.v(41): extended using "x" or "z"
Warning (10273): Verilog HDL warning at GR8RAM.v(49): extended using "x" or "z"
Warning (10268): Verilog HDL information at GR8RAM.v(176): always construct contains both blocking and non-blocking assignments

2
cpld/output_files/GR8RAM.map.summary
View File

@ -1,4 +1,4 @@
Analysis & Synthesis Status : Successful - Mon Sep 02 01:41:25 2019
Analysis & Synthesis Status : Successful - Mon Sep 02 20:55:48 2019
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM

BIN
cpld/output_files/GR8RAM.pof
View File

Binary file not shown.

76
cpld/output_files/GR8RAM.sta.rpt
View File

@ -1,5 +1,5 @@
TimeQuest Timing Analyzer report for GR8RAM
Mon Sep 02 01:41:42 2019
Mon Sep 02 20:56:05 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -97,7 +97,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+---------+---------------+
; C7M ; -47.000 ; -1763.000 ;
; C7M ; -47.000 ; -1816.000 ;
; C7M_2 ; -27.500 ; -33.000 ;
+-------+---------+---------------+
@ -152,10 +152,13 @@ No paths to report.
; -47.000 ; REGEN ; Addr[19] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[20] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[12] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[13] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[21] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[22] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
@ -236,9 +239,6 @@ No paths to report.
; -25.000 ; Addr[10] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[9] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[8] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[7] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[6] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[5] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
+---------+-----------+-----------+--------------+-------------+--------------+------------+------------+
@ -314,10 +314,13 @@ No paths to report.
; 5.000 ; Addr[19] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[3] ; Addr[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[4] ; Addr[4] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[20] ; Addr[20] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[12] ; Addr[12] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[13] ; Addr[13] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[21] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[5] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[6] ; Addr[6] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[22] ; Addr[22] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[14] ; Addr[14] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
@ -349,6 +352,10 @@ No paths to report.
; 5.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[2] ; FullIOEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; FullIOEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; FullIOEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; REGEN ; FullIOEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
@ -378,13 +385,6 @@ No paths to report.
; 18.000 ; RAMSELreg ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[15] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[14] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[13] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[12] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[11] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[10] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
@ -479,8 +479,8 @@ No paths to report.
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CASr ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CSDBEN ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CSDBEN ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IOBank0 ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IOBank0 ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; FullIOEN ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; FullIOEN ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IOROMEN ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IOROMEN ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI0seen ;
@ -560,11 +560,11 @@ No paths to report.
+-----------+------------+---------+---------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+---------+---------+------------+-----------------+
; A[*] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[0] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[1] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[2] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[3] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[*] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[0] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[1] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[2] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[3] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[4] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[5] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[6] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
@ -572,20 +572,20 @@ No paths to report.
; A[8] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[9] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[10] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; D[*] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; D[0] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; D[1] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; D[2] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; D[3] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; D[4] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; D[5] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; D[6] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; D[7] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; D[*] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; D[0] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; D[1] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; D[2] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; D[3] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; D[4] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; D[5] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; D[6] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; D[7] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; PHI1in ; C7M ; -12.000 ; -12.000 ; Rise ; C7M ;
; nDEVSEL ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; nDEVSEL ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; nIOSEL ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; nIOSTRB ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; nWE ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; nWE ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[*] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ;
; A[0] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ;
; A[1] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ;
@ -1041,7 +1041,7 @@ No paths to report.
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C7M ; C7M ; 706 ; 0 ; 0 ; 0 ;
; C7M ; C7M ; 736 ; 0 ; 0 ; 0 ;
; C7M ; C7M_2 ; 0 ; 0 ; 14 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -1052,7 +1052,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C7M ; C7M ; 706 ; 0 ; 0 ; 0 ;
; C7M ; C7M ; 736 ; 0 ; 0 ; 0 ;
; C7M ; C7M_2 ; 0 ; 0 ; 14 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -1078,9 +1078,9 @@ No dedicated SERDES Receiver circuitry present in device or used in design
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 34 ; 34 ;
; Unconstrained Input Port Paths ; 428 ; 428 ;
; Unconstrained Input Port Paths ; 449 ; 449 ;
; Unconstrained Output Ports ; 35 ; 35 ;
; Unconstrained Output Port Paths ; 264 ; 264 ;
; Unconstrained Output Port Paths ; 267 ; 267 ;
+---------------------------------+-------+------+
@ -1090,7 +1090,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Mon Sep 02 01:41:37 2019
Info: Processing started: Mon Sep 02 20:55:59 2019
Info: Command: quartus_sta GR8RAM -c GR8RAM
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
@ -1107,7 +1107,7 @@ Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -47.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -47.000 -1763.000 C7M
Info (332119): -47.000 -1816.000 C7M
Info (332119): -27.500 -33.000 C7M_2
Info (332146): Worst-case hold slack is -1.500
Info (332119): Slack End Point TNS Clock
@ -1126,8 +1126,8 @@ Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 263 megabytes
Info: Processing ended: Mon Sep 02 01:41:42 2019
Info: Elapsed time: 00:00:05
Info: Processing ended: Mon Sep 02 20:56:05 2019
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05

2
cpld/output_files/GR8RAM.sta.summary
View File

@ -4,7 +4,7 @@ TimeQuest Timing Analyzer Summary
Type : Setup 'C7M'
Slack : -47.000
TNS : -1763.000
TNS : -1816.000
Type : Setup 'C7M_2'
Slack : -27.500