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GR8RAM
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Made AddrH high bit variable with mode input

This commit is contained in:
Zane Kaminski 2019-09-07 21:16:23 -04:00
parent b0a001aa58
commit 2382fdfda6
42 changed files with 506 additions and 493 deletions
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3
cpld/GR8RAM.qsf
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@ -160,4 +160,5 @@ set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b9_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI0seen
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1reg
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b0_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b0_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to IOROMEN

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cpld/GR8RAM.v
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@ -1,11 +1,11 @@
module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
A, RA, nWE, D, RD, nINH,
nDEVSEL, nIOSEL, nIOSTRB,
module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
A, RA, nWE, D, RD,
nDEVSEL, nIOSEL, nIOSTRB, nINH,
nRAS, nCAS0, nCAS1, nRCS, nROE, nRWE);
/* Clock, Reset, Mode */
input C7M, C7M_2, Q3, PHI0in, PHI1in; // Clock inputs
input nRES, MODE; // Reset, mode
input nRES, nMode; // Reset, mode
/* PHI1 Delay */
wire [8:0] PHI1b;
@ -32,6 +32,20 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
(~ASel & nIOSEL & nIOSTRB) ? Addr[18:11] :
(ASel & nIOSEL & nIOSTRB) ? Addr[7:0] : 8'h00;
/* Select Signals */
wire BankSELA = A[3:0]==4'hF;
wire SetSELA = A[3:0]==4'hE;
wire RAMSELA = A[3:0]==4'h3;
wire AddrHSELA = A[3:0]==4'h2;
wire AddrMSELA = A[3:0]==4'h1;
wire AddrLSELA = A[3:0]==4'h0;
LCELL BankWR_MC (.in(BankSELA & ~nWE & ~nDEVSEL & REGEN), .out(BankWR)); wire BankWR;
wire SetWR = SetSELA & ~nWE & ~nDEVSEL & REGEN;
LCELL RAMSEL_MC (.in(RAMSELA & ~nDEVSEL & REGEN), .out(RAMSEL)); wire RAMSEL;
LCELL AddrHWR_MC (.in(AddrHSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrHWR)); wire AddrHWR;
LCELL AddrMWR_MC (.in(AddrMSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrMWR)); wire AddrMWR;
LCELL AddrLWR_MC (.in(AddrLSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrLWR)); wire AddrLWR;
/* Data Bus Routing */
// DRAM/ROM data bus
wire RDOE = CSDBEN & ~nWE;
@ -40,7 +54,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
wire DOE = CSDBEN & nWE &
((~nDEVSEL & REGEN) | ~nIOSEL | (~nIOSTRB & IOROMEN));
wire [7:0] Dout = (nDEVSEL | RAMSELA) ? RD[7:0] :
AddrHSELA ? {1'b1, Addr[22:16]} :
AddrHSELA ? {nMode, Addr[22:16]} :
AddrMSELA ? Addr[15:8] :
AddrLSELA ? Addr[7:0] : 8'h00;
inout [7:0] D = DOE ? Dout : 8'bZ;
@ -78,20 +92,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
reg [2:0] S = 3'h0; // State counter
reg [3:0] Ref = 4'h0; // Refresh skip counter
/* Select Signals */
wire BankSELA = A[3:0]==4'hF;
wire SetSELA = A[3:0]==4'hE;
wire RAMSELA = A[3:0]==4'h3;
wire AddrHSELA = A[3:0]==4'h2;
wire AddrMSELA = A[3:0]==4'h1;
wire AddrLSELA = A[3:0]==4'h0;
LCELL BankWR_MC (.in(BankSELA & ~nWE & ~nDEVSEL & REGEN), .out(BankWR)); wire BankWR;
wire SetWR = SetSELA & ~nWE & ~nDEVSEL & REGEN;
LCELL RAMSEL_MC (.in(RAMSELA & ~nDEVSEL & REGEN), .out(RAMSEL)); wire RAMSEL;
LCELL AddrHWR_MC (.in(AddrHSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrHWR)); wire AddrHWR;
LCELL AddrMWR_MC (.in(AddrMSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrMWR)); wire AddrMWR;
LCELL AddrLWR_MC (.in(AddrLSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrLWR)); wire AddrLWR;
/* Misc. */
reg REGEN = 0; // Register enable
reg IOROMEN = 0; // IOSTRB ROM enable

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cpld/db/GR8RAM.asm.qmsg
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@ -1,5 +1,5 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567734309571 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567734309571 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 21:45:09 2019 " "Processing started: Thu Sep 05 21:45:09 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567734309571 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567734309571 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567734309571 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567734311414 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567734311820 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 21:45:11 2019 " "Processing ended: Thu Sep 05 21:45:11 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567734311820 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567734311820 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567734311820 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567734311820 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567905339785 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567905339800 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 21:15:39 2019 " "Processing started: Sat Sep 07 21:15:39 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567905339800 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567905339800 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567905339800 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567905341676 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567905342082 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 21:15:42 2019 " "Processing ended: Sat Sep 07 21:15:42 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567905342082 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567905342082 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567905342082 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567905342082 ""}

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cpld/db/GR8RAM.db_info
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@ -1,3 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Fri Sep 06 16:48:57 2019
Creation_Time = Sat Sep 07 21:14:51 2019

7
cpld/db/GR8RAM.fit.qmsg
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@ -1,3 +1,4 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567734307336 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567734307352 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567734307977 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 21:45:07 2019 " "Processing ended: Thu Sep 05 21:45:07 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567734307977 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567734307977 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567734307977 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567734307977 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567905337363 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567905337394 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "MODE " "Node \"MODE\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "MODE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1567905337613 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1567905337613 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567905338144 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 21:15:38 2019 " "Processing ended: Sat Sep 07 21:15:38 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567905338144 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567905338144 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567905338144 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567905338144 ""}

12
cpld/db/GR8RAM.hier_info
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@ -21,7 +21,7 @@ PHI0in => ~NO_FANOUT~
PHI1in => comb.IN0
PHI1in => PHI1b0_MC.DATAIN
nRES => always0.IN0
MODE => ~NO_FANOUT~
nMode => comb.DATAB
A[0] => Equal0.IN7
A[0] => Equal1.IN7
A[0] => Equal2.IN7
@ -75,11 +75,11 @@ RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[10] <= RA.DB_MAX_OUTPUT_PORT_TYPE
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN1
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => CASf.IN1
D[0] <> D[0]
D[1] <> D[1]
@ -97,7 +97,6 @@ RD[4] <> RD[4]
RD[5] <> RD[5]
RD[6] <> RD[6]
RD[7] <> RD[7]
nINH <= nINH.DB_MAX_OUTPUT_PORT_TYPE
nDEVSEL => comb.IN0
nDEVSEL => comb.IN0
nDEVSEL => comb.IN0
@ -114,6 +113,7 @@ nIOSTRB => RA.IN0
nIOSTRB => RA.IN1
nIOSTRB => RA.IN1
nIOSTRB => comb.IN1
nINH <= nINH.DB_MAX_OUTPUT_PORT_TYPE
nRAS <= comb.DB_MAX_OUTPUT_PORT_TYPE
nCAS0 <= comb.DB_MAX_OUTPUT_PORT_TYPE
nCAS1 <= comb.DB_MAX_OUTPUT_PORT_TYPE

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cpld/db/GR8RAM.map.qmsg
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@ -1,40 +1,40 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567734290759 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567734290759 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 21:44:50 2019 " "Processing started: Thu Sep 05 21:44:50 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567734290759 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567734290759 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567734290759 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567734295337 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(38) " "Verilog HDL warning at GR8RAM.v(38): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567734295555 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(46) " "Verilog HDL warning at GR8RAM.v(46): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 46 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567734295555 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(194) " "Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 194 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567734295555 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567734295555 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567734295555 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567734296071 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567734296071 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(126) " "Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567734296071 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567734296071 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(163) " "Verilog HDL assignment warning at GR8RAM.v(163): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567734296071 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(168) " "Verilog HDL assignment warning at GR8RAM.v(168): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567734296071 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (7)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567734296071 "|GR8RAM"}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734296337 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567734296337 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734296352 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 168 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734296352 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 163 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734296352 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734296352 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567734296352 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734296946 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734296946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734296946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734296946 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567734296946 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734297243 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297243 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567734297243 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297509 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297790 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297805 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298024 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298243 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298259 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734298430 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add5 " "Instantiated megafunction \"lpm_add_sub:Add5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 7 " "Parameter \"LPM_WIDTH\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298430 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567734298430 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 250 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298430 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298446 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 191 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298477 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 192 10 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298493 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|altshift:result_ext_latency_ffs lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298509 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567734298821 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567734298821 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567734299102 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567734299102 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567734299102 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567734299649 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567734299680 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567734299680 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567734299680 ""} { "Info" "ICUT_CUT_TM_MCELLS" "103 " "Implemented 103 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567734299680 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567734299680 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567734299680 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567734300149 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "304 " "Peak virtual memory: 304 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567734300258 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 21:45:00 2019 " "Processing ended: Thu Sep 05 21:45:00 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567734300258 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567734300258 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567734300258 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567734300258 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567905323534 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567905323534 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 21:15:23 2019 " "Processing started: Sat Sep 07 21:15:23 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567905323534 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567905323534 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567905323534 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567905327409 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567905327550 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567905327550 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(194) " "Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 194 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567905327550 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567905327550 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567905327550 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567905328081 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567905328081 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(126) " "Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567905328081 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567905328081 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(163) " "Verilog HDL assignment warning at GR8RAM.v(163): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567905328081 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(168) " "Verilog HDL assignment warning at GR8RAM.v(168): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567905328081 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (7)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567905328081 "|GR8RAM"}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905328487 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567905328487 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905328487 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 168 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905328487 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 163 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905328487 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905328487 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567905328487 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905329066 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329066 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329066 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329066 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567905329066 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905329394 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329394 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329394 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329394 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329394 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567905329394 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329644 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329847 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329862 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330112 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330378 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330378 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905330566 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add5 " "Instantiated megafunction \"lpm_add_sub:Add5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 7 " "Parameter \"LPM_WIDTH\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330566 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330566 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330566 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330566 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567905330566 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 250 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330581 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330613 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 191 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330628 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 192 10 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330644 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|altshift:result_ext_latency_ffs lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330675 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567905330972 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567905330972 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567905331238 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567905331238 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567905331238 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "7 " "Design contains 7 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567905331613 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567905331628 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567905331628 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567905331628 ""} { "Info" "ICUT_CUT_TM_MCELLS" "103 " "Implemented 103 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567905331628 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567905331628 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567905331628 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567905331925 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "304 " "Peak virtual memory: 304 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567905332050 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 21:15:32 2019 " "Processing ended: Sat Sep 07 21:15:32 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567905332050 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567905332050 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567905332050 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567905332050 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567734315117 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567734315117 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 21:45:12 2019 " "Processing started: Thu Sep 05 21:45:12 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567734315117 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567734315117 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567734315117 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567734315211 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567734317164 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567734317180 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567734317195 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567734317242 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567734317320 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567734317320 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317320 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317320 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317320 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567734317336 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567734317430 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317445 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317445 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -1992.500 C7M " " -47.500 -1992.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317445 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317445 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567734317445 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317461 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317461 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317461 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317461 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567734317461 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567734317477 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567734317492 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -450.000 C7M " " -4.500 -450.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317508 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567734317508 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567734317633 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567734317664 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567734317664 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "259 " "Peak virtual memory: 259 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567734317789 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 21:45:17 2019 " "Processing ended: Thu Sep 05 21:45:17 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567734317789 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567734317789 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567734317789 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567734317789 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567905345566 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567905345582 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 21:15:43 2019 " "Processing started: Sat Sep 07 21:15:43 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567905345582 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567905345582 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567905345582 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567905345723 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567905347942 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567905347973 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567905347973 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567905348004 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567905348098 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567905348098 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348098 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348098 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348098 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567905348113 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567905348238 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348317 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348317 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -1979.500 C7M " " -47.500 -1979.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348317 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348317 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567905348317 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348332 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348332 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348332 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348332 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567905348332 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567905348348 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567905348363 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -450.000 C7M " " -4.500 -450.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348379 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567905348379 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567905348488 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567905348535 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567905348535 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "259 " "Peak virtual memory: 259 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567905348676 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 21:15:48 2019 " "Processing ended: Sat Sep 07 21:15:48 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567905348676 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567905348676 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567905348676 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567905348676 ""}

BIN
cpld/db/GR8RAM.sta.rdb
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Binary file not shown.

BIN
cpld/db/GR8RAM.sta_cmp.15_slow.tdb
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Binary file not shown.

6
cpld/db/GR8RAM.tmw_info Executable file
View File

@ -0,0 +1,6 @@
start_full_compilation:s:00:00:28
start_analysis_synthesis:s:00:00:11-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:06-start_full_compilation
start_assembler:s:00:00:04-start_full_compilation
start_timing_analyzer:s:00:00:07-start_full_compilation

12
cpld/output_files/GR8RAM.asm.rpt
View File

@ -1,5 +1,5 @@
Assembler report for GR8RAM
Thu Sep 05 21:45:11 2019
Sat Sep 07 21:15:42 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Thu Sep 05 21:45:11 2019 ;
; Assembler Status ; Successful - Sat Sep 07 21:15:42 2019 ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX7000S ;
@ -89,7 +89,7 @@ applicable agreement for further details.
+----------------+-------------------------------------------------------+
; Device ; EPM7128SLC84-15 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x0017D4EA ;
; Checksum ; 0x0017B9A5 ;
+----------------+-------------------------------------------------------+
@ -99,13 +99,13 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Sep 05 21:45:09 2019
Info: Processing started: Sat Sep 07 21:15:39 2019
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 277 megabytes
Info: Processing ended: Thu Sep 05 21:45:11 2019
Info: Elapsed time: 00:00:02
Info: Processing ended: Sat Sep 07 21:15:42 2019
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02

2
cpld/output_files/GR8RAM.done
View File

@ -1 +1 @@
Thu Sep 05 21:45:18 2019
Sat Sep 07 21:15:49 2019

241
cpld/output_files/GR8RAM.fit.rpt
View File

@ -1,5 +1,5 @@
Fitter report for GR8RAM
Thu Sep 05 21:45:07 2019
Sat Sep 07 21:15:37 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -54,7 +54,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Thu Sep 05 21:45:07 2019 ;
; Fitter Status ; Successful - Sat Sep 07 21:15:37 2019 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
@ -107,11 +107,11 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; Global signals ; 2 ;
; Shareable expanders ; 1 / 128 ( < 1 % ) ;
; Parallel expanders ; 0 / 120 ( 0 % ) ;
; Cells using turbo bit ; 43 / 128 ( 34 % ) ;
; Cells using turbo bit ; 16 / 128 ( 13 % ) ;
; Maximum fan-out ; 52 ;
; Highest non-global fan-out ; 51 ;
; Total fan-out ; 830 ;
; Average fan-out ; 4.91 ;
; Total fan-out ; 831 ;
; Average fan-out ; 4.92 ;
+------------------------------+--------------------+
@ -138,13 +138,13 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; A[9] ; 10 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
; C7M ; 83 ; -- ; -- ; 50 ; 0 ; yes ; no ; TTL ; User ;
; C7M_2 ; 84 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ;
; MODE ; 44 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ;
; PHI0in ; 8 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
; PHI1in ; 2 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ;
; Q3 ; 6 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
; nDEVSEL ; 21 ; -- ; 2 ; 16 ; 0 ; no ; no ; TTL ; User ;
; nIOSEL ; 74 ; -- ; 8 ; 13 ; 0 ; no ; no ; TTL ; User ;
; nIOSTRB ; 24 ; -- ; 3 ; 12 ; 0 ; no ; no ; TTL ; User ;
; nMode ; 37 ; -- ; 4 ; 1 ; 0 ; no ; no ; TTL ; Fitter ;
; nRES ; 1 ; -- ; -- ; 52 ; 0 ; yes ; no ; TTL ; User ;
; nWE ; 20 ; -- ; 2 ; 10 ; 0 ; no ; no ; TTL ; User ;
+---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
@ -241,14 +241,14 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; 34 ; 33 ; -- ; D[2] ; bidir ; TTL ; ; Y ;
; 35 ; 34 ; -- ; D[1] ; bidir ; TTL ; ; Y ;
; 36 ; 35 ; -- ; D[0] ; bidir ; TTL ; ; Y ;
; 37 ; 36 ; -- ; RESERVED ; ; ; ; ;
; 37 ; 36 ; -- ; nMode ; input ; TTL ; ; N ;
; 38 ; 37 ; -- ; VCCIO ; power ; ; 5.0V ; ;
; 39 ; 38 ; -- ; nCAS0 ; output ; TTL ; ; Y ;
; 40 ; 39 ; -- ; nCAS1 ; output ; TTL ; ; Y ;
; 41 ; 40 ; -- ; nRCS ; output ; TTL ; ; Y ;
; 42 ; 41 ; -- ; GND ; gnd ; ; ; ;
; 43 ; 42 ; -- ; VCCINT ; power ; ; 5.0V ; ;
; 44 ; 43 ; -- ; MODE ; input ; TTL ; ; Y ;
; 44 ; 43 ; -- ; RESERVED ; ; ; ; ;
; 45 ; 44 ; -- ; nROE ; output ; TTL ; ; Y ;
; 46 ; 45 ; -- ; RA[9] ; output ; TTL ; ; Y ;
; 47 ; 46 ; -- ; GND ; gnd ; ; ; ;
@ -345,14 +345,14 @@ Note: User assignments will override these defaults. The user specified values a
; A[1] ; PIN_76 ; 15 ; Clock enable ; no ; -- ; -- ;
; A[2] ; PIN_77 ; 15 ; Clock enable ; no ; -- ; -- ;
; A[3] ; PIN_79 ; 15 ; Clock enable ; no ; -- ; -- ;
; BankWR_MC ; LC102 ; 8 ; Clock enable ; no ; -- ; -- ;
; BankWR_MC ; LC106 ; 8 ; Clock enable ; no ; -- ; -- ;
; C7M ; PIN_83 ; 50 ; Clock ; yes ; On ; -- ;
; C7M_2 ; PIN_84 ; 2 ; Clock ; no ; -- ; -- ;
; PHI1b9_MC ; LC33 ; 5 ; Clock enable ; no ; -- ; -- ;
; REGEN ; LC35 ; 7 ; Clock enable ; no ; -- ; -- ;
; S[0] ; LC122 ; 49 ; Clock enable ; no ; -- ; -- ;
; S[1] ; LC117 ; 49 ; Clock enable ; no ; -- ; -- ;
; S[2] ; LC126 ; 51 ; Clock enable ; no ; -- ; -- ;
; PHI1b9_MC ; LC50 ; 5 ; Clock enable ; no ; -- ; -- ;
; REGEN ; LC41 ; 7 ; Clock enable ; no ; -- ; -- ;
; S[0] ; LC123 ; 49 ; Clock enable ; no ; -- ; -- ;
; S[1] ; LC113 ; 49 ; Clock enable ; no ; -- ; -- ;
; S[2] ; LC127 ; 51 ; Clock enable ; no ; -- ; -- ;
; nDEVSEL ; PIN_21 ; 16 ; Clock enable ; no ; -- ; -- ;
; nIOSEL ; PIN_74 ; 13 ; Clock enable ; no ; -- ; -- ;
; nRES ; PIN_1 ; 52 ; Async. clear ; yes ; On ; -- ;
@ -465,6 +465,7 @@ Note: User assignments will override these defaults. The user specified values a
; A[6] ; 1 ;
; A[5] ; 1 ;
; A[4] ; 1 ;
; nMode ; 1 ;
; ~VCC~0 ; 1 ;
; RA~120 ; 1 ;
; RA~108 ; 1 ;
@ -476,14 +477,14 @@ Note: User assignments will override these defaults. The user specified values a
; RA~73 ; 1 ;
; Bank[7] ; 1 ;
; IncAddrM~9 ; 1 ;
; comb~43 ; 1 ;
; comb~39 ; 1 ;
; comb~38 ; 1 ;
; comb~34 ; 1 ;
; RA~68 ; 1 ;
; RA~65 ; 1 ;
; RA~62 ; 1 ;
; comb~36 ; 1 ;
; comb~31 ; 1 ;
; RASf ; 1 ;
; comb~34 ; 1 ;
; comb~29 ; 1 ;
; RASr ; 1 ;
; PHI1b8_MC ; 1 ;
; PHI1b7_MC ; 1 ;
@ -492,7 +493,7 @@ Note: User assignments will override these defaults. The user specified values a
; PHI1b4_MC ; 1 ;
; PHI1b3_MC ; 1 ;
; PHI1b2_MC ; 1 ;
; comb~30 ; 1 ;
; comb~25 ; 1 ;
; PHI1b1_MC ; 1 ;
; nWE~1 ; 1 ;
; PHI1b0_MC ; 1 ;
@ -504,14 +505,14 @@ Note: User assignments will override these defaults. The user specified values a
; D[2]~28 ; 1 ;
; D[1]~26 ; 1 ;
; D[0]~24 ; 1 ;
; Dout[7]~113 ; 1 ;
; Dout[6]~107 ; 1 ;
; Dout[5]~101 ; 1 ;
; Dout[4]~95 ; 1 ;
; Dout[3]~89 ; 1 ;
; Dout[2]~83 ; 1 ;
; Dout[1]~77 ; 1 ;
; Dout[0]~71 ; 1 ;
; Dout[7]~120 ; 1 ;
; Dout[6]~114 ; 1 ;
; Dout[5]~108 ; 1 ;
; Dout[4]~102 ; 1 ;
; Dout[3]~96 ; 1 ;
; Dout[2]~90 ; 1 ;
; Dout[1]~84 ; 1 ;
; Dout[0]~78 ; 1 ;
+-------------------------------+---------+
@ -521,15 +522,15 @@ Note: User assignments will override these defaults. The user specified values a
; Other Routing Resource Type ; Usage ;
+-----------------------------+--------------------+
; Output enables ; 2 / 6 ( 33 % ) ;
; PIA buffers ; 219 / 288 ( 76 % ) ;
; PIAs ; 244 / 288 ( 85 % ) ;
; PIA buffers ; 208 / 288 ( 72 % ) ;
; PIAs ; 246 / 288 ( 85 % ) ;
+-----------------------------+--------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 30.50) ; Number of LABs (Total = 8) ;
; LAB External Interconnects (Average = 30.75) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ;
@ -539,8 +540,8 @@ Note: User assignments will override these defaults. The user specified values a
; 15 - 17 ; 0 ;
; 18 - 20 ; 0 ;
; 21 - 23 ; 0 ;
; 24 - 26 ; 1 ;
; 27 - 29 ; 1 ;
; 24 - 26 ; 0 ;
; 27 - 29 ; 2 ;
; 30 - 32 ; 5 ;
; 33 - 35 ; 1 ;
+-----------------------------------------------+-----------------------------+
@ -559,12 +560,12 @@ Note: User assignments will override these defaults. The user specified values a
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 8 ; 0 ;
; 9 ; 2 ;
; 10 ; 0 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 1 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 2 ;
; 16 ; 2 ;
@ -586,109 +587,109 @@ Note: User assignments will override these defaults. The user specified values a
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[0], S[2], S[1], Addr[2], IncAddrL, Addr[1], Addr[0] ; Dout[2]~83, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~79 ;
; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[0], S[2], S[1], Addr[1], IncAddrL, Addr[0] ; Dout[1]~77, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~120 ;
; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[0], S[2], S[1], Addr[0], IncAddrL ; Dout[0]~71, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~73 ;
; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[7]~113, IncAddrH, Addr[15], RA~87 ;
; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[0], S[2], S[1], Addr[7], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[7]~113, Addr[7], IncAddrM, RA~108 ;
; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[0], S[2], S[1], Addr[6], IncAddrL, Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[6]~107, Addr[6], Addr[7], IncAddrM, RA~101 ;
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[6]~107, Addr[14], IncAddrH, Addr[15], RA~80 ;
; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], IncAddrM ; Dout[0]~71, Addr[8], Addr[9], Addr[10], RA~62, Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15] ;
; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[5]~101, Addr[13], Addr[14], IncAddrH, Addr[15], RA~79 ;
; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[4]~95, Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15], RA~120 ;
; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[3]~89, Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15], RA~73 ;
; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[0], S[2], S[1], Addr[5], IncAddrL, Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[5]~101, Addr[5], Addr[6], Addr[7], IncAddrM, RA~94 ;
; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[2]~83, Addr[10], Addr[11], Addr[12], RA~68, Addr[13], Addr[14], IncAddrH, Addr[15] ;
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[0], S[2], S[1], Addr[4], IncAddrL, Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[4]~95, Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~87 ;
; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], Addr[8], IncAddrM ; Dout[1]~77, Addr[9], Addr[10], Addr[11], Addr[12], RA~65, Addr[13], Addr[14], IncAddrH, Addr[15] ;
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[0], S[2], S[1], Addr[3], IncAddrL, Addr[2], Addr[1], Addr[0] ; Dout[3]~89, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~80 ;
; B ; LC25 ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[0], S[1], Addr[20], IncAddrH, Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[4]~95, Addr[20], RA~65, Addr[21], Addr[22] ;
; B ; LC21 ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[0], S[1], Addr[21], IncAddrH, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[5]~101, Addr[21], RA~68, Addr[22] ;
; B ; LC23 ; C7M, nRES, D[5], BankWR_MC, S[2], S[1], S[0] ; RA~94, RA~101, RA~108 ;
; B ; LC31 ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[0], S[1], Addr[22], IncAddrH, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[6]~107, Addr[22], comb~39, comb~43 ;
; B ; LC29 ; C7M, nRES, D[6], BankWR_MC, S[2], S[1], S[0] ; RA~101, RA~108 ;
; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[0], S[2], S[1], Addr[2], IncAddrL, Addr[1], Addr[0] ; Dout[2]~90, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~79 ;
; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[0], S[2], S[1], Addr[1], IncAddrL, Addr[0] ; Dout[1]~84, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~120 ;
; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[7]~120, IncAddrH, Addr[15], RA~87 ;
; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[0], S[2], S[1], Addr[0], IncAddrL ; Dout[0]~78, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~73 ;
; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[0], S[2], S[1], Addr[7], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[7]~120, Addr[7], IncAddrM, RA~108 ;
; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[0], S[2], S[1], Addr[6], IncAddrL, Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[6]~114, Addr[6], Addr[7], IncAddrM, RA~101 ;
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[6]~114, Addr[14], IncAddrH, Addr[15], RA~80 ;
; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], IncAddrM ; Dout[0]~78, Addr[8], Addr[9], Addr[10], RA~62, Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15] ;
; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[5]~108, Addr[13], Addr[14], IncAddrH, Addr[15], RA~79 ;
; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[4]~102, Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15], RA~120 ;
; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[3]~96, Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15], RA~73 ;
; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[0], S[2], S[1], Addr[5], IncAddrL, Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[5]~108, Addr[5], Addr[6], Addr[7], IncAddrM, RA~94 ;
; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[2]~90, Addr[10], Addr[11], Addr[12], RA~68, Addr[13], Addr[14], IncAddrH, Addr[15] ;
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[0], S[2], S[1], Addr[4], IncAddrL, Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[4]~102, Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~87 ;
; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], Addr[8], IncAddrM ; Dout[1]~84, Addr[9], Addr[10], Addr[11], Addr[12], RA~65, Addr[13], Addr[14], IncAddrH, Addr[15] ;
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[0], S[2], S[1], Addr[3], IncAddrL, Addr[2], Addr[1], Addr[0] ; Dout[3]~96, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~80 ;
; B ; LC22 ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[0], S[1], Addr[21], IncAddrH, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[5]~108, Addr[21], RA~68, Addr[22] ;
; B ; LC30 ; C7M, nRES, D[5], BankWR_MC, S[2], S[1], S[0] ; RA~94, RA~101, RA~108 ;
; B ; LC24 ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[0], S[1], Addr[22], IncAddrH, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[6]~114, Addr[22], comb~34, comb~38 ;
; B ; LC18 ; C7M, nRES, D[6], BankWR_MC, S[2], S[1], S[0] ; RA~101, RA~108 ;
; B ; LC17 ; ; nINH ;
; B ; LC32 ; C7M, nRES, D[7], AddrLWR_MC, Addr[7], S[2], S[0], S[1], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrM, IncAddrM~9 ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, IncAddrM, Addr[15] ;
; B ; LC27 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[0], S[1], Addr[17], IncAddrH, Addr[16] ; Dout[1]~77, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~101 ;
; B ; LC22 ; PHI1b2_MC ; PHI1b4_MC ;
; B ; LC24 ; C7M, nRES, D[2], BankWR_MC, S[2], S[1], S[0] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108 ;
; B ; LC30 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[0], S[1], Addr[18], IncAddrH, Addr[17], Addr[16] ; Dout[2]~83, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~108 ;
; B ; LC26 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[0], S[1], Addr[19], IncAddrH, Addr[18], Addr[17], Addr[16] ; Dout[3]~89, Addr[19], RA~62, Addr[20], Addr[21], Addr[22] ;
; B ; LC28 ; C7M, nRES, D[1], BankWR_MC, S[2], S[1], S[0] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
; B ; LC20 ; C7M, nRES, D[3], BankWR_MC, S[2], S[1], S[0] ; RA~80, RA~87, RA~94, RA~101, RA~108 ;
; B ; LC18 ; C7M, nRES, D[4], BankWR_MC, S[2], S[1], S[0] ; RA~87, RA~94, RA~101, RA~108 ;
; C ; LC34 ; PHI1in ; PHI1b1_MC ;
; B ; LC31 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~29 ;
; B ; LC26 ; C7M, nRES, D[7], AddrLWR_MC, Addr[7], S[2], S[0], S[1], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrM, IncAddrM~9 ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, IncAddrM, Addr[15] ;
; B ; LC32 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[0], S[1], Addr[17], IncAddrH, Addr[16] ; Dout[1]~84, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~101 ;
; B ; LC20 ; C7M, nRES, D[2], BankWR_MC, S[2], S[1], S[0] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108 ;
; B ; LC23 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[0], S[1], Addr[18], IncAddrH, Addr[17], Addr[16] ; Dout[2]~90, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~108 ;
; B ; LC25 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[0], S[1], Addr[19], IncAddrH, Addr[18], Addr[17], Addr[16] ; Dout[3]~96, Addr[19], RA~62, Addr[20], Addr[21], Addr[22] ;
; B ; LC21 ; C7M, nRES, D[3], BankWR_MC, S[2], S[1], S[0] ; RA~80, RA~87, RA~94, RA~101, RA~108 ;
; B ; LC19 ; C7M, nRES, D[1], BankWR_MC, S[2], S[1], S[0] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
; B ; LC27 ; C7M, nRES, D[4], BankWR_MC, S[2], S[1], S[0] ; RA~87, RA~94, RA~101, RA~108 ;
; B ; LC29 ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[0], S[1], Addr[20], IncAddrH, Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[4]~102, Addr[20], RA~65, Addr[21], Addr[22] ;
; C ; LC38 ; RD[4], nDEVSEL, A[0], A[1], A[2], A[3], Addr[12], Addr[20], Addr[4] ; D[4] ;
; C ; LC40 ; RD[5], nDEVSEL, A[0], A[1], A[2], A[3], Addr[13], Addr[21], Addr[5] ; D[5] ;
; C ; LC43 ; RD[6], nDEVSEL, A[0], A[1], A[2], A[3], Addr[14], Addr[22], Addr[6] ; D[6] ;
; C ; LC45 ; RD[7], nDEVSEL, A[1], A[2], A[3], A[0], Addr[15], Addr[7] ; D[7] ;
; C ; LC33 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, S[0], S[1], S[2] ;
; C ; LC42 ; PHI1b1_MC ; PHI1b3_MC ;
; C ; LC35 ; C7M, nRES, nIOSEL, S[2], S[1], S[0] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, FullIOEN ;
; C ; LC36 ; C7M, nRES, D[0], AddrHWR_MC, S[1], S[2], S[0], Addr[16], IncAddrH ; Dout[0]~71, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~94 ;
; C ; LC45 ; RD[7], nDEVSEL, A[0], A[1], A[2], A[3], Addr[15], nMode, Addr[7] ; D[7] ;
; C ; LC41 ; C7M, nRES, nIOSEL, S[2], S[1], S[0] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, FullIOEN ;
; C ; LC35 ; PHI1b1_MC ; PHI1b3_MC ;
; C ; LC47 ; C7M, nRES, D[0], AddrHWR_MC, S[1], S[2], S[0], Addr[16], IncAddrH ; Dout[0]~78, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~94 ;
; C ; LC36 ; C7M, nRES, D[7], BankWR_MC, S[2], S[1], S[0] ; RA~108 ;
; C ; LC34 ; C7M, nRES, D[0], BankWR_MC, S[2], S[1], S[0] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ;
; D ; LC56 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ;
; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ;
; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ;
; D ; LC51 ; Addr[22], CASf, RAMSEL_MC, CASr ; nCAS1 ;
; D ; LC50 ; PHI1b0_MC ; PHI1b2_MC ;
; D ; LC53 ; Addr[22], CASf, RAMSEL_MC, CASr ; nCAS0 ;
; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ;
; E ; LC72 ; Addr[21], ASel, Addr[10] ; RA[10] ;
; D ; LC51 ; Addr[22], CASf, RAMSEL_MC, CASr ; nCAS1 ;
; D ; LC53 ; Addr[22], CASf, RAMSEL_MC, CASr ; nCAS0 ;
; D ; LC52 ; PHI1in ; PHI1b1_MC ;
; D ; LC50 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, S[0], S[1], S[2] ;
; D ; LC54 ; PHI1b0_MC ; PHI1b2_MC ;
; E ; LC67 ; nWE ; nROE ;
; E ; LC70 ; C7M, nRES, D[7], AddrMWR_MC, Addr[15], S[1], S[2], S[0], IncAddrH, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], IncAddrH, Addr[22] ;
; E ; LC74 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~34 ;
; E ; LC78 ; C7M, nRES, D[7], BankWR_MC, S[2], S[1], S[0] ; RA~108 ;
; E ; LC77 ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ;
; E ; LC66 ; PHI1b6_MC ; PHI1b8_MC ;
; E ; LC70 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; E ; LC71 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; E ; LC65 ; PHI1b7_MC ; PHI1b9_MC ;
; E ; LC76 ; C7M, nRES, S[1], S[2], RAMSEL_MC ; RA~62, RA~65, RA~68, RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
; E ; LC69 ; Addr[20], ASel, Addr[9] ; RA[9] ;
; E ; LC72 ; Addr[21], ASel, Addr[10] ; RA[10] ;
; E ; LC80 ; Bank[0], FullIOEN, nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0] ; RA[0] ;
; E ; LC75 ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2] ; RA[2] ;
; E ; LC73 ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ;
; E ; LC77 ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ;
; E ; LC79 ; C7M, nRES, D[0], BankWR_MC, S[2], S[1], S[0] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
; E ; LC69 ; Addr[20], ASel, Addr[9] ; RA[9] ;
; F ; LC87 ; C7M, nRES, S[1], S[2], RAMSEL_MC ; RA~62, RA~65, RA~68, RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
; F ; LC93 ; RASr, RASf ; nRAS ;
; F ; LC84 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; F ; LC95 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; F ; LC91 ; Addr[19], ASel, Addr[8] ; RA[8] ;
; F ; LC85 ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ;
; F ; LC81 ; PHI1b3_MC ; PHI1b5_MC ;
; F ; LC94 ; D[7] ; RD[7] ;
; F ; LC89 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1], IncAddrL ; IncAddrL, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM~9, IncAddrM ;
; F ; LC96 ; C7M, nRES, RAMSEL_MC, S[2], S[1], S[0] ; comb~36 ;
; F ; LC83 ; Addr[12], ASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0] ; RA[1] ;
; F ; LC86 ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ;
; F ; LC87 ; C7M, nRES, RAMSEL_MC, S[2], S[1], S[0] ; comb~31 ;
; F ; LC92 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1], IncAddrL ; IncAddrL, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM~9, IncAddrM ;
; F ; LC91 ; Addr[19], ASel, Addr[8] ; RA[8] ;
; F ; LC93 ; RASr, RASf ; nRAS ;
; F ; LC85 ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ;
; F ; LC88 ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ;
; G ; LC97 ; D[5] ; RD[5] ;
; F ; LC86 ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ;
; F ; LC83 ; Addr[12], ASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0] ; RA[1] ;
; G ; LC112 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ;
; G ; LC109 ; D[1] ; RD[1] ;
; G ; LC105 ; D[3] ; RD[3] ;
; G ; LC101 ; D[4] ; RD[4] ;
; G ; LC97 ; D[5] ; RD[5] ;
; G ; LC99 ; D[6] ; RD[6] ;
; G ; LC108 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15] ;
; G ; LC104 ; nDEVSEL, nIOSEL, nIOSTRB, nWE ; nRWE ;
; G ; LC110 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ;
; G ; LC100 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15] ;
; G ; LC108 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ;
; G ; LC102 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[2], S[1], S[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
; G ; LC106 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ;
; G ; LC107 ; D[2] ; RD[2] ;
; G ; LC98 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[2], S[1], S[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
; G ; LC102 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ;
; G ; LC106 ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~34 ;
; G ; LC98 ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~29 ;
; G ; LC111 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22] ;
; G ; LC103 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; RASr, IncAddrL, ASel, CASr, RASf, comb~39, comb~43 ;
; G ; LC110 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; RASr, IncAddrL, ASel, CASr, RASf, comb~34, comb~38 ;
; H ; LC123 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[2], S[1], S[0] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, IncAddrL, lpm_counter:Ref_rtl_0|dffs[2], Addr[8], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Bank[0], Addr[16], Addr[2], Addr[17], Addr[3], Bank[1], Addr[9], Addr[4], Addr[10], Addr[5], Bank[2], Addr[18], Addr[19], Bank[3], Addr[11], Addr[12], Bank[4], Addr[20], Addr[21], Bank[5], Addr[13], Addr[14], IncAddrH, Addr[22], Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], Bank[7], FullIOEN ;
; H ; LC120 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC122 ; nRES, S[2], S[1], S[0], nWE, C7M_2 ; comb~34, comb~38 ;
; H ; LC128 ; PHI1b3_MC ; PHI1b5_MC ;
; H ; LC127 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, IncAddrL, ASel, lpm_counter:Ref_rtl_0|dffs[2], Addr[8], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Bank[0], Addr[16], Addr[2], Addr[17], Addr[3], Bank[1], Addr[9], Addr[4], Addr[10], Addr[5], Bank[2], Addr[18], Addr[19], Bank[3], Addr[11], Addr[12], Bank[4], Addr[20], Addr[21], Bank[5], Addr[13], Addr[14], IncAddrH, Addr[22], Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], Bank[7], FullIOEN ;
; H ; LC116 ; PHI1b5_MC ; PHI1b7_MC ;
; H ; LC125 ; PHI1b4_MC ; PHI1b6_MC ;
; H ; LC119 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC124 ; C7M, nRES, S[1], S[0], S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], RAMSEL_MC ; comb~34, comb~38 ;
; H ; LC121 ; nRES, S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[1], S[0], RAMSEL_MC, C7M_2 ; comb~31 ;
; H ; LC118 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC114 ; C7M, nRES, D[7], AddrMWR_MC, Addr[15], S[1], S[2], S[0], IncAddrH, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], IncAddrH, Addr[22] ;
; H ; LC115 ; D[0] ; RD[0] ;
; H ; LC118 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC116 ; nRES, S[2], S[1], S[0], nWE, C7M_2 ; comb~39, comb~43 ;
; H ; LC124 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC122 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[2], S[1], S[0] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, IncAddrL, lpm_counter:Ref_rtl_0|dffs[2], Addr[8], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Bank[0], Addr[16], Addr[2], Addr[17], Addr[3], Bank[1], Addr[9], Addr[4], Addr[10], Addr[5], Bank[2], Addr[18], Addr[19], Bank[3], Addr[11], Addr[12], Bank[4], Addr[20], Addr[21], Bank[5], Addr[13], Addr[14], IncAddrH, Addr[22], Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], Bank[7], FullIOEN ;
; H ; LC127 ; PHI1b7_MC ; PHI1b9_MC ;
; H ; LC120 ; C7M, nRES, S[1], S[0], S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], RAMSEL_MC ; comb~39, comb~43 ;
; H ; LC121 ; nRES, S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[1], S[0], RAMSEL_MC, C7M_2 ; comb~36 ;
; H ; LC126 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, IncAddrL, ASel, lpm_counter:Ref_rtl_0|dffs[2], Addr[8], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Bank[0], Addr[16], Addr[2], Addr[17], Addr[3], Bank[1], Addr[9], Addr[4], Addr[10], Addr[5], Bank[2], Addr[18], Addr[19], Bank[3], Addr[11], Addr[12], Bank[4], Addr[20], Addr[21], Bank[5], Addr[13], Addr[14], IncAddrH, Addr[22], Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], Bank[7], FullIOEN ;
; H ; LC125 ; PHI1b6_MC ; PHI1b8_MC ;
; H ; LC119 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC117 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[2], S[1], S[0] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, IncAddrL, ASel, lpm_counter:Ref_rtl_0|dffs[2], Addr[8], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Bank[0], Addr[16], Addr[2], Addr[17], Addr[3], Bank[1], Addr[9], Addr[4], Addr[10], Addr[5], Bank[2], Addr[18], Addr[19], Bank[3], Addr[11], Addr[12], Bank[4], Addr[20], Addr[21], Bank[5], Addr[13], Addr[14], IncAddrH, Addr[22], Bank[6], Addr[6], Addr[7], IncAddrM, Addr[15], Bank[7], FullIOEN ;
; H ; LC113 ; PHI1b5_MC ; PHI1b7_MC ;
; H ; LC114 ; PHI1b4_MC ; PHI1b6_MC ;
; H ; LC128 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
; H ; LC123 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC117 ; PHI1b2_MC ; PHI1b4_MC ;
; H ; LC113 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[2], S[1], S[0] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, IncAddrL, ASel, lpm_counter:Ref_rtl_0|dffs[2], Addr[8], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Bank[0], Addr[16], Addr[2], Addr[17], Addr[3], Bank[1], Addr[9], Addr[4], Addr[10], Addr[5], Bank[2], Addr[18], Addr[19], Bank[3], Addr[11], Addr[12], Bank[4], Addr[20], Addr[21], Bank[5], Addr[13], Addr[14], IncAddrH, Addr[22], Bank[6], Addr[6], Addr[7], IncAddrM, Addr[15], Bank[7], FullIOEN ;
; H ; LC126 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@ -712,10 +713,12 @@ Note: User assignments will override these defaults. The user specified values a
+-----------------+
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM"
Info: Quartus II 32-bit Fitter was successful. 0 errors, 1 warning
Warning (15705): Ignored locations or region assignments to the following nodes
Warning (15706): Node "MODE" is assigned to location or region, but does not exist in design
Info: Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 287 megabytes
Info: Processing ended: Thu Sep 05 21:45:07 2019
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:06
Info: Processing ended: Sat Sep 07 21:15:38 2019
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05

2
cpld/output_files/GR8RAM.fit.summary
View File

@ -1,4 +1,4 @@
Fitter Status : Successful - Thu Sep 05 21:45:07 2019
Fitter Status : Successful - Sat Sep 07 21:15:37 2019
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM

17
cpld/output_files/GR8RAM.flow.rpt
View File

@ -1,5 +1,5 @@
Flow report for GR8RAM
Thu Sep 05 21:45:17 2019
Sat Sep 07 21:15:48 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -40,7 +40,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------+-------------------------------------------------+
; Flow Status ; Successful - Thu Sep 05 21:45:11 2019 ;
; Flow Status ; Successful - Sat Sep 07 21:15:42 2019 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
@ -57,7 +57,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/05/2019 21:44:55 ;
; Start date & time ; 09/07/2019 21:15:27 ;
; Main task ; Compilation ;
; Revision Name ; GR8RAM ;
+-------------------+---------------------+
@ -71,7 +71,8 @@ applicable agreement for further details.
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ;
; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 52238299365.156773429502244 ; -- ; -- ; -- ;
; AUTO_TURBO_BIT ; Off ; On ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 52238299365.156790532703820 ; -- ; -- ; -- ;
; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ;
; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ;
; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ;
@ -97,11 +98,11 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 304 MB ; 00:00:09 ;
; Fitter ; 00:00:06 ; 1.0 ; 287 MB ; 00:00:06 ;
; Assembler ; 00:00:02 ; 1.0 ; 275 MB ; 00:00:02 ;
; Analysis & Synthesis ; 00:00:08 ; 1.0 ; 304 MB ; 00:00:08 ;
; Fitter ; 00:00:04 ; 1.0 ; 287 MB ; 00:00:05 ;
; Assembler ; 00:00:03 ; 1.0 ; 275 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 259 MB ; 00:00:05 ;
; Total ; 00:00:23 ; -- ; -- ; 00:00:22 ;
; Total ; 00:00:20 ; -- ; -- ; 00:00:20 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+

2
cpld/output_files/GR8RAM.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="377ae0e3d641f83b46e8"/>
<hash md5_digest_80b="c391878a634f7d9b75fb"/>
</project>
<file_info>
<file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>

21
cpld/output_files/GR8RAM.map.rpt
View File

@ -1,5 +1,5 @@
Analysis & Synthesis report for GR8RAM
Thu Sep 05 21:45:00 2019
Sat Sep 07 21:15:31 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -44,7 +44,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 05 21:45:00 2019 ;
; Analysis & Synthesis Status ; Successful - Sat Sep 07 21:15:31 2019 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
@ -159,8 +159,8 @@ applicable agreement for further details.
; Shareable expanders ; 1 ;
; Maximum fan-out node ; nRES ;
; Maximum fan-out ; 52 ;
; Total fan-out ; 830 ;
; Average fan-out ; 5.03 ;
; Total fan-out ; 831 ;
; Average fan-out ; 5.04 ;
+----------------------+----------------------+
@ -319,7 +319,7 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Sep 05 21:44:50 2019
Info: Processing started: Sat Sep 07 21:15:23 2019
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
@ -371,10 +371,9 @@ Info (13014): Ignored 32 buffer(s)
Info (280013): Promoted pin-driven signal(s) to global signal
Info (280014): Promoted clock signal driven by pin "C7M" to global clock signal
Info (280015): Promoted clear signal driven by pin "nRES" to global clear signal
Warning (21074): Design contains 8 input pin(s) that do not drive logic
Warning (21074): Design contains 7 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "Q3"
Warning (15610): No output dependent on input pin "PHI0in"
Warning (15610): No output dependent on input pin "MODE"
Warning (15610): No output dependent on input pin "A[11]"
Warning (15610): No output dependent on input pin "A[12]"
Warning (15610): No output dependent on input pin "A[13]"
@ -387,11 +386,11 @@ Info (21057): Implemented 165 device resources after synthesis - the final resou
Info (21063): Implemented 103 macrocells
Info (21073): Implemented 1 shareable expanders
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 15 warnings
Info: Peak virtual memory: 304 megabytes
Info: Processing ended: Thu Sep 05 21:45:00 2019
Info: Elapsed time: 00:00:10
Info: Total CPU time (on all processors): 00:00:09
Info: Processing ended: Sat Sep 07 21:15:32 2019
Info: Elapsed time: 00:00:09
Info: Total CPU time (on all processors): 00:00:08
+------------------------------------------+

4
cpld/output_files/GR8RAM.map.smsg
View File

@ -1,3 +1,3 @@
Warning (10273): Verilog HDL warning at GR8RAM.v(38): extended using "x" or "z"
Warning (10273): Verilog HDL warning at GR8RAM.v(46): extended using "x" or "z"
Warning (10273): Verilog HDL warning at GR8RAM.v(52): extended using "x" or "z"
Warning (10273): Verilog HDL warning at GR8RAM.v(60): extended using "x" or "z"
Warning (10268): Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments

2
cpld/output_files/GR8RAM.map.summary
View File

@ -1,4 +1,4 @@
Analysis & Synthesis Status : Successful - Thu Sep 05 21:45:00 2019
Analysis & Synthesis Status : Successful - Sat Sep 07 21:15:31 2019
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM

4
cpld/output_files/GR8RAM.pin
View File

@ -97,14 +97,14 @@ D[3] : 33 : bidir : TTL :
D[2] : 34 : bidir : TTL : : : Y
D[1] : 35 : bidir : TTL : : : Y
D[0] : 36 : bidir : TTL : : : Y
RESERVED : 37 : : : : :
nMode : 37 : input : TTL : : : N
VCCIO : 38 : power : : 5.0V : :
nCAS0 : 39 : output : TTL : : : Y
nCAS1 : 40 : output : TTL : : : Y
nRCS : 41 : output : TTL : : : Y
GND : 42 : gnd : : : :
VCCINT : 43 : power : : 5.0V : :
MODE : 44 : input : TTL : : : Y
RESERVED : 44 : : : : :
nROE : 45 : output : TTL : : : Y
RA[9] : 46 : output : TTL : : : Y
GND : 47 : gnd : : : :

BIN
cpld/output_files/GR8RAM.pof
View File

Binary file not shown.

488
cpld/output_files/GR8RAM.sta.rpt
View File

@ -1,5 +1,5 @@
TimeQuest Timing Analyzer report for GR8RAM
Thu Sep 05 21:45:17 2019
Sat Sep 07 21:15:48 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -97,7 +97,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+---------+---------------+
; C7M ; -47.500 ; -1992.500 ;
; C7M ; -47.500 ; -1979.500 ;
; C7M_2 ; -27.500 ; -33.000 ;
+-------+---------+---------------+
@ -301,6 +301,9 @@ No paths to report.
; 5.000 ; S[2] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[2] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
@ -332,9 +335,6 @@ No paths to report.
; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; CSDBEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
@ -524,17 +524,17 @@ No paths to report.
; A[1] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
; A[2] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
; A[3] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
; A[4] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; A[5] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; A[6] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; A[7] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; A[8] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; A[9] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; A[10] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; A[4] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
; A[5] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
; A[6] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
; A[7] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
; A[8] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
; A[9] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
; A[10] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
; PHI1in ; C7M ; 101.000 ; 101.000 ; Rise ; C7M ;
; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
; nIOSEL ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; nIOSTRB ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; nIOSTRB ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
; A[*] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ;
; A[0] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ;
; A[1] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ;
@ -566,22 +566,22 @@ No paths to report.
+-----------+------------+---------+---------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+---------+---------+------------+-----------------+
; A[*] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[0] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[1] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[2] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[3] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[4] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[5] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[6] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[7] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[8] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[9] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[10] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; A[*] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[0] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[1] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[2] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[3] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[4] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[5] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[6] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[7] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[8] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[9] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[10] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; PHI1in ; C7M ; -12.000 ; -12.000 ; Rise ; C7M ;
; nDEVSEL ; C7M ; -38.000 ; -38.000 ; Rise ; C7M ;
; nIOSEL ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; nIOSTRB ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; nIOSEL ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; nIOSTRB ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
; A[*] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
; A[0] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
; A[1] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
@ -613,43 +613,43 @@ No paths to report.
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; RA[*] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[0] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[1] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[2] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[3] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[4] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[5] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[6] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[7] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[8] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[9] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[10] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[2] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[3] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[4] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[5] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[6] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[7] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[8] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[9] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[10] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; nCAS0 ; C7M ; 56.000 ; 56.000 ; Rise ; C7M ;
; nCAS1 ; C7M ; 56.000 ; 56.000 ; Rise ; C7M ;
; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; D[*] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[0] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[1] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[2] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[3] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[4] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[5] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[6] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[7] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[*] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[0] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[1] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[2] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[3] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[4] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[5] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[6] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[7] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[8] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[9] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[10] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[8] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[9] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[10] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; nCAS0 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; nCAS1 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; nCAS0 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
@ -663,43 +663,43 @@ No paths to report.
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; RA[*] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[0] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[1] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[2] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[3] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[4] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[5] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[6] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[7] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[8] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[9] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[10] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[2] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[3] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[4] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[5] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[6] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[7] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[8] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[9] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; RA[10] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; nCAS0 ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; nCAS1 ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
; D[*] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[0] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[1] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[2] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[3] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[4] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[5] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[6] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[7] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[*] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[0] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[1] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[2] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[3] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[4] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[5] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[6] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[7] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[8] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[9] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; RA[10] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
; D[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; D[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[8] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[9] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; RA[10] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; nCAS0 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; nCAS1 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
; nCAS0 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
@ -713,70 +713,70 @@ No paths to report.
+------------+-------------+--------+--------+--------+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+--------+--------+--------+--------+
; A[0] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; nCAS0 ; 54.000 ; ; ; 54.000 ;
; A[0] ; nCAS1 ; 54.000 ; ; ; 54.000 ;
; A[1] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; nCAS0 ; 54.000 ; ; ; 54.000 ;
; A[1] ; nCAS1 ; 54.000 ; ; ; 54.000 ;
; A[2] ; D[0] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[1] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[2] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[3] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[4] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[5] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[6] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[7] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[0] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[1] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[2] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[3] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[4] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[5] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[6] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[7] ; ; 32.000 ; 32.000 ; ;
; A[2] ; nCAS0 ; ; 54.000 ; 54.000 ; ;
; A[2] ; nCAS1 ; ; 54.000 ; 54.000 ; ;
; A[3] ; D[0] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[1] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[2] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[3] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[4] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[5] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[6] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[7] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[0] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[1] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[2] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[3] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[4] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[5] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[6] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[7] ; ; 32.000 ; 32.000 ; ;
; A[3] ; nCAS0 ; ; 54.000 ; 54.000 ; ;
; A[3] ; nCAS1 ; ; 54.000 ; 54.000 ; ;
; D[0] ; RD[0] ; 19.000 ; ; ; 19.000 ;
; D[1] ; RD[1] ; 19.000 ; ; ; 19.000 ;
; D[2] ; RD[2] ; 19.000 ; ; ; 19.000 ;
; D[3] ; RD[3] ; 19.000 ; ; ; 19.000 ;
; D[4] ; RD[4] ; 19.000 ; ; ; 19.000 ;
; D[5] ; RD[5] ; 19.000 ; ; ; 19.000 ;
; D[6] ; RD[6] ; 19.000 ; ; ; 19.000 ;
; D[7] ; RD[7] ; 19.000 ; ; ; 19.000 ;
; RD[0] ; D[0] ; 19.000 ; ; ; 19.000 ;
; RD[1] ; D[1] ; 19.000 ; ; ; 19.000 ;
; RD[2] ; D[2] ; 19.000 ; ; ; 19.000 ;
; RD[3] ; D[3] ; 19.000 ; ; ; 19.000 ;
; RD[4] ; D[4] ; 19.000 ; ; ; 19.000 ;
; RD[5] ; D[5] ; 19.000 ; ; ; 19.000 ;
; RD[6] ; D[6] ; 19.000 ; ; ; 19.000 ;
; RD[7] ; D[7] ; 19.000 ; ; ; 19.000 ;
; nDEVSEL ; D[0] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
; nDEVSEL ; D[1] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
; nDEVSEL ; D[2] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
; nDEVSEL ; D[3] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
; nDEVSEL ; D[4] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
; nDEVSEL ; D[5] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
; nDEVSEL ; D[6] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
; nDEVSEL ; D[7] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
; D[0] ; RD[0] ; 32.000 ; ; ; 32.000 ;
; D[1] ; RD[1] ; 32.000 ; ; ; 32.000 ;
; D[2] ; RD[2] ; 32.000 ; ; ; 32.000 ;
; D[3] ; RD[3] ; 32.000 ; ; ; 32.000 ;
; D[4] ; RD[4] ; 32.000 ; ; ; 32.000 ;
; D[5] ; RD[5] ; 32.000 ; ; ; 32.000 ;
; D[6] ; RD[6] ; 32.000 ; ; ; 32.000 ;
; D[7] ; RD[7] ; 32.000 ; ; ; 32.000 ;
; RD[0] ; D[0] ; 32.000 ; ; ; 32.000 ;
; RD[1] ; D[1] ; 32.000 ; ; ; 32.000 ;
; RD[2] ; D[2] ; 32.000 ; ; ; 32.000 ;
; RD[3] ; D[3] ; 32.000 ; ; ; 32.000 ;
; RD[4] ; D[4] ; 32.000 ; ; ; 32.000 ;
; RD[5] ; D[5] ; 32.000 ; ; ; 32.000 ;
; RD[6] ; D[6] ; 32.000 ; ; ; 32.000 ;
; RD[7] ; D[7] ; 32.000 ; ; ; 32.000 ;
; nDEVSEL ; D[0] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ;
; nDEVSEL ; D[1] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ;
; nDEVSEL ; D[2] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ;
; nDEVSEL ; D[3] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ;
; nDEVSEL ; D[4] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ;
; nDEVSEL ; D[5] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ;
; nDEVSEL ; D[6] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ;
; nDEVSEL ; D[7] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ;
; nDEVSEL ; nCAS0 ; ; 54.000 ; 54.000 ; ;
; nDEVSEL ; nCAS1 ; ; 54.000 ; 54.000 ; ;
; nDEVSEL ; nRWE ; 32.000 ; ; ; 32.000 ;
@ -788,14 +788,14 @@ No paths to report.
; nIOSEL ; D[5] ; ; 39.000 ; 39.000 ; ;
; nIOSEL ; D[6] ; ; 39.000 ; 39.000 ; ;
; nIOSEL ; D[7] ; ; 39.000 ; 39.000 ; ;
; nIOSEL ; RA[0] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[1] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[2] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[3] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[4] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[5] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[6] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[7] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[0] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[1] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[2] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[3] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[4] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[5] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[6] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[7] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; nRCS ; ; 32.000 ; 32.000 ; ;
; nIOSEL ; nRWE ; 32.000 ; ; ; 32.000 ;
; nIOSTRB ; D[0] ; ; 39.000 ; 39.000 ; ;
@ -806,16 +806,17 @@ No paths to report.
; nIOSTRB ; D[5] ; ; 39.000 ; 39.000 ; ;
; nIOSTRB ; D[6] ; ; 39.000 ; 39.000 ; ;
; nIOSTRB ; D[7] ; ; 39.000 ; 39.000 ; ;
; nIOSTRB ; RA[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; nRCS ; ; 32.000 ; 32.000 ; ;
; nIOSTRB ; nRWE ; 32.000 ; ; ; 32.000 ;
; nMode ; D[7] ; 32.000 ; ; ; 32.000 ;
; nWE ; D[0] ; 39.000 ; ; ; 39.000 ;
; nWE ; D[1] ; 39.000 ; ; ; 39.000 ;
; nWE ; D[2] ; 39.000 ; ; ; 39.000 ;
@ -842,70 +843,70 @@ No paths to report.
+------------+-------------+--------+--------+--------+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+--------+--------+--------+--------+
; A[0] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[0] ; nCAS0 ; 54.000 ; ; ; 54.000 ;
; A[0] ; nCAS1 ; 54.000 ; ; ; 54.000 ;
; A[1] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; A[1] ; nCAS0 ; 54.000 ; ; ; 54.000 ;
; A[1] ; nCAS1 ; 54.000 ; ; ; 54.000 ;
; A[2] ; D[0] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[1] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[2] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[3] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[4] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[5] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[6] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[7] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[0] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[1] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[2] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[3] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[4] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[5] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[6] ; ; 32.000 ; 32.000 ; ;
; A[2] ; D[7] ; ; 32.000 ; 32.000 ; ;
; A[2] ; nCAS0 ; ; 54.000 ; 54.000 ; ;
; A[2] ; nCAS1 ; ; 54.000 ; 54.000 ; ;
; A[3] ; D[0] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[1] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[2] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[3] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[4] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[5] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[6] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[7] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[0] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[1] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[2] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[3] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[4] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[5] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[6] ; ; 32.000 ; 32.000 ; ;
; A[3] ; D[7] ; ; 32.000 ; 32.000 ; ;
; A[3] ; nCAS0 ; ; 54.000 ; 54.000 ; ;
; A[3] ; nCAS1 ; ; 54.000 ; 54.000 ; ;
; D[0] ; RD[0] ; 19.000 ; ; ; 19.000 ;
; D[1] ; RD[1] ; 19.000 ; ; ; 19.000 ;
; D[2] ; RD[2] ; 19.000 ; ; ; 19.000 ;
; D[3] ; RD[3] ; 19.000 ; ; ; 19.000 ;
; D[4] ; RD[4] ; 19.000 ; ; ; 19.000 ;
; D[5] ; RD[5] ; 19.000 ; ; ; 19.000 ;
; D[6] ; RD[6] ; 19.000 ; ; ; 19.000 ;
; D[7] ; RD[7] ; 19.000 ; ; ; 19.000 ;
; RD[0] ; D[0] ; 19.000 ; ; ; 19.000 ;
; RD[1] ; D[1] ; 19.000 ; ; ; 19.000 ;
; RD[2] ; D[2] ; 19.000 ; ; ; 19.000 ;
; RD[3] ; D[3] ; 19.000 ; ; ; 19.000 ;
; RD[4] ; D[4] ; 19.000 ; ; ; 19.000 ;
; RD[5] ; D[5] ; 19.000 ; ; ; 19.000 ;
; RD[6] ; D[6] ; 19.000 ; ; ; 19.000 ;
; RD[7] ; D[7] ; 19.000 ; ; ; 19.000 ;
; nDEVSEL ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nDEVSEL ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nDEVSEL ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nDEVSEL ; D[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nDEVSEL ; D[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nDEVSEL ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nDEVSEL ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nDEVSEL ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; D[0] ; RD[0] ; 32.000 ; ; ; 32.000 ;
; D[1] ; RD[1] ; 32.000 ; ; ; 32.000 ;
; D[2] ; RD[2] ; 32.000 ; ; ; 32.000 ;
; D[3] ; RD[3] ; 32.000 ; ; ; 32.000 ;
; D[4] ; RD[4] ; 32.000 ; ; ; 32.000 ;
; D[5] ; RD[5] ; 32.000 ; ; ; 32.000 ;
; D[6] ; RD[6] ; 32.000 ; ; ; 32.000 ;
; D[7] ; RD[7] ; 32.000 ; ; ; 32.000 ;
; RD[0] ; D[0] ; 32.000 ; ; ; 32.000 ;
; RD[1] ; D[1] ; 32.000 ; ; ; 32.000 ;
; RD[2] ; D[2] ; 32.000 ; ; ; 32.000 ;
; RD[3] ; D[3] ; 32.000 ; ; ; 32.000 ;
; RD[4] ; D[4] ; 32.000 ; ; ; 32.000 ;
; RD[5] ; D[5] ; 32.000 ; ; ; 32.000 ;
; RD[6] ; D[6] ; 32.000 ; ; ; 32.000 ;
; RD[7] ; D[7] ; 32.000 ; ; ; 32.000 ;
; nDEVSEL ; D[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nDEVSEL ; D[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nDEVSEL ; D[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nDEVSEL ; D[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nDEVSEL ; D[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nDEVSEL ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nDEVSEL ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nDEVSEL ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nDEVSEL ; nCAS0 ; ; 54.000 ; 54.000 ; ;
; nDEVSEL ; nCAS1 ; ; 54.000 ; 54.000 ; ;
; nDEVSEL ; nRWE ; 32.000 ; ; ; 32.000 ;
@ -917,14 +918,14 @@ No paths to report.
; nIOSEL ; D[5] ; ; 39.000 ; 39.000 ; ;
; nIOSEL ; D[6] ; ; 39.000 ; 39.000 ; ;
; nIOSEL ; D[7] ; ; 39.000 ; 39.000 ; ;
; nIOSEL ; RA[0] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[1] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[2] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[3] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[4] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[5] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[6] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[7] ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; RA[0] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[1] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[2] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[3] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[4] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[5] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[6] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; RA[7] ; 32.000 ; ; ; 32.000 ;
; nIOSEL ; nRCS ; ; 32.000 ; 32.000 ; ;
; nIOSEL ; nRWE ; 32.000 ; ; ; 32.000 ;
; nIOSTRB ; D[0] ; ; 39.000 ; 39.000 ; ;
@ -935,16 +936,17 @@ No paths to report.
; nIOSTRB ; D[5] ; ; 39.000 ; 39.000 ; ;
; nIOSTRB ; D[6] ; ; 39.000 ; 39.000 ; ;
; nIOSTRB ; D[7] ; ; 39.000 ; 39.000 ; ;
; nIOSTRB ; RA[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nIOSTRB ; RA[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; RA[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
; nIOSTRB ; nRCS ; ; 32.000 ; 32.000 ; ;
; nIOSTRB ; nRWE ; 32.000 ; ; ; 32.000 ;
; nMode ; D[7] ; 32.000 ; ; ; 32.000 ;
; nWE ; D[0] ; 39.000 ; ; ; 39.000 ;
; nWE ; D[1] ; 39.000 ; ; ; 39.000 ;
; nWE ; D[2] ; 39.000 ; ; ; 39.000 ;
@ -1111,10 +1113,10 @@ No dedicated SERDES Receiver circuitry present in device or used in design
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 33 ; 33 ;
; Unconstrained Input Port Paths ; 463 ; 463 ;
; Unconstrained Input Ports ; 34 ; 34 ;
; Unconstrained Input Port Paths ; 464 ; 464 ;
; Unconstrained Output Ports ; 33 ; 33 ;
; Unconstrained Output Port Paths ; 265 ; 265 ;
; Unconstrained Output Port Paths ; 266 ; 266 ;
+---------------------------------+-------+------+
@ -1124,7 +1126,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Sep 05 21:45:12 2019
Info: Processing started: Sat Sep 07 21:15:43 2019
Info: Command: quartus_sta GR8RAM -c GR8RAM
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
@ -1141,7 +1143,7 @@ Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -47.500
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -47.500 -1992.500 C7M
Info (332119): -47.500 -1979.500 C7M
Info (332119): -27.500 -33.000 C7M_2
Info (332146): Worst-case hold slack is -1.500
Info (332119): Slack End Point TNS Clock
@ -1160,7 +1162,7 @@ Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 259 megabytes
Info: Processing ended: Thu Sep 05 21:45:17 2019
Info: Processing ended: Sat Sep 07 21:15:48 2019
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05

2
cpld/output_files/GR8RAM.sta.summary
View File

@ -4,7 +4,7 @@ TimeQuest Timing Analyzer Summary
Type : Setup 'C7M'
Slack : -47.500
TNS : -1992.500
TNS : -1979.500
Type : Setup 'C7M_2'
Slack : -27.500