Pipelined addition

cpld/GR8RAM.qsf

@@ -144,28 +144,10 @@ set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS OFF
 set_location_assignment PIN_76 -to A[1]
 set_location_assignment PIN_8 -to PHI0in
 set_location_assignment PIN_2 -to PHI1in
-set_location_assignment PIN_31 -to C7Mout
-set_location_assignment PIN_30 -to PHI1out
 set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES OFF
 set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES OFF
 set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to ASel
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[0]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[1]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[2]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[3]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[4]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[5]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[6]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[7]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[8]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[9]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[10]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[11]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[12]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[13]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[14]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[15]
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Add0
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Add1
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Add2
@@ -174,72 +156,16 @@ set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to AddrHWR_MC
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to AddrLWR_MC
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to AddrMWR_MC
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[0]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[1]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[2]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[3]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[4]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[5]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[6]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[7]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[8]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[9]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[10]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[11]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[12]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[13]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[14]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[15]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[16]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[17]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[18]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[19]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[20]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[21]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[22]
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to BankWR_MC
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[0]
+set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to C7M
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[1]
+set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to C7M_2
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[2]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[3]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[4]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[5]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[6]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[7]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to C7M
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to C7M_2
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to C7Mout
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to CASf
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to CASr
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to CSDBEN
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to DOE
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[0]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[0]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[1]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[1]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[2]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[2]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[3]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[3]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[4]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[4]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[5]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[5]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[6]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[6]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[7]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[7]~direct
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[0]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[1]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[2]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[3]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[4]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[5]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[6]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[7]
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal0
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal1
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal2
@@ -258,11 +184,10 @@ set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal14
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal15
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal16
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal17
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to IOBank0
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to IOROMEN
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to MODE
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI0seen
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b
+set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b0_MC
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b1_MC
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b2_MC
@@ -274,7 +199,6 @@ set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b7_MC
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b8_MC
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b9_MC
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1in
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1out
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1reg
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Q3
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA
@@ -282,45 +206,11 @@ set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RAMSEL_MC
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RAMSELreg
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RASf
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RASr
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[0]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[1]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[2]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[3]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[4]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[5]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[6]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[7]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[8]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[9]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[10]
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RDOE
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[0]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[0]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[1]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[1]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[2]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[2]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[3]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[3]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[4]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[4]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[5]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[5]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[6]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[6]~direct
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[7]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[7]~direct
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to REGEN
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[0]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[1]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[2]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[3]
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S[0]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S[1]
-set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S[2]
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to SetWR
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to always0
 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to always2

cpld/GR8RAM.v

@@ -1,8 +1,7 @@
 module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
 			  A, RA, nWE, D, RD, nINH,
 			  nDEVSEL, nIOSEL, nIOSTRB,
-			  nRAS, nCAS0, nCAS1, nRCS, nROE, nRWE,
+			  nRAS, nCAS0, nCAS1, nRCS, nROE, nRWE);
-			  C7Mout, PHI1out);
 
 	/* Clock, Reset, Mode */
 	input C7M, C7M_2, Q3, PHI0in, PHI1in; // Clock inputs
@@ -21,8 +20,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
 	LCELL PHI1b7_MC (.in(PHI1b[6]), .out(PHI1b[7]));
 	LCELL PHI1b8_MC (.in(PHI1b[7]), .out(PHI1b[8]));
 	LCELL PHI1b9_MC (.in(PHI1b[8] & PHI1in), .out(PHI1));
-	output C7Mout = C7M_2;
-	output PHI1out = PHI1;
 
 	/* Address Bus, etc. */
 	input nDEVSEL, nIOSEL, nIOSTRB; // Card select signals
@@ -31,7 +28,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
 	output [10:0] RA; // DRAM/ROM address
 	assign RA[10:8] = ASel ? Addr[21:19] : Addr[10:8];
 	assign RA[7:0] = (~nIOSTRB & FullIOEN) ? Bank+1 :
-		(~nIOSTRB & ~FullIOEN) ? {7'b0000001, Bank[0]} :
+		(~nIOSTRB & ~FullIOEN) ? {7'b0000001, Bank[0]} : 
 		(~ASel & nIOSEL & nIOSTRB) ? Addr[18:11] :
 		(ASel & nIOSEL & nIOSTRB) ? Addr[7:0] : 8'h00;
 
@@ -51,7 +48,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
 	/* Inhibit output */
 	wire AROMSEL;
 	LCELL AROMSEL_MC (.in(/*(A[15:12]==4'hD | A[15:12]==4'hE | A[15:12]==4'hF) & nWE & ~MODE*/0), .out(AROMSEL));
-	output nINH = AROMSEL ? 1'b0 : 1'bZ;
+	output nINH = AROMSEL ? 1'b0 :  1'bZ;
 
 	/* DRAM and ROM Control Signals */
 	output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSDBEN); // ROM chip select
@@ -64,6 +61,9 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
   	/* 6502-accessible Registers */
 	reg [7:0] Bank = 8'h00; // Bank register for ROM access
 	reg [22:0] Addr = 23'h00000; // RAM address register
+	
+	/* Increment Control */
+	reg IncAddrL = 0, IncAddrM = 0, IncAddrH = 0;
 
 	/* CAS rising/falling edge components */
 	// These are combined to create the CAS outputs.
@@ -79,7 +79,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
 	reg [3:0] Ref = 4'h0; // Refresh skip counter
 
 	/* Select Signals */
-	reg RAMSELreg = 1'b0; // RAMSEL registered at end of S4
 	wire BankSELA = A[3:0]==4'hF;
 	wire SetSELA = A[3:0]==4'hE;
 	wire RAMSELA = A[3:0]==4'h3;
@@ -120,10 +119,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
 			REGEN <= 1'b0;
 			IOROMEN <= 1'b0;
 			CSDBEN <= 1'b0;
-			Addr <= 23'h000000;
-			Bank <= 8'h00;
-			FullIOEN <= 1'b0;
-			RAMSELreg <= 1'b0;
 		end else begin
 			// Synchronize state counter to S1 when just entering PHI1
 			PHI1reg <= PHI1; // Save old PHI1
@@ -144,9 +139,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
 			// Enable IOSTRB ROM when accessing CnXX in IOSEL ROM.
 			if (S==4 & ~nIOSEL) IOROMEN <= 1'b1;
 
-			// Register RAM "register" selected at end of S4.
-			if (S==4) RAMSELreg <= RAMSEL;
-
 			// Only drive Apple II data bus after state 4 to avoid bus fight.
 			// Thus we wait 1.5 7M cycles (210 ns) into PHI0 before driving.
 			// Same for driving the ROM/SRAM data bus (RD).
@@ -154,17 +146,43 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
 			// This provides address setup time for write operations and 
 			// minimizes power consumption.
 			CSDBEN <= S==4 | S==5 | S==6 | S==7;
-
+		end
-			// Increment address register after RAM access.
+	end
-			if (S==2 & RAMSELreg) begin
+	
-				Addr <= Addr+1;
+	always @(negedge C7M, negedge nRES) begin
-				RAMSELreg <= 1'b0;
+		if (~nRES) begin
+			Addr <= 23'h000000;
+			Bank <= 8'h00;
+			FullIOEN <= 1'b0;
+			IncAddrL <= 1'b0;
+			IncAddrM <= 1'b0;
+			IncAddrH <= 1'b0;
+		end else begin
+			// Increment address register
+			if (S==1 & IncAddrL) begin
+				Addr[7:0] <= Addr[7:0]+1;
+				IncAddrL <= 0;
+				IncAddrM <= Addr[7:0] == 8'hFF;
+			end
+			if (S==2 & IncAddrM) begin
+				Addr[15:8] <= Addr[15:8]+1;
+				IncAddrM <= 0;
+				IncAddrH <= Addr[15:8] == 8'hFF;
+			end
+			if (S==3 & IncAddrH) begin
+				IncAddrH <= 0;
+				Addr[22:16] <= Addr[22:16]+1;
 			end
 			
 			// Set register during S6 if accessed.
 			if (S==6) begin
 				if (BankWR) Bank[7:0] <= D[7:0]; // Bank
 				if (SetWR) FullIOEN <= D[7:0] == 8'hE5;
+				
+				IncAddrL <= RAMSEL;
+				IncAddrM <= AddrLWR & Addr[7] & ~D[7];
+				IncAddrH <= AddrMWR & Addr[15] & ~D[7];
+				
 				if (AddrHWR) Addr[22:16] <= D[6:0]; // Addr hi
 				if (AddrMWR) Addr[15:8] <= D[7:0]; // Addr mid
 				if (AddrLWR) Addr[7:0] <= D[7:0]; // Addr lo

cpld/db/GR8RAM.asm.qmsg

@@ -1,5 +1,5 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567472156106 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567534158591 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567472156106 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 20:55:55 2019 " "Processing started: Mon Sep 02 20:55:55 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567472156106 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567472156106 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567534158591 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:09:18 2019 " "Processing started: Tue Sep 03 14:09:18 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567534158591 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567534158591 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567472156106 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567534158592 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567472157934 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567534158715 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567472158387 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 20:55:58 2019 " "Processing ended: Mon Sep 02 20:55:58 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567472158387 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567472158387 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567472158387 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567472158387 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4521 " "Peak virtual memory: 4521 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567534158856 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:09:18 2019 " "Processing ended: Tue Sep 03 14:09:18 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567534158856 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567534158856 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567534158856 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567534158856 ""}

cpld/db/GR8RAM.db_info

@@ -1,3 +1,3 @@
 Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 Version_Index = 302049280
-Creation_Time = Mon Sep 02 20:55:35 2019
+Creation_Time = Mon Sep 02 21:03:24 2019

cpld/db/GR8RAM.fit.qmsg

@@ -1,3 +1,3 @@
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567472153965 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567534157574 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567472153981 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567534157576 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567472154481 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 20:55:54 2019 " "Processing ended: Mon Sep 02 20:55:54 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567472154481 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567472154481 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567472154481 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567472154481 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567534157800 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:09:17 2019 " "Processing ended: Tue Sep 03 14:09:17 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567534157800 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567534157800 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567534157800 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567534157800 ""}

cpld/db/GR8RAM.hier_info

@@ -1,40 +1,8 @@
 |GR8RAM
+C7M => always1.IN0
 C7M => CASr.CLK
 C7M => RASr.CLK
 C7M => ASel.CLK
-C7M => RAMSELreg.CLK
-C7M => FullIOEN.CLK
-C7M => Bank[0].CLK
-C7M => Bank[1].CLK
-C7M => Bank[2].CLK
-C7M => Bank[3].CLK
-C7M => Bank[4].CLK
-C7M => Bank[5].CLK
-C7M => Bank[6].CLK
-C7M => Bank[7].CLK
-C7M => Addr[0].CLK
-C7M => Addr[1].CLK
-C7M => Addr[2].CLK
-C7M => Addr[3].CLK
-C7M => Addr[4].CLK
-C7M => Addr[5].CLK
-C7M => Addr[6].CLK
-C7M => Addr[7].CLK
-C7M => Addr[8].CLK
-C7M => Addr[9].CLK
-C7M => Addr[10].CLK
-C7M => Addr[11].CLK
-C7M => Addr[12].CLK
-C7M => Addr[13].CLK
-C7M => Addr[14].CLK
-C7M => Addr[15].CLK
-C7M => Addr[16].CLK
-C7M => Addr[17].CLK
-C7M => Addr[18].CLK
-C7M => Addr[19].CLK
-C7M => Addr[20].CLK
-C7M => Addr[21].CLK
-C7M => Addr[22].CLK
 C7M => CSDBEN.CLK
 C7M => IOROMEN.CLK
 C7M => REGEN.CLK
@@ -47,8 +15,7 @@ C7M => S[1].CLK
 C7M => S[2].CLK
 C7M => PHI0seen.CLK
 C7M => PHI1reg.CLK
-C7M_2 => always2.IN0
+C7M_2 => always3.IN0
-C7M_2 => C7Mout.DATAIN
 Q3 => ~NO_FANOUT~
 PHI0in => ~NO_FANOUT~
 PHI1in => comb.IN0
@@ -153,7 +120,5 @@ nCAS1 <= comb.DB_MAX_OUTPUT_PORT_TYPE
 nRCS <= comb.DB_MAX_OUTPUT_PORT_TYPE
 nROE <= comb.DB_MAX_OUTPUT_PORT_TYPE
 nRWE <= comb.DB_MAX_OUTPUT_PORT_TYPE
-C7Mout <= C7M_2.DB_MAX_OUTPUT_PORT_TYPE
-PHI1out <= PHI1b9_MC.DB_MAX_OUTPUT_PORT_TYPE
 
 

cpld/db/GR8RAM.map.qmsg

@@ -1,36 +1,40 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567472141027 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567534155639 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567472141042 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 20:55:40 2019 " "Processing started: Mon Sep 02 20:55:40 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567472141042 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567472141042 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567534155640 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:09:15 2019 " "Processing started: Tue Sep 03 14:09:15 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567534155640 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567534155640 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567472141042 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567534155640 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567472144652 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567534155858 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(41) " "Verilog HDL warning at GR8RAM.v(41): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 41 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567472144777 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(38) " "Verilog HDL warning at GR8RAM.v(38): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 38 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567534155883 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(49) " "Verilog HDL warning at GR8RAM.v(49): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 49 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567472144777 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(46) " "Verilog HDL warning at GR8RAM.v(46): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 46 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567534155883 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(176) " "Verilog HDL information at GR8RAM.v(176): always construct contains both blocking and non-blocking assignments" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 176 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567472144777 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(194) " "Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 194 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567534155883 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567472144793 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567472144793 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567534155884 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567534155884 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567472145183 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567534155924 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(33) " "Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567472145183 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567534155925 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (3)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 131 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567472145183 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(126) " "Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (3)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 126 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567534155926 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(136) " "Verilog HDL assignment warning at GR8RAM.v(136): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 136 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567472145183 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 131 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567534155926 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 GR8RAM.v(160) " "Verilog HDL assignment warning at GR8RAM.v(160): truncated value with size 32 to match size of target (23)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567472145199 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(163) " "Verilog HDL assignment warning at GR8RAM.v(163): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567534155927 "|GR8RAM"}
-{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" {  } {  } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472145527 ""}  } {  } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567472145527 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(168) " "Verilog HDL assignment warning at GR8RAM.v(168): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 168 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567534155927 "|GR8RAM"}
-{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" {  } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472145543 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" {  } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472145543 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567472145543 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (7)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567534155927 "|GR8RAM"}
-{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" {  } {  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472145949 ""}
+{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" {  } {  } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156051 ""}  } {  } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567534156051 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472145949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472145949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472145949 ""}  } {  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567472145949 ""}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" {  } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156051 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" {  } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 168 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156051 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" {  } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 163 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156051 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" {  } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156051 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567534156051 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472146261 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" {  } {  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156077 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146261 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146261 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146261 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146261 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567472146261 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156077 ""}  } {  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567534156077 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146480 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156095 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146699 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156095 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156095 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156095 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156095 ""}  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567534156095 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146715 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156108 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472146980 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156118 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147199 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156119 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147199 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156131 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472147246 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156142 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add3 " "Instantiated megafunction \"lpm_add_sub:Add3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 23 " "Parameter \"LPM_WIDTH\" = \"23\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147246 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147246 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147246 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147246 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567472147246 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156143 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|addcore:adder\[2\] lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|addcore:adder\[2\]\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147246 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156157 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|look_add:look_ahead_unit lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147308 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add5 " "Instantiated megafunction \"lpm_add_sub:Add5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 7 " "Parameter \"LPM_WIDTH\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156157 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156157 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156157 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156157 ""}  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567534156157 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|altshift:result_ext_latency_ffs lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567472147324 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 250 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156158 ""}
-{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "31 " "Ignored 31 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "31 " "Ignored 31 SOFT buffer(s)" {  } {  } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567472147683 ""}  } {  } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567472147683 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156160 ""}
-{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" {  } {  } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567472147886 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" {  } {  } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567472147886 ""}  } {  } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567472147886 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 191 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156161 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567472148308 "|GR8RAM|A[15]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567472148308 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 192 10 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156164 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567472148308 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567472148308 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567472148308 ""} { "Info" "ICUT_CUT_TM_MCELLS" "102 " "Implemented 102 macrocells" {  } {  } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567472148308 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567472148308 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|altshift:result_ext_latency_ffs lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156166 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567472148605 ""}
+{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" {  } {  } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567534156222 ""}  } {  } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567534156222 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567472148777 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 20:55:48 2019 " "Processing ended: Mon Sep 02 20:55:48 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567472148777 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567472148777 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567472148777 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567472148777 ""}
+{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" {  } {  } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567534156316 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" {  } {  } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567534156316 ""}  } {  } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567534156316 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|A[15]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567534156494 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567534156495 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567534156495 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567534156495 ""} { "Info" "ICUT_CUT_TM_MCELLS" "103 " "Implemented 103 macrocells" {  } {  } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567534156495 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" {  } {  } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567534156495 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567534156495 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567534156532 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567534156569 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:09:16 2019 " "Processing ended: Tue Sep 03 14:09:16 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567534156569 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567534156569 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567534156569 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567534156569 ""}

cpld/db/GR8RAM.sta.qmsg

@@ -1,22 +1,22 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567472162325 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567534159804 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567472162341 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 20:55:59 2019 " "Processing started: Mon Sep 02 20:55:59 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567472162341 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567472162341 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567534159805 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:09:19 2019 " "Processing started: Tue Sep 03 14:09:19 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567534159805 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567534159805 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567472162341 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567534159805 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567472162450 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567534159859 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567472164700 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567534159956 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567472164731 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567534159966 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567472164731 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567534159968 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." {  } {  } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567472164872 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." {  } {  } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567534159988 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567472165013 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567534160005 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567472165013 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567534160005 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165028 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165028 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165028 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160006 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160006 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160006 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567472165044 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567534160008 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567472165185 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567534160020 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.000 " "Worst-case setup slack is -47.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165200 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165200 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -47.000     -1816.000 C7M  " "  -47.000     -1816.000 C7M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165200 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -27.500       -33.000 C7M_2  " "  -27.500       -33.000 C7M_2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165200 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567472165200 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160023 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160023 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -47.500     -1888.500 C7M  " "  -47.500     -1888.500 C7M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160023 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -27.500       -33.000 C7M_2  " "  -27.500       -33.000 C7M_2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160023 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567534160023 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.500        -3.000 C7M_2  " "   -1.500        -3.000 C7M_2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    5.000         0.000 C7M  " "    5.000         0.000 C7M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165247 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567472165247 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.500        -3.000 C7M_2  " "   -1.500        -3.000 C7M_2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    5.000         0.000 C7M  " "    5.000         0.000 C7M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160027 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567534160027 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567472165263 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567534160031 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567472165278 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567534160034 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -5.500       -22.000 C7M_2  " "   -5.500       -22.000 C7M_2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.500      -432.000 C7M  " "   -4.500      -432.000 C7M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567472165294 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567472165294 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -5.500       -22.000 C7M_2  " "   -5.500       -22.000 C7M_2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.500      -450.000 C7M  " "   -4.500      -450.000 C7M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160037 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567534160037 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567472165435 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567534160107 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567472165497 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567534160131 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567472165497 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567534160132 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "263 " "Peak virtual memory: 263 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567472165685 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 20:56:05 2019 " "Processing ended: Mon Sep 02 20:56:05 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567472165685 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567472165685 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567472165685 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567472165685 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567534160247 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:09:20 2019 " "Processing ended: Tue Sep 03 14:09:20 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567534160247 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567534160247 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567534160247 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567534160247 ""}

cpld/db/GR8RAM.tmw_info

@@ -1,6 +0,0 @@
-start_full_compilation:s:00:00:27
-start_analysis_synthesis:s:00:00:10-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:06-start_full_compilation
-start_assembler:s:00:00:04-start_full_compilation
-start_timing_analyzer:s:00:00:07-start_full_compilation

cpld/db/add_sub_8ph.tdf

@@ -1,5 +1,5 @@
 --lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=23 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ  VERSION_END
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
 
 
 -- Copyright (C) 1991-2013 Altera Corporation

cpld/db/add_sub_9ph.tdf

@@ -0,0 +1,46 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=15 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 16 
+SUBDESIGN add_sub_9ph
+( 
+	cin	:	input;
+	dataa[14..0]	:	input;
+	datab[14..0]	:	input;
+	result[14..0]	:	output;
+) 
+VARIABLE 
+	add_sub_cella[14..0] : carry_sum;
+	external_cin_cell : carry_sum;
+	datab_node[14..0]	: WIRE;
+	main_cin_wire	: WIRE;
+
+BEGIN 
+	add_sub_cella[].cin = ( ((dataa[14..14] & datab_node[14..14]) # ((dataa[14..14] # datab_node[14..14]) & add_sub_cella[13].cout)), ((dataa[13..13] & datab_node[13..13]) # ((dataa[13..13] # datab_node[13..13]) & add_sub_cella[12].cout)), ((dataa[12..12] & datab_node[12..12]) # ((dataa[12..12] # datab_node[12..12]) & add_sub_cella[11].cout)), ((dataa[11..11] & datab_node[11..11]) # ((dataa[11..11] # datab_node[11..11]) & add_sub_cella[10].cout)), ((dataa[10..10] & datab_node[10..10]) # ((dataa[10..10] # datab_node[10..10]) & add_sub_cella[9].cout)), ((dataa[9..9] & datab_node[9..9]) # ((dataa[9..9] # datab_node[9..9]) & add_sub_cella[8].cout)), ((dataa[8..8] & datab_node[8..8]) # ((dataa[8..8] # datab_node[8..8]) & add_sub_cella[7].cout)), ((dataa[7..7] & datab_node[7..7]) # ((dataa[7..7] # datab_node[7..7]) & add_sub_cella[6].cout)), ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
+	add_sub_cella[].sin = ( ((dataa[14..14] $ datab_node[14..14]) $ add_sub_cella[13].cout), ((dataa[13..13] $ datab_node[13..13]) $ add_sub_cella[12].cout), ((dataa[12..12] $ datab_node[12..12]) $ add_sub_cella[11].cout), ((dataa[11..11] $ datab_node[11..11]) $ add_sub_cella[10].cout), ((dataa[10..10] $ datab_node[10..10]) $ add_sub_cella[9].cout), ((dataa[9..9] $ datab_node[9..9]) $ add_sub_cella[8].cout), ((dataa[8..8] $ datab_node[8..8]) $ add_sub_cella[7].cout), ((dataa[7..7] $ datab_node[7..7]) $ add_sub_cella[6].cout), ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
+	external_cin_cell.cin = cin;
+	external_cin_cell.sin = B"0";
+	datab_node[] = datab[];
+	main_cin_wire = external_cin_cell.cout;
+	result[] = add_sub_cella[].sout;
+END;
+--VALID FILE

cpld/db/add_sub_qnh.tdf

@@ -0,0 +1,46 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=7 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 8 
+SUBDESIGN add_sub_qnh
+( 
+	cin	:	input;
+	dataa[6..0]	:	input;
+	datab[6..0]	:	input;
+	result[6..0]	:	output;
+) 
+VARIABLE 
+	add_sub_cella[6..0] : carry_sum;
+	external_cin_cell : carry_sum;
+	datab_node[6..0]	: WIRE;
+	main_cin_wire	: WIRE;
+
+BEGIN 
+	add_sub_cella[].cin = ( ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
+	add_sub_cella[].sin = ( ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
+	external_cin_cell.cin = cin;
+	external_cin_cell.sin = B"0";
+	datab_node[] = datab[];
+	main_cin_wire = external_cin_cell.cout;
+	result[] = add_sub_cella[].sout;
+END;
+--VALID FILE

cpld/db/add_sub_rnh.tdf

@@ -1,5 +1,5 @@
 --lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ  VERSION_END
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
 
 
 -- Copyright (C) 1991-2013 Altera Corporation

cpld/db/prev_cmp_GR8RAM.qmsg

@@ -1,74 +1,78 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567402633084 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567533898320 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402633084 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:37:12 2019 " "Processing started: Mon Sep 02 01:37:12 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402633084 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567402633084 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567533898321 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:04:58 2019 " "Processing started: Tue Sep 03 14:04:58 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567533898321 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567533898321 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567402633084 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567533898321 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567402636787 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567533898533 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(40) " "Verilog HDL warning at GR8RAM.v(40): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 40 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567402636975 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(38) " "Verilog HDL warning at GR8RAM.v(38): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 38 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567533898558 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(48) " "Verilog HDL warning at GR8RAM.v(48): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 48 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567402636975 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(46) " "Verilog HDL warning at GR8RAM.v(46): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 46 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567533898558 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(175) " "Verilog HDL information at GR8RAM.v(175): always construct contains both blocking and non-blocking assignments" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 175 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567402636975 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(194) " "Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 194 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567533898558 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567402636975 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567402636975 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567533898559 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567533898559 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567402637240 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567533898605 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(33) " "Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402637240 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567533898607 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (3)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402637240 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(126) " "Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (3)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 126 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567533898607 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(135) " "Verilog HDL assignment warning at GR8RAM.v(135): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 135 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402637240 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 131 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567533898607 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 GR8RAM.v(159) " "Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (23)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402637240 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(163) " "Verilog HDL assignment warning at GR8RAM.v(163): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567533898607 "|GR8RAM"}
-{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" {  } {  } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402637600 ""}  } {  } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567402637600 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(168) " "Verilog HDL assignment warning at GR8RAM.v(168): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 168 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567533898607 "|GR8RAM"}
-{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" {  } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402637600 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" {  } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402637600 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567402637600 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (7)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567533898607 "|GR8RAM"}
-{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" {  } {  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402638147 ""}
+{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" {  } {  } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898686 ""}  } {  } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567533898686 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638162 ""}  } {  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567402638162 ""}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" {  } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898686 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" {  } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 168 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898686 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" {  } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 163 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898686 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" {  } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898686 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567533898686 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402638412 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" {  } {  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898719 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638412 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638412 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638412 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638412 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567402638412 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898719 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898719 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898719 ""}  } {  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567533898719 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638740 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898736 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639006 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898736 ""}  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567533898736 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639053 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898750 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639272 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898760 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639693 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898761 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639787 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898774 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402639959 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898783 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add3 " "Instantiated megafunction \"lpm_add_sub:Add3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 23 " "Parameter \"LPM_WIDTH\" = \"23\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639959 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639959 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639959 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639959 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567402639959 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898784 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|addcore:adder\[2\] lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|addcore:adder\[2\]\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402640178 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898798 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|look_add:look_ahead_unit lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402640318 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add5 " "Instantiated megafunction \"lpm_add_sub:Add5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 7 " "Parameter \"LPM_WIDTH\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898798 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898798 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898798 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898798 ""}  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567533898798 ""}
-{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|altshift:result_ext_latency_ffs lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402640365 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 250 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898799 ""}
-{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "31 " "Ignored 31 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "31 " "Ignored 31 SOFT buffer(s)" {  } {  } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567402640850 ""}  } {  } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567402640850 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898801 ""}
-{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" {  } {  } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567402641146 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" {  } {  } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567402641146 ""}  } {  } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567402641146 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 191 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898802 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|A[15]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567402641725 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" {  } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 192 10 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898804 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567402641740 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567402641740 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567402641740 ""} { "Info" "ICUT_CUT_TM_MCELLS" "102 " "Implemented 102 macrocells" {  } {  } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567402641740 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567402641740 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|altshift:result_ext_latency_ffs lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898806 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567402642303 ""}
+{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" {  } {  } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567533898861 ""}  } {  } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567533898861 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "308 " "Peak virtual memory: 308 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402642443 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:37:22 2019 " "Processing ended: Mon Sep 02 01:37:22 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402642443 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402642443 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402642443 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567402642443 ""}
+{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" {  } {  } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567533898953 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" {  } {  } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567533898953 ""}  } {  } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567533898953 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567402646912 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|A[15]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567533899135 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402646943 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:37:23 2019 " "Processing started: Mon Sep 02 01:37:23 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402646943 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1567402646943 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567533899135 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567533899135 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567533899135 ""} { "Info" "ICUT_CUT_TM_MCELLS" "103 " "Implemented 103 macrocells" {  } {  } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567533899135 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" {  } {  } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567533899135 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567533899135 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1567402646943 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567533899176 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1567402647256 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567533899220 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:04:59 2019 " "Processing ended: Tue Sep 03 14:04:59 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567533899220 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567533899220 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567533899220 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567533899220 ""}
-{ "Info" "0" "" "Project  = GR8RAM" {  } {  } 0 0 "Project  = GR8RAM" 0 0 "Fitter" 0 0 1567402647256 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567533900167 ""}
-{ "Info" "0" "" "Revision = GR8RAM" {  } {  } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1567402647256 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567533900167 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:04:59 2019 " "Processing started: Tue Sep 03 14:04:59 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567533900167 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1567533900167 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567402650052 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1567533900167 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567402650084 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1567533900219 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402651162 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:37:31 2019 " "Processing ended: Mon Sep 02 01:37:31 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402651162 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402651162 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402651162 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567402651162 ""}
+{ "Info" "0" "" "Project  = GR8RAM" {  } {  } 0 0 "Project  = GR8RAM" 0 0 "Fitter" 0 0 1567533900219 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1567402654115 ""}
+{ "Info" "0" "" "Revision = GR8RAM" {  } {  } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1567533900220 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402654130 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:37:33 2019 " "Processing started: Mon Sep 02 01:37:33 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402654130 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567402654130 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567533900261 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567402654130 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567533900263 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567402659802 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567533900441 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:05:00 2019 " "Processing ended: Tue Sep 03 14:05:00 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567533900441 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567533900441 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567533900441 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567533900441 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402660708 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:37:40 2019 " "Processing ended: Mon Sep 02 01:37:40 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402660708 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402660708 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402660708 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567402660708 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1567533901287 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1567402662083 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567533901287 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:05:01 2019 " "Processing started: Tue Sep 03 14:05:01 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567533901287 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567533901287 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1567402666020 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567533901287 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402666020 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:37:42 2019 " "Processing started: Mon Sep 02 01:37:42 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402666020 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567402666020 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567533901404 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567402666020 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4521 " "Peak virtual memory: 4521 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567533901536 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:05:01 2019 " "Processing ended: Tue Sep 03 14:05:01 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567533901536 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567533901536 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567533901536 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567533901536 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567402666129 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1567533902188 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567402668660 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1567533902511 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567402668676 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902512 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:05:02 2019 " "Processing started: Tue Sep 03 14:05:02 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567533902512 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567533902512 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567402668676 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567533902512 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." {  } {  } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567402668785 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567533902568 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567402668863 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567533902719 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567402668863 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567533902726 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567402668863 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567402668863 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567402668863 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567533902728 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567402668879 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." {  } {  } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567533902748 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567402669035 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567533902762 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.000 " "Worst-case setup slack is -47.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -47.000     -1802.000 C7M  " "  -47.000     -1802.000 C7M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -27.500       -33.000 C7M_2  " "  -27.500       -33.000 C7M_2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669113 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567402669113 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567533902762 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669129 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669129 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.500        -3.000 C7M_2  " "   -1.500        -3.000 C7M_2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669129 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    5.000         0.000 C7M  " "    5.000         0.000 C7M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669129 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567402669129 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902763 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902763 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902763 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567402669129 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567533902765 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567402669144 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567533902776 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669160 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669160 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -5.500       -22.000 C7M_2  " "   -5.500       -22.000 C7M_2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669160 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.500      -432.000 C7M  " "   -4.500      -432.000 C7M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669160 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567402669160 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -47.500     -1888.500 C7M  " "  -47.500     -1888.500 C7M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -27.500       -33.000 C7M_2  " "  -27.500       -33.000 C7M_2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902778 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567533902778 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567402669285 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902782 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902782 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.500        -3.000 C7M_2  " "   -1.500        -3.000 C7M_2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902782 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    5.000         0.000 C7M  " "    5.000         0.000 C7M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902782 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567533902782 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567402669347 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567533902786 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567402669347 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567533902789 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "263 " "Peak virtual memory: 263 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402669582 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:37:49 2019 " "Processing ended: Mon Sep 02 01:37:49 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402669582 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402669582 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402669582 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567402669582 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902792 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902792 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -5.500       -22.000 C7M_2  " "   -5.500       -22.000 C7M_2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902792 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.500      -450.000 C7M  " "   -4.500      -450.000 C7M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902792 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567533902792 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 19 s " "Quartus II Full Compilation was successful. 0 errors, 19 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567402670472 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567533902856 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567533902887 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567533902888 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4541 " "Peak virtual memory: 4541 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567533902965 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:05:02 2019 " "Processing ended: Tue Sep 03 14:05:02 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567533902965 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567533902965 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567533902965 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567533902965 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus II Full Compilation was successful. 0 errors, 21 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567533903599 ""}

cpld/output_files/GR8RAM.asm.rpt

@@ -1,6 +1,6 @@
 Assembler report for GR8RAM
-Mon Sep 02 20:55:58 2019
+Tue Sep 03 14:09:18 2019
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -10,7 +10,7 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
   2. Assembler Summary
   3. Assembler Settings
   4. Assembler Generated Files
-  5. Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof
+  5. Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof
   6. Assembler Messages
 
 
@@ -37,7 +37,7 @@ applicable agreement for further details.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Mon Sep 02 20:55:58 2019 ;
+; Assembler Status      ; Successful - Tue Sep 03 14:09:18 2019 ;
 ; Revision Name         ; GR8RAM                                ;
 ; Top-level Entity Name ; GR8RAM                                ;
 ; Family                ; MAX7000S                              ;
@@ -73,39 +73,39 @@ applicable agreement for further details.
 +-----------------------------------------------------------------------------+----------+---------------+
 
 
-+----------------------------------------------+
++--------------------------------------------------------------------+
-; Assembler Generated Files                    ;
+; Assembler Generated Files                                          ;
-+----------------------------------------------+
++--------------------------------------------------------------------+
-; File Name                                    ;
+; File Name                                                          ;
-+----------------------------------------------+
++--------------------------------------------------------------------+
-; Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
+; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
-+----------------------------------------------+
++--------------------------------------------------------------------+
 
 
-+------------------------------------------------------------------------+
++----------------------------------------------------------------------------------------------+
-; Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
+; Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
-+----------------+-------------------------------------------------------+
++----------------+-----------------------------------------------------------------------------+
-; Option         ; Setting                                               ;
+; Option         ; Setting                                                                     ;
-+----------------+-------------------------------------------------------+
++----------------+-----------------------------------------------------------------------------+
-; Device         ; EPM7128SLC84-15                                       ;
+; Device         ; EPM7128SLC84-15                                                             ;
-; JTAG usercode  ; 0x00000000                                            ;
+; JTAG usercode  ; 0x00000000                                                                  ;
-; Checksum       ; 0x0017B008                                            ;
+; Checksum       ; 0x0017D254                                                                  ;
-+----------------+-------------------------------------------------------+
++----------------+-----------------------------------------------------------------------------+
 
 
 +--------------------+
 ; Assembler Messages ;
 +--------------------+
 Info: *******************************************************************
-Info: Running Quartus II 32-bit Assembler
+Info: Running Quartus II 64-Bit Assembler
     Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Mon Sep 02 20:55:55 2019
+    Info: Processing started: Tue Sep 03 14:09:18 2019
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
 Info (115030): Assembler is generating device programming files
-Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 277 megabytes
+    Info: Peak virtual memory: 4521 megabytes
-    Info: Processing ended: Mon Sep 02 20:55:58 2019
+    Info: Processing ended: Tue Sep 03 14:09:18 2019
-    Info: Elapsed time: 00:00:03
+    Info: Elapsed time: 00:00:00
-    Info: Total CPU time (on all processors): 00:00:02
+    Info: Total CPU time (on all processors): 00:00:00
 
 

cpld/output_files/GR8RAM.done

@@ -1 +1 @@
-Mon Sep 02 20:56:06 2019
+Tue Sep 03 14:09:20 2019

cpld/output_files/GR8RAM.fit.rpt

@@ -1,6 +1,6 @@
 Fitter report for GR8RAM
-Mon Sep 02 20:55:54 2019
+Tue Sep 03 14:09:17 2019
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -9,25 +9,27 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
   1. Legal Notice
   2. Fitter Summary
   3. Fitter Settings
-  4. Pin-Out File
+  4. Parallel Compilation
-  5. Fitter Resource Usage Summary
+  5. Pin-Out File
-  6. Input Pins
+  6. Fitter Resource Usage Summary
-  7. Output Pins
+  7. Input Pins
-  8. Bidir Pins
+  8. Output Pins
-  9. All Package Pins
+  9. Bidir Pins
- 10. I/O Standard
+ 10. All Package Pins
- 11. Dedicated Inputs I/O
+ 11. I/O Standard
- 12. Output Pin Default Load For Reported TCO
+ 12. Dedicated Inputs I/O
- 13. Fitter Resource Utilization by Entity
+ 13. Output Pin Default Load For Reported TCO
- 14. Control Signals
+ 14. Fitter Resource Utilization by Entity
- 15. Global & Other Fast Signals
+ 15. Control Signals
- 16. Non-Global High Fan-Out Signals
+ 16. Global & Other Fast Signals
- 17. Other Routing Usage Summary
+ 17. Non-Global High Fan-Out Signals
- 18. LAB External Interconnect
+ 18. Other Routing Usage Summary
- 19. LAB Macrocells
+ 19. LAB External Interconnect
- 20. Logic Cell Interconnection
+ 20. LAB Macrocells
- 21. Fitter Device Options
+ 21. Shareable Expander
- 22. Fitter Messages
+ 22. Logic Cell Interconnection
+ 23. Fitter Device Options
+ 24. Fitter Messages
 
 
 
@@ -53,15 +55,15 @@ applicable agreement for further details.
 +-----------------------------------------------------------------------------+
 ; Fitter Summary                                                              ;
 +---------------------------+-------------------------------------------------+
-; Fitter Status             ; Successful - Mon Sep 02 20:55:54 2019           ;
+; Fitter Status             ; Successful - Tue Sep 03 14:09:17 2019           ;
-; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
 ; Revision Name             ; GR8RAM                                          ;
 ; Top-level Entity Name     ; GR8RAM                                          ;
 ; Family                    ; MAX7000S                                        ;
 ; Device                    ; EPM7128SLC84-15                                 ;
 ; Timing Models             ; Final                                           ;
-; Total macrocells          ; 102 / 128 ( 80 % )                              ;
+; Total macrocells          ; 103 / 128 ( 80 % )                              ;
-; Total pins                ; 67 / 68 ( 99 % )                                ;
+; Total pins                ; 65 / 68 ( 96 % )                                ;
 +---------------------------+-------------------------------------------------+
 
 
@@ -85,10 +87,21 @@ applicable agreement for further details.
 +----------------------------------------------------------------------------+-----------------------+---------------+
 
 
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 8      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
 +--------------+
 ; Pin-Out File ;
 +--------------+
-The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pin.
 
 
 +---------------------------------------------------+
@@ -96,21 +109,21 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
 +------------------------------+--------------------+
 ; Resource                     ; Usage              ;
 +------------------------------+--------------------+
-; Logic cells                  ; 102 / 128 ( 80 % ) ;
+; Logic cells                  ; 103 / 128 ( 80 % ) ;
-; Registers                    ; 50 / 128 ( 39 % )  ;
+; Registers                    ; 52 / 128 ( 41 % )  ;
-; Number of pterms used        ; 251                ;
+; Number of pterms used        ; 260                ;
-; I/O pins                     ; 67 / 68 ( 99 % )   ;
+; I/O pins                     ; 65 / 68 ( 96 % )   ;
 ;     -- Clock pins            ; 2 / 2 ( 100 % )    ;
 ;     -- Dedicated input pins  ; 2 / 2 ( 100 % )    ;
 ;                              ;                    ;
 ; Global signals               ; 2                  ;
-; Shareable expanders          ; 0 / 128 ( 0 % )    ;
+; Shareable expanders          ; 1 / 128 ( < 1 % )  ;
 ; Parallel expanders           ; 0 / 120 ( 0 % )    ;
-; Cells using turbo bit        ; 57 / 128 ( 45 % )  ;
+; Cells using turbo bit        ; 59 / 128 ( 46 % )  ;
-; Maximum fan-out              ; 50                 ;
+; Maximum fan-out              ; 52                 ;
-; Highest non-global fan-out   ; 48                 ;
+; Highest non-global fan-out   ; 51                 ;
-; Total fan-out                ; 971                ;
+; Total fan-out                ; 830                ;
-; Average fan-out              ; 5.75               ;
+; Average fan-out              ; 4.91               ;
 +------------------------------+--------------------+
 
 
@@ -135,8 +148,8 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
 ; A[7]    ; 5     ; --       ; 1   ; 1                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
 ; A[8]    ; 9     ; --       ; 1   ; 1                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
 ; A[9]    ; 10    ; --       ; 1   ; 1                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
-; C7M     ; 83    ; --       ; --  ; 48                    ; 0                  ; yes    ; no             ; TTL          ; User                 ;
+; C7M     ; 83    ; --       ; --  ; 50                    ; 0                  ; yes    ; no             ; TTL          ; User                 ;
-; C7M_2   ; 84    ; --       ; --  ; 3                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; C7M_2   ; 84    ; --       ; --  ; 2                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
 ; MODE    ; 44    ; --       ; 5   ; 0                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
 ; PHI0in  ; 8     ; --       ; 1   ; 0                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
 ; PHI1in  ; 2     ; --       ; --  ; 2                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
@@ -144,37 +157,35 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
 ; nDEVSEL ; 21    ; --       ; 2   ; 16                    ; 0                  ; no     ; no             ; TTL          ; User                 ;
 ; nIOSEL  ; 74    ; --       ; 8   ; 13                    ; 0                  ; no     ; no             ; TTL          ; User                 ;
 ; nIOSTRB ; 24    ; --       ; 3   ; 12                    ; 0                  ; no     ; no             ; TTL          ; User                 ;
-; nRES    ; 1     ; --       ; --  ; 50                    ; 0                  ; yes    ; no             ; TTL          ; User                 ;
+; nRES    ; 1     ; --       ; --  ; 52                    ; 0                  ; yes    ; no             ; TTL          ; User                 ;
 ; nWE     ; 20    ; --       ; 2   ; 10                    ; 0                  ; no     ; no             ; TTL          ; User                 ;
 +---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                 ;
+; Output Pins                                                                                                                                                                                ;
-+---------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
++--------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
-; Name    ; Pin # ; I/O Bank ; LAB ; Output Register ; Slow Slew Rate ; Open Drain ; TRI Primitive ; I/O Standard ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
+; Name   ; Pin # ; I/O Bank ; LAB ; Output Register ; Slow Slew Rate ; Open Drain ; TRI Primitive ; I/O Standard ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
++--------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
-; C7Mout  ; 31    ; --       ; 3   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[0]  ; 52    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; PHI1out ; 30    ; --       ; 3   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[10] ; 48    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[0]   ; 52    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[1]  ; 54    ; --       ; 6   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[10]  ; 48    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[2]  ; 50    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[1]   ; 54    ; --       ; 6   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[3]  ; 49    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[2]   ; 50    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[4]  ; 55    ; --       ; 6   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[3]   ; 49    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[5]  ; 51    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[4]   ; 55    ; --       ; 6   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[6]  ; 57    ; --       ; 6   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[5]   ; 51    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[7]  ; 56    ; --       ; 6   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[6]   ; 57    ; --       ; 6   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[8]  ; 58    ; --       ; 6   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[7]   ; 56    ; --       ; 6   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[9]  ; 46    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[8]   ; 58    ; --       ; 6   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; nCAS0  ; 39    ; --       ; 4   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[9]   ; 46    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; nCAS1  ; 40    ; --       ; 4   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; nCAS0   ; 39    ; --       ; 4   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; nINH   ; 22    ; --       ; 2   ; no              ; yes            ; yes        ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; nCAS1   ; 40    ; --       ; 4   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; nRAS   ; 60    ; --       ; 6   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; nINH    ; 22    ; --       ; 2   ; no              ; yes            ; yes        ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; nRCS   ; 41    ; --       ; 4   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; nRAS    ; 60    ; --       ; 6   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; nROE   ; 45    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; nRCS    ; 41    ; --       ; 4   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; nRWE   ; 67    ; --       ; 7   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-; nROE    ; 45    ; --       ; 5   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
++--------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
-; nRWE    ; 67    ; --       ; 7   ; no              ; yes            ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
-+---------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
 
 
 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -189,7 +200,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
 ; D[4]  ; 29    ; --       ; 3   ; 6                     ; 0                  ; no     ; no             ; no              ; yes            ; no         ; TTL          ; User                 ; 10 pF ; DOE~5                ; -                   ;
 ; D[5]  ; 28    ; --       ; 3   ; 6                     ; 0                  ; no     ; no             ; no              ; yes            ; no         ; TTL          ; User                 ; 10 pF ; DOE~5                ; -                   ;
 ; D[6]  ; 27    ; --       ; 3   ; 6                     ; 0                  ; no     ; no             ; no              ; yes            ; no         ; TTL          ; User                 ; 10 pF ; DOE~5                ; -                   ;
-; D[7]  ; 25    ; --       ; 3   ; 5                     ; 0                  ; no     ; no             ; no              ; yes            ; no         ; TTL          ; User                 ; 10 pF ; DOE~5                ; -                   ;
+; D[7]  ; 25    ; --       ; 3   ; 7                     ; 0                  ; no     ; no             ; no              ; yes            ; no         ; TTL          ; User                 ; 10 pF ; DOE~5                ; -                   ;
 ; RD[0] ; 73    ; --       ; 8   ; 1                     ; 0                  ; no     ; no             ; no              ; yes            ; no         ; TTL          ; User                 ; 10 pF ; RDOE~1               ; -                   ;
 ; RD[1] ; 70    ; --       ; 7   ; 1                     ; 0                  ; no     ; no             ; no              ; yes            ; no         ; TTL          ; User                 ; 10 pF ; RDOE~1               ; -                   ;
 ; RD[2] ; 69    ; --       ; 7   ; 1                     ; 0                  ; no     ; no             ; no              ; yes            ; no         ; TTL          ; User                 ; 10 pF ; RDOE~1               ; -                   ;
@@ -235,8 +246,8 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
 ; 27       ; 26         ; --       ; D[6]           ; bidir  ; TTL          ;         ; Y               ;
 ; 28       ; 27         ; --       ; D[5]           ; bidir  ; TTL          ;         ; Y               ;
 ; 29       ; 28         ; --       ; D[4]           ; bidir  ; TTL          ;         ; Y               ;
-; 30       ; 29         ; --       ; PHI1out        ; output ; TTL          ;         ; Y               ;
+; 30       ; 29         ; --       ; RESERVED       ;        ;              ;         ;                 ;
-; 31       ; 30         ; --       ; C7Mout         ; output ; TTL          ;         ; Y               ;
+; 31       ; 30         ; --       ; RESERVED       ;        ;              ;         ;                 ;
 ; 32       ; 31         ; --       ; GND            ; gnd    ;              ;         ;                 ;
 ; 33       ; 32         ; --       ; D[3]           ; bidir  ; TTL          ;         ; Y               ;
 ; 34       ; 33         ; --       ; D[2]           ; bidir  ; TTL          ;         ; Y               ;
@@ -332,7 +343,7 @@ Note: User assignments will override these defaults. The user specified values a
 +----------------------------+------------+------+-------------------------------+--------------+
 ; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name           ; Library Name ;
 +----------------------------+------------+------+-------------------------------+--------------+
-; |GR8RAM                    ; 102        ; 67   ; |GR8RAM                       ; work         ;
+; |GR8RAM                    ; 103        ; 65   ; |GR8RAM                       ; work         ;
 ;    |lpm_counter:Ref_rtl_0| ; 4          ; 0    ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work         ;
 +----------------------------+------------+------+-------------------------------+--------------+
 
@@ -346,17 +357,17 @@ Note: User assignments will override these defaults. The user specified values a
 ; A[1]      ; PIN_76   ; 15      ; Clock enable ; no     ; --                   ; --               ;
 ; A[2]      ; PIN_77   ; 15      ; Clock enable ; no     ; --                   ; --               ;
 ; A[3]      ; PIN_79   ; 15      ; Clock enable ; no     ; --                   ; --               ;
-; BankWR_MC ; LC111    ; 8       ; Clock enable ; no     ; --                   ; --               ;
+; BankWR_MC ; LC102    ; 8       ; Clock enable ; no     ; --                   ; --               ;
-; C7M       ; PIN_83   ; 48      ; Clock        ; yes    ; On                   ; --               ;
+; C7M       ; PIN_83   ; 50      ; Clock        ; yes    ; On                   ; --               ;
-; C7M_2     ; PIN_84   ; 3       ; Clock        ; no     ; --                   ; --               ;
+; C7M_2     ; PIN_84   ; 2       ; Clock        ; no     ; --                   ; --               ;
-; PHI1b9_MC ; LC37     ; 6       ; Clock enable ; no     ; --                   ; --               ;
+; PHI1b9_MC ; LC33     ; 5       ; Clock enable ; no     ; --                   ; --               ;
-; REGEN     ; LC106    ; 7       ; Clock enable ; no     ; --                   ; --               ;
+; REGEN     ; LC35     ; 7       ; Clock enable ; no     ; --                   ; --               ;
-; S[0]      ; LC113    ; 46      ; Clock enable ; no     ; --                   ; --               ;
+; S[0]      ; LC122    ; 49      ; Clock enable ; no     ; --                   ; --               ;
-; S[1]      ; LC121    ; 47      ; Clock enable ; no     ; --                   ; --               ;
+; S[1]      ; LC117    ; 49      ; Clock enable ; no     ; --                   ; --               ;
-; S[2]      ; LC117    ; 48      ; Clock enable ; no     ; --                   ; --               ;
+; S[2]      ; LC126    ; 51      ; Clock enable ; no     ; --                   ; --               ;
 ; nDEVSEL   ; PIN_21   ; 16      ; Clock enable ; no     ; --                   ; --               ;
 ; nIOSEL    ; PIN_74   ; 13      ; Clock enable ; no     ; --                   ; --               ;
-; nRES      ; PIN_1    ; 50      ; Async. clear ; yes    ; On                   ; --               ;
+; nRES      ; PIN_1    ; 52      ; Async. clear ; yes    ; On                   ; --               ;
 ; nWE       ; PIN_20   ; 10      ; Clock enable ; no     ; --                   ; --               ;
 +-----------+----------+---------+--------------+--------+----------------------+------------------+
 
@@ -366,8 +377,8 @@ Note: User assignments will override these defaults. The user specified values a
 +------+----------+---------+----------------------+------------------+
 ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
 +------+----------+---------+----------------------+------------------+
-; C7M  ; PIN_83   ; 48      ; On                   ; --               ;
+; C7M  ; PIN_83   ; 50      ; On                   ; --               ;
-; nRES ; PIN_1    ; 50      ; On                   ; --               ;
+; nRES ; PIN_1    ; 52      ; On                   ; --               ;
 +------+----------+---------+----------------------+------------------+
 
 
@@ -376,45 +387,42 @@ Note: User assignments will override these defaults. The user specified values a
 +-------------------------------+---------+
 ; Name                          ; Fan-Out ;
 +-------------------------------+---------+
-; S[2]                          ; 48      ;
+; S[2]                          ; 51      ;
-; S[1]                          ; 47      ;
+; S[1]                          ; 49      ;
-; S[0]                          ; 46      ;
+; S[0]                          ; 49      ;
-; Addr[0]                       ; 25      ;
-; Addr[1]                       ; 24      ;
-; RAMSELreg                     ; 24      ;
-; Addr[2]                       ; 23      ;
-; Addr[3]                       ; 22      ;
-; Addr[4]                       ; 21      ;
-; Addr[5]                       ; 20      ;
-; Addr[6]                       ; 19      ;
-; Addr[7]                       ; 18      ;
-; Addr[8]                       ; 17      ;
 ; nDEVSEL                       ; 16      ;
-; Addr[9]                       ; 16      ;
 ; A[3]                          ; 15      ;
 ; A[2]                          ; 15      ;
 ; A[1]                          ; 15      ;
 ; A[0]                          ; 15      ;
-; Addr[10]                      ; 15      ;
-; Addr[11]                      ; 14      ;
 ; nIOSEL                        ; 13      ;
-; Addr[12]                      ; 13      ;
 ; nIOSTRB                       ; 12      ;
-; Addr[13]                      ; 12      ;
+; Addr[0]                       ; 11      ;
-; Addr[14]                      ; 11      ;
+; Addr[8]                       ; 11      ;
 ; ASel                          ; 11      ;
+; IncAddrL                      ; 11      ;
 ; nWE                           ; 10      ;
-; Addr[15]                      ; 10      ;
+; IncAddrM                      ; 10      ;
+; Addr[9]                       ; 10      ;
+; Addr[1]                       ; 10      ;
+; Addr[10]                      ; 9       ;
+; Addr[2]                       ; 9       ;
 ; Addr[16]                      ; 9       ;
+; AddrLWR_MC                    ; 9       ;
+; AddrMWR_MC                    ; 9       ;
 ; FullIOEN                      ; 8       ;
+; IncAddrH                      ; 8       ;
+; Addr[11]                      ; 8       ;
+; Addr[3]                       ; 8       ;
 ; Addr[17]                      ; 8       ;
 ; Bank[0]                       ; 8       ;
 ; BankWR_MC                     ; 8       ;
-; AddrLWR_MC                    ; 8       ;
-; AddrMWR_MC                    ; 8       ;
 ; RDOE~1                        ; 8       ;
 ; DOE~5                         ; 8       ;
+; D[7]~7                        ; 7       ;
+; Addr[12]                      ; 7       ;
 ; Addr[18]                      ; 7       ;
+; Addr[4]                       ; 7       ;
 ; Bank[1]                       ; 7       ;
 ; AddrHWR_MC                    ; 7       ;
 ; RAMSEL_MC                     ; 7       ;
@@ -426,26 +434,31 @@ Note: User assignments will override these defaults. The user specified values a
 ; D[2]~2                        ; 6       ;
 ; D[1]~1                        ; 6       ;
 ; D[0]~0                        ; 6       ;
+; Addr[13]                      ; 6       ;
 ; Addr[19]                      ; 6       ;
 ; Bank[2]                       ; 6       ;
+; Addr[5]                       ; 6       ;
 ; lpm_counter:Ref_rtl_0|dffs[3] ; 6       ;
 ; lpm_counter:Ref_rtl_0|dffs[2] ; 6       ;
 ; lpm_counter:Ref_rtl_0|dffs[0] ; 6       ;
-; PHI1b9_MC                     ; 6       ;
+; Addr[6]                       ; 5       ;
-; D[7]~7                        ; 5       ;
+; Addr[14]                      ; 5       ;
 ; Addr[20]                      ; 5       ;
 ; Bank[3]                       ; 5       ;
 ; lpm_counter:Ref_rtl_0|dffs[1] ; 5       ;
+; PHI1b9_MC                     ; 5       ;
+; Addr[15]                      ; 4       ;
+; Addr[7]                       ; 4       ;
 ; Addr[22]                      ; 4       ;
 ; Addr[21]                      ; 4       ;
 ; Bank[4]                       ; 4       ;
-; C7M_2                         ; 3       ;
 ; Bank[5]                       ; 3       ;
 ; IOROMEN                       ; 3       ;
 ; CSDBEN                        ; 3       ;
 ; PHI0seen                      ; 3       ;
 ; PHI1reg                       ; 3       ;
 ; PHI1in                        ; 2       ;
+; C7M_2                         ; 2       ;
 ; Bank[6]                       ; 2       ;
 ; CASr                          ; 2       ;
 ; CASf                          ; 2       ;
@@ -474,6 +487,7 @@ Note: User assignments will override these defaults. The user specified values a
 ; RA~79                         ; 1       ;
 ; RA~73                         ; 1       ;
 ; Bank[7]                       ; 1       ;
+; IncAddrM~9                    ; 1       ;
 ; comb~43                       ; 1       ;
 ; comb~39                       ; 1       ;
 ; RA~68                         ; 1       ;
@@ -481,8 +495,8 @@ Note: User assignments will override these defaults. The user specified values a
 ; RA~62                         ; 1       ;
 ; comb~36                       ; 1       ;
 ; RASf                          ; 1       ;
-; RASr                          ; 1       ;
 ; comb~34                       ; 1       ;
+; RASr                          ; 1       ;
 ; PHI1b8_MC                     ; 1       ;
 ; PHI1b7_MC                     ; 1       ;
 ; PHI1b6_MC                     ; 1       ;
@@ -492,7 +506,6 @@ Note: User assignments will override these defaults. The user specified values a
 ; PHI1b2_MC                     ; 1       ;
 ; comb~30                       ; 1       ;
 ; PHI1b1_MC                     ; 1       ;
-; C7M_2~1                       ; 1       ;
 ; nWE~1                         ; 1       ;
 ; PHI1b0_MC                     ; 1       ;
 ; D[7]~38                       ; 1       ;
@@ -520,33 +533,35 @@ Note: User assignments will override these defaults. The user specified values a
 ; Other Routing Resource Type ; Usage              ;
 +-----------------------------+--------------------+
 ; Output enables              ; 2 / 6 ( 33 % )     ;
-; PIA buffers                 ; 196 / 288 ( 68 % ) ;
+; PIA buffers                 ; 219 / 288 ( 76 % ) ;
-; PIAs                        ; 221 / 288 ( 77 % ) ;
+; PIAs                        ; 244 / 288 ( 85 % ) ;
 +-----------------------------+--------------------+
 
 
 +-----------------------------------------------------------------------------+
 ; LAB External Interconnect                                                   ;
 +-----------------------------------------------+-----------------------------+
-; LAB External Interconnects  (Average = 27.63) ; Number of LABs  (Total = 8) ;
+; LAB External Interconnects  (Average = 30.50) ; Number of LABs  (Total = 8) ;
 +-----------------------------------------------+-----------------------------+
-; 0 - 3                                         ; 0                           ;
+; 0 - 2                                         ; 0                           ;
-; 4 - 7                                         ; 0                           ;
+; 3 - 5                                         ; 0                           ;
-; 8 - 11                                        ; 0                           ;
+; 6 - 8                                         ; 0                           ;
-; 12 - 15                                       ; 1                           ;
+; 9 - 11                                        ; 0                           ;
-; 16 - 19                                       ; 0                           ;
+; 12 - 14                                       ; 0                           ;
-; 20 - 23                                       ; 0                           ;
+; 15 - 17                                       ; 0                           ;
-; 24 - 27                                       ; 2                           ;
+; 18 - 20                                       ; 0                           ;
-; 28 - 31                                       ; 4                           ;
+; 21 - 23                                       ; 0                           ;
-; 32 - 35                                       ; 0                           ;
+; 24 - 26                                       ; 1                           ;
-; 36 - 39                                       ; 1                           ;
+; 27 - 29                                       ; 1                           ;
+; 30 - 32                                       ; 5                           ;
+; 33 - 35                                       ; 1                           ;
 +-----------------------------------------------+-----------------------------+
 
 
 +-----------------------------------------------------------------------+
 ; LAB Macrocells                                                        ;
 +-----------------------------------------+-----------------------------+
-; Number of Macrocells  (Average = 12.75) ; Number of LABs  (Total = 8) ;
+; Number of Macrocells  (Average = 12.88) ; Number of LABs  (Total = 8) ;
 +-----------------------------------------+-----------------------------+
 ; 0                                       ; 0                           ;
 ; 1                                       ; 0                           ;
@@ -555,127 +570,138 @@ Note: User assignments will override these defaults. The user specified values a
 ; 4                                       ; 0                           ;
 ; 5                                       ; 0                           ;
 ; 6                                       ; 0                           ;
-; 7                                       ; 1                           ;
+; 7                                       ; 0                           ;
-; 8                                       ; 2                           ;
+; 8                                       ; 1                           ;
-; 9                                       ; 0                           ;
+; 9                                       ; 1                           ;
 ; 10                                      ; 0                           ;
-; 11                                      ; 0                           ;
+; 11                                      ; 1                           ;
 ; 12                                      ; 0                           ;
-; 13                                      ; 0                           ;
+; 13                                      ; 1                           ;
 ; 14                                      ; 0                           ;
-; 15                                      ; 1                           ;
+; 15                                      ; 2                           ;
-; 16                                      ; 4                           ;
+; 16                                      ; 2                           ;
 +-----------------------------------------+-----------------------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
++-------------------------------------------------------------------------------+
-; Logic Cell Interconnection                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+; Shareable Expander                                                            ;
-+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
++-------------------------------------------------+-----------------------------+
-; LAB ; Logic Cell ; Input                                                                                                                                                                                                                                                                                ; Output                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+; Number of shareable expanders  (Average = 0.13) ; Number of LABs  (Total = 1) ;
-+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
++-------------------------------------------------+-----------------------------+
-;  A  ; LC11       ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                                                         ; Dout[2]~83, Addr[16], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], RA~68, Addr[22], Addr[14], Addr[15]                                                                                                                                                                                                                                                                                                                                                                         ;
+; 0                                               ; 7                           ;
-;  A  ; LC1        ; C7M, nRES, D[0], AddrLWR_MC, S[2], S[1], S[0], Addr[0], RAMSELreg                                                                                                                                                                                                                    ; Dout[0]~71, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~73                                                                                                                                                                                                                                                                               ;
+; 1                                               ; 1                           ;
-;  A  ; LC2        ; C7M, nRES, D[1], AddrLWR_MC, S[2], S[1], S[0], Addr[1], Addr[0], RAMSELreg                                                                                                                                                                                                           ; Dout[1]~77, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~120                                                                                                                                                                                                                                                                                       ;
++-------------------------------------------------+-----------------------------+
-;  A  ; LC5        ; C7M, nRES, D[4], AddrLWR_MC, S[2], S[1], S[0], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                                                                                                                ; Dout[4]~95, Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~87                                                                                                                                                                                                                                                                                                                   ;
+
-;  A  ; LC6        ; C7M, nRES, D[5], AddrLWR_MC, S[2], S[1], S[0], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                                                                                                       ; Dout[5]~101, Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~94                                                                                                                                                                                                                                                                                                                           ;
+
-;  A  ; LC3        ; C7M, nRES, D[2], AddrLWR_MC, S[2], S[1], S[0], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                                                                                                                                  ; Dout[2]~83, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~79                                                                                                                                                                                                                                                                                                 ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-;  A  ; LC4        ; C7M, nRES, D[3], AddrLWR_MC, S[2], S[1], S[0], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                                                                                                                         ; Dout[3]~89, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~80                                                                                                                                                                                                                                                                                                          ;
+; Logic Cell Interconnection                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-;  A  ; LC14       ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                           ; Dout[5]~101, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~79                                                                                                                                                                                                                                                                                                                                                                                                      ;
++-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-;  A  ; LC13       ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                                     ; Dout[4]~95, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~120                                                                                                                                                                                                                                                                                                                                                                                            ;
+; LAB ; Logic Cell ; Input                                                                                                                                                                ; Output                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  A  ; LC15       ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                 ; Dout[6]~107, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[14], Addr[15], RA~80                                                                                                                                                                                                                                                                                                                                                                                                                ;
++-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-;  A  ; LC12       ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                                               ; Dout[3]~89, Addr[16], Addr[17], Addr[18], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~73                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  A  ; LC3        ; C7M, nRES, D[2], AddrLWR_MC, S[0], S[2], S[1], Addr[2], IncAddrL, Addr[1], Addr[0]                                                                                   ; Dout[2]~83, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~79                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
-;  A  ; LC7        ; C7M, nRES, D[6], AddrLWR_MC, S[2], S[1], S[0], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                                                                                              ; Dout[6]~107, Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~101                                                                                                                                                                                                                                                                                                                                   ;
+;  A  ; LC2        ; C7M, nRES, D[1], AddrLWR_MC, S[0], S[2], S[1], Addr[1], IncAddrL, Addr[0]                                                                                            ; Dout[1]~77, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~120                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
-;  A  ; LC10       ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                                                                   ; Dout[1]~77, Addr[16], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], RA~65, Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15]                                                                                                                                                                                                                                                                                                                                                                ;
+;  A  ; LC1        ; C7M, nRES, D[0], AddrLWR_MC, S[0], S[2], S[1], Addr[0], IncAddrL                                                                                                     ; Dout[0]~71, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~73                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
-;  A  ; LC9        ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                                                                            ; Dout[0]~71, Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], RA~62, Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15]                                                                                                                                                                                                                                                                                                                                                       ;
+;  A  ; LC16       ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM                                ; Dout[7]~113, IncAddrH, Addr[15], RA~87                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  A  ; LC8        ; C7M, nRES, D[7], AddrLWR_MC, S[2], S[1], S[0], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                                                                                                     ; Dout[7]~113, Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15], RA~108                                                                                                                                                                                                                                                                                                                                            ;
+;  A  ; LC8        ; C7M, nRES, D[7], AddrLWR_MC, S[0], S[2], S[1], Addr[7], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0]                                      ; Dout[7]~113, Addr[7], IncAddrM, RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  A  ; LC16       ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                                       ; Dout[7]~113, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[15], RA~87                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+;  A  ; LC7        ; C7M, nRES, D[6], AddrLWR_MC, S[0], S[2], S[1], Addr[6], IncAddrL, Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0]                                               ; Dout[6]~107, Addr[6], Addr[7], IncAddrM, RA~101                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
-;  B  ; LC30       ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[1], S[0], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                     ; Dout[4]~95, Addr[20], RA~65, Addr[21], Addr[22]                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+;  A  ; LC15       ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM                                          ; Dout[6]~107, Addr[14], IncAddrH, Addr[15], RA~80                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-;  B  ; LC23       ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[1], S[0], Addr[22], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[6]~107, Addr[22], comb~39, comb~43                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+;  A  ; LC9        ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], IncAddrM                                                                                                     ; Dout[0]~71, Addr[8], Addr[9], Addr[10], RA~62, Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15]                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
-;  B  ; LC31       ; C7M, nRES, D[0], AddrHWR_MC, S[2], S[1], S[0], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                             ; Dout[0]~71, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~94                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+;  A  ; LC14       ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM                                                    ; Dout[5]~101, Addr[13], Addr[14], IncAddrH, Addr[15], RA~79                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
-;  B  ; LC20       ; C7M, nRES, D[3], BankWR_MC, S[2], S[1], S[0]                                                                                                                                                                                                                                         ; RA~80, RA~87, RA~94, RA~101, RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+;  A  ; LC13       ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM                                                              ; Dout[4]~95, Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15], RA~120                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  B  ; LC24       ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[1], S[0], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg           ; Dout[5]~101, Addr[21], RA~68, Addr[22]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+;  A  ; LC12       ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM                                                                        ; Dout[3]~89, Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15], RA~73                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
-;  B  ; LC26       ; C7M, nRES, D[5], BankWR_MC, S[2], S[1], S[0]                                                                                                                                                                                                                                         ; RA~94, RA~101, RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  A  ; LC6        ; C7M, nRES, D[5], AddrLWR_MC, S[0], S[2], S[1], Addr[5], IncAddrL, Addr[4], Addr[3], Addr[2], Addr[1], Addr[0]                                                        ; Dout[5]~101, Addr[5], Addr[6], Addr[7], IncAddrM, RA~94                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
-;  B  ; LC25       ; C7M, nRES, D[4], BankWR_MC, S[2], S[1], S[0]                                                                                                                                                                                                                                         ; RA~87, RA~94, RA~101, RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+;  A  ; LC11       ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], Addr[9], Addr[8], IncAddrM                                                                                  ; Dout[2]~83, Addr[10], Addr[11], Addr[12], RA~68, Addr[13], Addr[14], IncAddrH, Addr[15]                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
-;  B  ; LC21       ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[1], S[0], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                               ; Dout[3]~89, Addr[19], RA~62, Addr[20], Addr[21], Addr[22]                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  A  ; LC5        ; C7M, nRES, D[4], AddrLWR_MC, S[0], S[2], S[1], Addr[4], IncAddrL, Addr[3], Addr[2], Addr[1], Addr[0]                                                                 ; Dout[4]~95, Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~87                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
-;  B  ; LC32       ; C7M, nRES, D[2], BankWR_MC, S[2], S[1], S[0]                                                                                                                                                                                                                                         ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+;  A  ; LC10       ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], Addr[8], IncAddrM                                                                                            ; Dout[1]~77, Addr[9], Addr[10], Addr[11], Addr[12], RA~65, Addr[13], Addr[14], IncAddrH, Addr[15]                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-;  B  ; LC29       ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[1], S[0], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                         ; Dout[2]~83, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  A  ; LC4        ; C7M, nRES, D[3], AddrLWR_MC, S[0], S[2], S[1], Addr[3], IncAddrL, Addr[2], Addr[1], Addr[0]                                                                          ; Dout[3]~89, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~80                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
-;  B  ; LC27       ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[1], S[0], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg                                                   ; Dout[1]~77, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~101                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+;  B  ; LC25       ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[0], S[1], Addr[20], IncAddrH, Addr[19], Addr[18], Addr[17], Addr[16]                                                            ; Dout[4]~95, Addr[20], RA~65, Addr[21], Addr[22]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
-;  B  ; LC28       ; C7M, nRES, D[1], BankWR_MC, S[2], S[1], S[0]                                                                                                                                                                                                                                         ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+;  B  ; LC21       ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[0], S[1], Addr[21], IncAddrH, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16]                                                  ; Dout[5]~101, Addr[21], RA~68, Addr[22]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  B  ; LC19       ; C7M, nRES, S[2]                                                                                                                                                                                                                                                                      ; DOE~5, RDOE~1, comb~34                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+;  B  ; LC23       ; C7M, nRES, D[5], BankWR_MC, S[2], S[1], S[0]                                                                                                                         ; RA~94, RA~101, RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  B  ; LC22       ; C7M, nRES, D[0], BankWR_MC, S[2], S[1], S[0]                                                                                                                                                                                                                                         ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  B  ; LC31       ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[0], S[1], Addr[22], IncAddrH, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16]                                        ; Dout[6]~107, Addr[22], comb~39, comb~43                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
-;  B  ; LC18       ; C7M, nRES, D[6], BankWR_MC, S[2], S[1], S[0]                                                                                                                                                                                                                                         ; RA~101, RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+;  B  ; LC29       ; C7M, nRES, D[6], BankWR_MC, S[2], S[1], S[0]                                                                                                                         ; RA~101, RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
-;  B  ; LC17       ;                                                                                                                                                                                                                                                                                      ; nINH                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  B  ; LC17       ;                                                                                                                                                                      ; nINH                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  C  ; LC38       ; RD[4], nDEVSEL, A[0], A[1], A[2], A[3], Addr[12], Addr[20], Addr[4]                                                                                                                                                                                                                  ; D[4]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  B  ; LC32       ; C7M, nRES, D[7], AddrLWR_MC, Addr[7], S[2], S[0], S[1], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrM, IncAddrM~9                ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, IncAddrM, Addr[15]                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-;  C  ; LC43       ; RD[6], nDEVSEL, A[0], A[1], A[2], A[3], Addr[14], Addr[22], Addr[6]                                                                                                                                                                                                                  ; D[6]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  B  ; LC27       ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[0], S[1], Addr[17], IncAddrH, Addr[16]                                                                                          ; Dout[1]~77, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~101                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
-;  C  ; LC45       ; RD[7], nDEVSEL, A[1], A[2], A[3], A[0], Addr[15], Addr[7]                                                                                                                                                                                                                            ; D[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  B  ; LC22       ; PHI1b2_MC                                                                                                                                                            ; PHI1b4_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
-;  C  ; LC36       ; PHI1in                                                                                                                                                                                                                                                                               ; PHI1b1_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  B  ; LC24       ; C7M, nRES, D[2], BankWR_MC, S[2], S[1], S[0]                                                                                                                         ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
-;  C  ; LC34       ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3]                                                                                                                                                                                                                                               ; ASel, RASr, RAMSELreg, CASr, RASf, comb~39, comb~43                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+;  B  ; LC30       ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[0], S[1], Addr[18], IncAddrH, Addr[17], Addr[16]                                                                                ; Dout[2]~83, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  C  ; LC35       ; C7M_2                                                                                                                                                                                                                                                                                ; C7Mout                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+;  B  ; LC26       ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[0], S[1], Addr[19], IncAddrH, Addr[18], Addr[17], Addr[16]                                                                      ; Dout[3]~89, Addr[19], RA~62, Addr[20], Addr[21], Addr[22]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
-;  C  ; LC40       ; RD[5], nDEVSEL, A[0], A[1], A[2], A[3], Addr[13], Addr[21], Addr[5]                                                                                                                                                                                                                  ; D[5]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  B  ; LC28       ; C7M, nRES, D[1], BankWR_MC, S[2], S[1], S[0]                                                                                                                         ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
-;  C  ; LC37       ; PHI1in, PHI1b8_MC                                                                                                                                                                                                                                                                    ; PHI1reg, PHI0seen, PHI1out, S[0], S[1], S[2]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+;  B  ; LC20       ; C7M, nRES, D[3], BankWR_MC, S[2], S[1], S[0]                                                                                                                         ; RA~80, RA~87, RA~94, RA~101, RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
-;  D  ; LC64       ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3]                                                                                                                                                                                                                  ; D[3]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  B  ; LC18       ; C7M, nRES, D[4], BankWR_MC, S[2], S[1], S[0]                                                                                                                         ; RA~87, RA~94, RA~101, RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
-;  D  ; LC61       ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2]                                                                                                                                                                                                                  ; D[2]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  C  ; LC34       ; PHI1in                                                                                                                                                               ; PHI1b1_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
-;  D  ; LC49       ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB                                                                                                                                                                                                                                                     ; nRCS                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  C  ; LC38       ; RD[4], nDEVSEL, A[0], A[1], A[2], A[3], Addr[12], Addr[20], Addr[4]                                                                                                  ; D[4]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  D  ; LC53       ; Addr[22], CASf, RAMSEL_MC, CASr                                                                                                                                                                                                                                                      ; nCAS0                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  C  ; LC40       ; RD[5], nDEVSEL, A[0], A[1], A[2], A[3], Addr[13], Addr[21], Addr[5]                                                                                                  ; D[5]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  D  ; LC51       ; Addr[22], CASf, RAMSEL_MC, CASr                                                                                                                                                                                                                                                      ; nCAS1                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  C  ; LC43       ; RD[6], nDEVSEL, A[0], A[1], A[2], A[3], Addr[14], Addr[22], Addr[6]                                                                                                  ; D[6]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  D  ; LC59       ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1]                                                                                                                                                                                                                   ; D[1]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  C  ; LC45       ; RD[7], nDEVSEL, A[1], A[2], A[3], A[0], Addr[15], Addr[7]                                                                                                            ; D[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  D  ; LC57       ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0]                                                                                                                                                                                                                   ; D[0]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  C  ; LC33       ; PHI1in, PHI1b8_MC                                                                                                                                                    ; PHI1reg, PHI0seen, S[0], S[1], S[2]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
-;  D  ; LC56       ; CSDBEN, nWE                                                                                                                                                                                                                                                                          ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+;  C  ; LC42       ; PHI1b1_MC                                                                                                                                                            ; PHI1b3_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
-;  E  ; LC74       ; PHI1b5_MC                                                                                                                                                                                                                                                                            ; PHI1b7_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  C  ; LC35       ; C7M, nRES, nIOSEL, S[2], S[1], S[0]                                                                                                                                  ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, FullIOEN                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
-;  E  ; LC68       ; PHI1b6_MC                                                                                                                                                                                                                                                                            ; PHI1b8_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  C  ; LC36       ; C7M, nRES, D[0], AddrHWR_MC, S[1], S[2], S[0], Addr[16], IncAddrH                                                                                                    ; Dout[0]~71, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~94                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
-;  E  ; LC79       ; PHI1b7_MC                                                                                                                                                                                                                                                                            ; PHI1b9_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  D  ; LC57       ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0]                                                                                                   ; D[0]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  E  ; LC65       ; PHI1b2_MC                                                                                                                                                                                                                                                                            ; PHI1b4_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  D  ; LC59       ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1]                                                                                                   ; D[1]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  E  ; LC69       ; Addr[20], ASel, Addr[9]                                                                                                                                                                                                                                                              ; RA[9]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  D  ; LC61       ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2]                                                                                                  ; D[2]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  E  ; LC72       ; Addr[21], ASel, Addr[10]                                                                                                                                                                                                                                                             ; RA[10]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+;  D  ; LC64       ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3]                                                                                                  ; D[3]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  E  ; LC67       ; nWE                                                                                                                                                                                                                                                                                  ; nROE                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  D  ; LC51       ; Addr[22], CASf, RAMSEL_MC, CASr                                                                                                                                      ; nCAS1                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  E  ; LC66       ; PHI1b0_MC                                                                                                                                                                                                                                                                            ; PHI1b2_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  D  ; LC50       ; PHI1b0_MC                                                                                                                                                            ; PHI1b2_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
-;  E  ; LC70       ; PHI1b1_MC                                                                                                                                                                                                                                                                            ; PHI1b3_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  D  ; LC53       ; Addr[22], CASf, RAMSEL_MC, CASr                                                                                                                                      ; nCAS0                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  E  ; LC76       ; PHI1b3_MC                                                                                                                                                                                                                                                                            ; PHI1b5_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  D  ; LC49       ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB                                                                                                                                     ; nRCS                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  E  ; LC80       ; Bank[0], FullIOEN, nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0]                                                                                                                                                                                                                          ; RA[0]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  E  ; LC72       ; Addr[21], ASel, Addr[10]                                                                                                                                             ; RA[10]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  E  ; LC75       ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2]                                                                                                                                                                                                        ; RA[2]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  E  ; LC67       ; nWE                                                                                                                                                                  ; nROE                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  E  ; LC73       ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3]                                                                                                                                                                                               ; RA[3]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  E  ; LC70       ; C7M, nRES, D[7], AddrMWR_MC, Addr[15], S[1], S[2], S[0], IncAddrH, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM                      ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], IncAddrH, Addr[22]                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
-;  E  ; LC77       ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5]                                                                                                                                                                             ; RA[5]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  E  ; LC74       ; C7M, nRES, S[2]                                                                                                                                                      ; DOE~5, RDOE~1, comb~34                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  E  ; LC78       ; PHI1b4_MC                                                                                                                                                                                                                                                                            ; PHI1b6_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  E  ; LC78       ; C7M, nRES, D[7], BankWR_MC, S[2], S[1], S[0]                                                                                                                         ; RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  F  ; LC86       ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7]                                                                                                                                                           ; RA[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  E  ; LC80       ; Bank[0], FullIOEN, nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0]                                                                                                          ; RA[0]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  F  ; LC88       ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6]                                                                                                                                                                    ; RA[6]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  E  ; LC75       ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2]                                                                                        ; RA[2]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  F  ; LC85       ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4]                                                                                                                                                                                      ; RA[4]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  E  ; LC73       ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3]                                                                               ; RA[3]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  F  ; LC91       ; Addr[19], ASel, Addr[8]                                                                                                                                                                                                                                                              ; RA[8]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  E  ; LC77       ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5]                                                             ; RA[5]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  F  ; LC93       ; RASr, RASf                                                                                                                                                                                                                                                                           ; nRAS                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  E  ; LC79       ; C7M, nRES, D[0], BankWR_MC, S[2], S[1], S[0]                                                                                                                         ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
-;  F  ; LC94       ; D[7]                                                                                                                                                                                                                                                                                 ; RD[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  E  ; LC69       ; Addr[20], ASel, Addr[9]                                                                                                                                              ; RA[9]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  F  ; LC83       ; Addr[12], ASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0]                                                                                                                                                                                                                 ; RA[1]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  F  ; LC87       ; C7M, nRES, S[1], S[2], RAMSEL_MC                                                                                                                                     ; RA~62, RA~65, RA~68, RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
-;  G  ; LC109      ; D[1]                                                                                                                                                                                                                                                                                 ; RD[1]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  F  ; LC93       ; RASr, RASf                                                                                                                                                           ; nRAS                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  G  ; LC102      ; C7M, nRES, D[7], BankWR_MC, S[2], S[1], S[0]                                                                                                                                                                                                                                         ; RA~108                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+;  F  ; LC84       ; C7M, nRES, PHI1b9_MC                                                                                                                                                 ; S[0], S[1], S[2]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-;  G  ; LC110      ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3]                                                                                                                                                             ; DOE~5, IOROMEN, comb~34                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+;  F  ; LC95       ; C7M, nRES, PHI1b9_MC                                                                                                                                                 ; S[0], S[1], S[2]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-;  G  ; LC103      ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[2], S[1], S[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3]                                                                                                                                                             ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  F  ; LC91       ; Addr[19], ASel, Addr[8]                                                                                                                                              ; RA[8]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  G  ; LC100      ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL                                                                                                                                                                                                                                          ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+;  F  ; LC85       ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4]                                                                      ; RA[4]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  G  ; LC98       ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL                                                                                                                                                                                                                                          ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15]                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+;  F  ; LC81       ; PHI1b3_MC                                                                                                                                                            ; PHI1b5_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
-;  G  ; LC107      ; D[2]                                                                                                                                                                                                                                                                                 ; RD[2]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  F  ; LC94       ; D[7]                                                                                                                                                                 ; RD[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  G  ; LC104      ; nDEVSEL, nIOSEL, nIOSTRB, nWE                                                                                                                                                                                                                                                        ; nRWE                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  F  ; LC89       ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1], IncAddrL                                                                                                                     ; IncAddrL, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM~9, IncAddrM                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  G  ; LC99       ; D[6]                                                                                                                                                                                                                                                                                 ; RD[6]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  F  ; LC96       ; C7M, nRES, RAMSEL_MC, S[2], S[1], S[0]                                                                                                                               ; comb~36                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
-;  G  ; LC97       ; D[5]                                                                                                                                                                                                                                                                                 ; RD[5]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  F  ; LC83       ; Addr[12], ASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0]                                                                                                 ; RA[1]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  G  ; LC101      ; D[4]                                                                                                                                                                                                                                                                                 ; RD[4]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  F  ; LC86       ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7]                                           ; RA[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  G  ; LC105      ; D[3]                                                                                                                                                                                                                                                                                 ; RD[3]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  F  ; LC88       ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6]                                                    ; RA[6]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  G  ; LC108      ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL                                                                                                                                                                                                                                          ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22]                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+;  G  ; LC97       ; D[5]                                                                                                                                                                 ; RD[5]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  G  ; LC112      ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB                                                                                                                                                                                                                                ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+;  G  ; LC112      ; CSDBEN, nWE                                                                                                                                                          ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  G  ; LC106      ; C7M, nRES, nIOSEL, S[0], S[2], S[1]                                                                                                                                                                                                                                                  ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, FullIOEN                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+;  G  ; LC109      ; D[1]                                                                                                                                                                 ; RD[1]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  G  ; LC111      ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3]                                                                                                                                                                                                                                          ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+;  G  ; LC105      ; D[3]                                                                                                                                                                 ; RD[3]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  H  ; LC127      ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0]                                                                                                                              ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+;  G  ; LC101      ; D[4]                                                                                                                                                                 ; RD[4]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  H  ; LC125      ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0]                                                                                                                                                             ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf                                                                                                                                                                                                                                                                                                                                                                                      ;
+;  G  ; LC99       ; D[6]                                                                                                                                                                 ; RD[6]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  H  ; LC128      ; nRES, S[2], S[1], S[0], nWE, C7M_2                                                                                                                                                                                                                                                   ; comb~39, comb~43                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+;  G  ; LC108      ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL                                                                                                                          ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15]                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  H  ; LC117      ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0]                                                                                                                                                                                                                            ; S[0], S[1], S[2], CSDBEN, CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Bank[0], Addr[8], Addr[9], Bank[1], Addr[17], Addr[18], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Bank[5], Addr[21], Addr[22], Bank[6], Addr[14], Addr[15], Bank[7], FullIOEN ;
+;  G  ; LC104      ; nDEVSEL, nIOSEL, nIOSTRB, nWE                                                                                                                                        ; nRWE                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  H  ; LC115      ; D[0]                                                                                                                                                                                                                                                                                 ; RD[0]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+;  G  ; LC110      ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL                                                                                                                          ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-;  H  ; LC119      ; C7M, nRES, S[1], S[0], S[2], RAMSEL_MC, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0]                                                                                                                   ; comb~39, comb~43                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+;  G  ; LC107      ; D[2]                                                                                                                                                                 ; RD[2]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  H  ; LC116      ; nRES, RAMSEL_MC, S[2], S[1], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], C7M_2                                                                                                                 ; comb~36                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+;  G  ; LC98       ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[2], S[1], S[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3]                                             ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
-;  H  ; LC120      ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1]                                                                                                                                                                                                                                               ; comb~36                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+;  G  ; LC102      ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3]                                                                                                                          ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  H  ; LC114      ; C7M, nRES, RAMSEL_MC, S[2], S[1]                                                                                                                                                                                                                                                     ; RA~62, RA~65, RA~68, RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+;  G  ; LC106      ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3]                                             ; DOE~5, IOROMEN, comb~34                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
-;  H  ; LC124      ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0]                                                                                                                              ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf                                                                                                                                                                                                                                                                                                                                                                                      ;
+;  G  ; LC111      ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL                                                                                                                          ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-;  H  ; LC123      ; C7M, nRES, PHI1b9_MC                                                                                                                                                                                                                                                                 ; S[0], S[1], S[2]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+;  G  ; LC103      ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3]                                                                                                                               ; RASr, IncAddrL, ASel, CASr, RASf, comb~39, comb~43                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
-;  H  ; LC126      ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0]                                                                                                                              ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf                                                                                                                                                                                                                                                                                                                                                                                      ;
+;  H  ; LC115      ; D[0]                                                                                                                                                                 ; RD[0]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-;  H  ; LC118      ; C7M, nRES, PHI1b9_MC                                                                                                                                                                                                                                                                 ; S[0], S[1], S[2]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+;  H  ; LC118      ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0]                                             ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  H  ; LC113      ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[2], S[1]                                                                                                                                                                                                                            ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Bank[0], Addr[8], Addr[9], Bank[1], Addr[17], Addr[18], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Bank[5], Addr[21], Addr[22], Bank[6], Addr[14], Addr[15], Bank[7], FullIOEN               ;
+;  H  ; LC116      ; nRES, S[2], S[1], S[0], nWE, C7M_2                                                                                                                                   ; comb~39, comb~43                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-;  H  ; LC121      ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2]                                                                                                                                                                                                                            ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Bank[0], Addr[8], Addr[9], Bank[1], Addr[17], Addr[18], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Bank[5], Addr[21], Addr[22], Bank[6], Addr[14], Addr[15], Bank[7], FullIOEN         ;
+;  H  ; LC124      ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0]              ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-;  H  ; LC122      ; C7M, nRES, S[2], S[1], S[0], RAMSEL_MC, RAMSELreg                                                                                                                                                                                                                                    ; RAMSELreg, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[16], Addr[8], Addr[9], Addr[17], Addr[18], Addr[10], Addr[11], Addr[19], Addr[20], Addr[12], Addr[13], Addr[21], Addr[22], Addr[14], Addr[15]                                                                                                                                                                                                                                                                                       ;
+;  H  ; LC122      ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[2], S[1], S[0]                                                                                                            ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, IncAddrL, lpm_counter:Ref_rtl_0|dffs[2], Addr[8], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Bank[0], Addr[16], Addr[2], Addr[17], Addr[3], Bank[1], Addr[9], Addr[4], Addr[10], Addr[5], Bank[2], Addr[18], Addr[19], Bank[3], Addr[11], Addr[12], Bank[4], Addr[20], Addr[21], Bank[5], Addr[13], Addr[14], IncAddrH, Addr[22], Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], Bank[7], FullIOEN               ;
-+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+;  H  ; LC127      ; PHI1b7_MC                                                                                                                                                            ; PHI1b9_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+;  H  ; LC120      ; C7M, nRES, S[1], S[0], S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], RAMSEL_MC   ; comb~39, comb~43                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+;  H  ; LC121      ; nRES, S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[1], S[0], RAMSEL_MC, C7M_2 ; comb~36                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+;  H  ; LC126      ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0]                                                                                                            ; S[0], S[1], S[2], CSDBEN, CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, IncAddrL, ASel, lpm_counter:Ref_rtl_0|dffs[2], Addr[8], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Bank[0], Addr[16], Addr[2], Addr[17], Addr[3], Bank[1], Addr[9], Addr[4], Addr[10], Addr[5], Bank[2], Addr[18], Addr[19], Bank[3], Addr[11], Addr[12], Bank[4], Addr[20], Addr[21], Bank[5], Addr[13], Addr[14], IncAddrH, Addr[22], Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], Bank[7], FullIOEN ;
+;  H  ; LC125      ; PHI1b6_MC                                                                                                                                                            ; PHI1b8_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+;  H  ; LC119      ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0]              ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+;  H  ; LC117      ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[2], S[1], S[0]                                                                                                            ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, IncAddrL, ASel, lpm_counter:Ref_rtl_0|dffs[2], Addr[8], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Bank[0], Addr[16], Addr[2], Addr[17], Addr[3], Bank[1], Addr[9], Addr[4], Addr[10], Addr[5], Bank[2], Addr[18], Addr[19], Bank[3], Addr[11], Addr[12], Bank[4], Addr[20], Addr[21], Bank[5], Addr[13], Addr[14], IncAddrH, Addr[22], Bank[6], Addr[6], Addr[7], IncAddrM, Addr[15], Bank[7], FullIOEN                     ;
+;  H  ; LC113      ; PHI1b5_MC                                                                                                                                                            ; PHI1b7_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+;  H  ; LC114      ; PHI1b4_MC                                                                                                                                                            ; PHI1b6_MC                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+;  H  ; LC128      ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB                                                                                                                ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+;  H  ; LC123      ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0]              ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 
 
 +---------------------------------------------------------------+
@@ -698,10 +724,10 @@ Note: User assignments will override these defaults. The user specified values a
 +-----------------+
 Warning (20028): Parallel compilation is not licensed and has been disabled
 Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM"
-Info: Quartus II 32-bit Fitter was successful. 0 errors, 1 warning
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 287 megabytes
+    Info: Peak virtual memory: 4708 megabytes
-    Info: Processing ended: Mon Sep 02 20:55:54 2019
+    Info: Processing ended: Tue Sep 03 14:09:17 2019
-    Info: Elapsed time: 00:00:04
+    Info: Elapsed time: 00:00:00
-    Info: Total CPU time (on all processors): 00:00:04
+    Info: Total CPU time (on all processors): 00:00:01
 
 

cpld/output_files/GR8RAM.fit.summary

@@ -1,9 +1,9 @@
-Fitter Status : Successful - Mon Sep 02 20:55:54 2019
+Fitter Status : Successful - Tue Sep 03 14:09:17 2019
-Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
 Revision Name : GR8RAM
 Top-level Entity Name : GR8RAM
 Family : MAX7000S
 Device : EPM7128SLC84-15
 Timing Models : Final
-Total macrocells : 102 / 128 ( 80 % )
+Total macrocells : 103 / 128 ( 80 % )
-Total pins : 67 / 68 ( 99 % )
+Total pins : 65 / 68 ( 96 % )

cpld/output_files/GR8RAM.flow.rpt

@@ -1,6 +1,6 @@
 Flow report for GR8RAM
-Mon Sep 02 20:56:05 2019
+Tue Sep 03 14:09:20 2019
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -40,15 +40,15 @@ applicable agreement for further details.
 +-----------------------------------------------------------------------------+
 ; Flow Summary                                                                ;
 +---------------------------+-------------------------------------------------+
-; Flow Status               ; Successful - Mon Sep 02 20:55:58 2019           ;
+; Flow Status               ; Successful - Tue Sep 03 14:09:18 2019           ;
-; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
 ; Revision Name             ; GR8RAM                                          ;
 ; Top-level Entity Name     ; GR8RAM                                          ;
 ; Family                    ; MAX7000S                                        ;
 ; Device                    ; EPM7128SLC84-15                                 ;
 ; Timing Models             ; Final                                           ;
-; Total macrocells          ; 102 / 128 ( 80 % )                              ;
+; Total macrocells          ; 103 / 128 ( 80 % )                              ;
-; Total pins                ; 67 / 68 ( 99 % )                                ;
+; Total pins                ; 65 / 68 ( 96 % )                                ;
 +---------------------------+-------------------------------------------------+
 
 
@@ -57,39 +57,39 @@ applicable agreement for further details.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 09/02/2019 20:55:44 ;
+; Start date & time ; 09/03/2019 14:09:15 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; GR8RAM              ;
 +-------------------+---------------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------+
++-------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                    ;
+; Flow Non-Default Global Settings                                                                                        ;
-+--------------------------------------------+-----------------------------+---------------+-------------+------------+
++--------------------------------------------+---------------------------------+---------------+-------------+------------+
-; Assignment Name                            ; Value                       ; Default Value ; Entity Name ; Section Id ;
+; Assignment Name                            ; Value                           ; Default Value ; Entity Name ; Section Id ;
-+--------------------------------------------+-----------------------------+---------------+-------------+------------+
++--------------------------------------------+---------------------------------+---------------+-------------+------------+
-; ALM_REGISTER_PACKING_EFFORT                ; High                        ; Medium        ; --          ; --         ;
+; ALM_REGISTER_PACKING_EFFORT                ; High                            ; Medium        ; --          ; --         ;
-; AUTO_LCELL_INSERTION                       ; Off                         ; On            ; --          ; --         ;
+; AUTO_LCELL_INSERTION                       ; Off                             ; On            ; --          ; --         ;
-; AUTO_PARALLEL_EXPANDERS                    ; Off                         ; On            ; --          ; --         ;
+; AUTO_PARALLEL_EXPANDERS                    ; Off                             ; On            ; --          ; --         ;
-; COMPILER_SIGNATURE_ID                      ; 52238299365.156747214401988 ; --            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID                      ; 207120313862967.156753415530004 ; --            ; --          ; --         ;
-; ECO_OPTIMIZE_TIMING                        ; On                          ; Off           ; --          ; --         ;
+; ECO_OPTIMIZE_TIMING                        ; On                              ; Off           ; --          ; --         ;
-; ECO_REGENERATE_REPORT                      ; On                          ; Off           ; --          ; --         ;
+; ECO_REGENERATE_REPORT                      ; On                              ; Off           ; --          ; --         ;
-; EXTRACT_VERILOG_STATE_MACHINES             ; Off                         ; On            ; --          ; --         ;
+; EXTRACT_VERILOG_STATE_MACHINES             ; Off                             ; On            ; --          ; --         ;
-; EXTRACT_VHDL_STATE_MACHINES                ; Off                         ; On            ; --          ; --         ;
+; EXTRACT_VHDL_STATE_MACHINES                ; Off                             ; On            ; --          ; --         ;
-; FITTER_EFFORT                              ; Standard Fit                ; Auto Fit      ; --          ; --         ;
+; FITTER_EFFORT                              ; Standard Fit                    ; Auto Fit      ; --          ; --         ;
-; MAX7000_IGNORE_LCELL_BUFFERS               ; Off                         ; Auto          ; --          ; --         ;
+; MAX7000_IGNORE_LCELL_BUFFERS               ; Off                             ; Auto          ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP                     ; 85                          ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP                     ; 85                              ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP                     ; 0                           ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP                     ; 0                               ; --            ; --          ; --         ;
-; OPTIMIZE_HOLD_TIMING                       ; Off                         ; --            ; --          ; --         ;
+; OPTIMIZE_HOLD_TIMING                       ; Off                             ; --            ; --          ; --         ;
-; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers       ; Normal        ; --          ; --         ;
+; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers           ; Normal        ; --          ; --         ;
-; PARALLEL_SYNTHESIS                         ; Off                         ; On            ; --          ; --         ;
+; PARALLEL_SYNTHESIS                         ; Off                             ; On            ; --          ; --         ;
-; PRE_MAPPING_RESYNTHESIS                    ; On                          ; Off           ; --          ; --         ;
+; PRE_MAPPING_RESYNTHESIS                    ; On                              ; Off           ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY                   ; output_files                ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY                   ; output_files                    ; --            ; --          ; --         ;
-; SLOW_SLEW_RATE                             ; On                          ; Off           ; --          ; --         ;
+; SLOW_SLEW_RATE                             ; On                              ; Off           ; --          ; --         ;
-; STATE_MACHINE_PROCESSING                   ; User-Encoded                ; Auto          ; --          ; --         ;
+; STATE_MACHINE_PROCESSING                   ; User-Encoded                    ; Auto          ; --          ; --         ;
-; SYNTH_MESSAGE_LEVEL                        ; High                        ; Medium        ; --          ; --         ;
+; SYNTH_MESSAGE_LEVEL                        ; High                            ; Medium        ; --          ; --         ;
-; SYNTH_TIMING_DRIVEN_SYNTHESIS              ; Off                         ; --            ; --          ; --         ;
+; SYNTH_TIMING_DRIVEN_SYNTHESIS              ; Off                             ; --            ; --          ; --         ;
-+--------------------------------------------+-----------------------------+---------------+-------------+------------+
++--------------------------------------------+---------------------------------+---------------+-------------+------------+
 
 
 +-------------------------------------------------------------------------------------------------------------------------------+
@@ -97,24 +97,24 @@ applicable agreement for further details.
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:08     ; 1.0                     ; 303 MB              ; 00:00:08                           ;
+; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 4587 MB             ; 00:00:01                           ;
-; Fitter                    ; 00:00:04     ; 1.0                     ; 287 MB              ; 00:00:04                           ;
+; Fitter                    ; 00:00:00     ; 1.0                     ; 4708 MB             ; 00:00:01                           ;
-; Assembler                 ; 00:00:03     ; 1.0                     ; 275 MB              ; 00:00:02                           ;
+; Assembler                 ; 00:00:00     ; 1.0                     ; 4521 MB             ; 00:00:00                           ;
-; TimeQuest Timing Analyzer ; 00:00:06     ; 1.0                     ; 263 MB              ; 00:00:05                           ;
+; TimeQuest Timing Analyzer ; 00:00:01     ; 1.0                     ; 4530 MB             ; 00:00:00                           ;
-; Total                     ; 00:00:21     ; --                      ; --                  ; 00:00:19                           ;
+; Total                     ; 00:00:02     ; --                      ; --                  ; 00:00:02                           ;
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
-+-----------------------------------------------------------------------------------------+
++----------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                         ;
+; Flow OS Summary                                                                        ;
-+---------------------------+------------------+------------+------------+----------------+
++---------------------------+------------------+-----------+------------+----------------+
-; Module Name               ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
-+---------------------------+------------------+------------+------------+----------------+
++---------------------------+------------------+-----------+------------+----------------+
-; Analysis & Synthesis      ; zane-f8c4ec68a5  ; Windows XP ; 5.1        ; i686           ;
+; Analysis & Synthesis      ; DESKTOP-G62HNQS  ; Windows 7 ; 6.2        ; x86_64         ;
-; Fitter                    ; zane-f8c4ec68a5  ; Windows XP ; 5.1        ; i686           ;
+; Fitter                    ; DESKTOP-G62HNQS  ; Windows 7 ; 6.2        ; x86_64         ;
-; Assembler                 ; zane-f8c4ec68a5  ; Windows XP ; 5.1        ; i686           ;
+; Assembler                 ; DESKTOP-G62HNQS  ; Windows 7 ; 6.2        ; x86_64         ;
-; TimeQuest Timing Analyzer ; zane-f8c4ec68a5  ; Windows XP ; 5.1        ; i686           ;
+; TimeQuest Timing Analyzer ; DESKTOP-G62HNQS  ; Windows 7 ; 6.2        ; x86_64         ;
-+---------------------------+------------------+------------+------------+----------------+
++---------------------------+------------------+-----------+------------+----------------+
 
 
 ------------

cpld/output_files/GR8RAM.jdi

@@ -1,6 +1,6 @@
 <sld_project_info>
   <project>
-    <hash md5_digest_80b="4117e9f02d3732265fc4"/>
+    <hash md5_digest_80b="6680f745e8da7e3a7216"/>
   </project>
   <file_info>
     <file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>

cpld/output_files/GR8RAM.map.rpt

@@ -1,6 +1,6 @@
 Analysis & Synthesis report for GR8RAM
-Mon Sep 02 20:55:48 2019
+Tue Sep 03 14:09:16 2019
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -9,14 +9,17 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
   1. Legal Notice
   2. Analysis & Synthesis Summary
   3. Analysis & Synthesis Settings
-  4. Analysis & Synthesis Source Files Read
+  4. Parallel Compilation
-  5. Analysis & Synthesis Resource Usage Summary
+  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Utilization by Entity
+  6. Analysis & Synthesis Resource Usage Summary
-  7. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0
+  7. Analysis & Synthesis Resource Utilization by Entity
-  8. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0
+  8. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0
-  9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3
+  9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0
- 10. Analysis & Synthesis Messages
+ 10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4
- 11. Analysis & Synthesis Suppressed Messages
+ 11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3
+ 12. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5
+ 13. Analysis & Synthesis Messages
+ 14. Analysis & Synthesis Suppressed Messages
 
 
 
@@ -42,13 +45,13 @@ applicable agreement for further details.
 +-------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                  ;
 +-----------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Mon Sep 02 20:55:48 2019           ;
+; Analysis & Synthesis Status ; Successful - Tue Sep 03 14:09:16 2019           ;
-; Quartus II 32-bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Quartus II 64-Bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
 ; Revision Name               ; GR8RAM                                          ;
 ; Top-level Entity Name       ; GR8RAM                                          ;
 ; Family                      ; MAX7000S                                        ;
-; Total macrocells            ; 102                                             ;
+; Total macrocells            ; 103                                             ;
-; Total pins                  ; 63                                              ;
+; Total pins                  ; 61                                              ;
 +-----------------------------+-------------------------------------------------+
 
 
@@ -116,12 +119,23 @@ applicable agreement for further details.
 +----------------------------------------------------------------------------+-----------------+---------------+
 
 
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 8      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 ; Analysis & Synthesis Source Files Read                                                                                                                            ;
 +----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
 ; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                              ; Library ;
 +----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
-; GR8RAM.v                         ; yes             ; User Verilog HDL File  ; Z:/Repos/GR8RAM/cpld/GR8RAM.v                                             ;         ;
+; GR8RAM.v                         ; yes             ; User Verilog HDL File  ; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v                       ;         ;
 ; lpm_counter.tdf                  ; yes             ; Megafunction           ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf         ;         ;
 ; lpm_constant.inc                 ; yes             ; Megafunction           ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc        ;         ;
 ; lpm_decode.inc                   ; yes             ; Megafunction           ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc          ;         ;
@@ -151,13 +165,14 @@ applicable agreement for further details.
 +----------------------+----------------------+
 ; Resource             ; Usage                ;
 +----------------------+----------------------+
-; Logic cells          ; 102                  ;
+; Logic cells          ; 103                  ;
-; Total registers      ; 50                   ;
+; Total registers      ; 52                   ;
-; I/O pins             ; 63                   ;
+; I/O pins             ; 61                   ;
+; Shareable expanders  ; 1                    ;
 ; Maximum fan-out node ; nRES                 ;
-; Maximum fan-out      ; 50                   ;
+; Maximum fan-out      ; 52                   ;
-; Total fan-out        ; 971                  ;
+; Total fan-out        ; 830                  ;
-; Average fan-out      ; 5.88                 ;
+; Average fan-out      ; 5.03                 ;
 +----------------------+----------------------+
 
 
@@ -166,7 +181,7 @@ applicable agreement for further details.
 +----------------------------+------------+------+-------------------------------+--------------+
 ; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name           ; Library Name ;
 +----------------------------+------------+------+-------------------------------+--------------+
-; |GR8RAM                    ; 102        ; 63   ; |GR8RAM                       ; work         ;
+; |GR8RAM                    ; 103        ; 61   ; |GR8RAM                       ; work         ;
 ;    |lpm_counter:Ref_rtl_0| ; 4          ; 0    ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work         ;
 +----------------------------+------------+------+-------------------------------+--------------+
 
@@ -227,11 +242,11 @@ Note: In order to hide this table in the UI and the text report file, please set
 
 
 +-------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3 ;
+; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4 ;
 +------------------------+-------------+----------------------------+
 ; Parameter Name         ; Value       ; Type                       ;
 +------------------------+-------------+----------------------------+
-; LPM_WIDTH              ; 23          ; Untyped                    ;
+; LPM_WIDTH              ; 8           ; Untyped                    ;
 ; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                    ;
 ; LPM_DIRECTION          ; ADD         ; Untyped                    ;
 ; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                    ;
@@ -245,7 +260,63 @@ Note: In order to hide this table in the UI and the text report file, please set
 ; DEVICE_FAMILY          ; MAX7000S    ; Untyped                    ;
 ; USE_WYS                ; OFF         ; Untyped                    ;
 ; STYLE                  ; FAST        ; Untyped                    ;
-; CBXI_PARAMETER         ; add_sub_8ph ; Untyped                    ;
+; CBXI_PARAMETER         ; add_sub_rnh ; Untyped                    ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                 ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY               ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE               ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE             ;
++------------------------+-------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3 ;
++------------------------+-------------+----------------------------+
+; Parameter Name         ; Value       ; Type                       ;
++------------------------+-------------+----------------------------+
+; LPM_WIDTH              ; 8           ; Untyped                    ;
+; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                    ;
+; LPM_DIRECTION          ; ADD         ; Untyped                    ;
+; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                    ;
+; LPM_PIPELINE           ; 0           ; Untyped                    ;
+; MAXIMIZE_SPEED         ; 5           ; Untyped                    ;
+; REGISTERED_AT_END      ; 0           ; Untyped                    ;
+; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                    ;
+; USE_CS_BUFFERS         ; 1           ; Untyped                    ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                    ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH         ;
+; DEVICE_FAMILY          ; MAX7000S    ; Untyped                    ;
+; USE_WYS                ; OFF         ; Untyped                    ;
+; STYLE                  ; FAST        ; Untyped                    ;
+; CBXI_PARAMETER         ; add_sub_rnh ; Untyped                    ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                 ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY               ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE               ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE             ;
++------------------------+-------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5 ;
++------------------------+-------------+----------------------------+
+; Parameter Name         ; Value       ; Type                       ;
++------------------------+-------------+----------------------------+
+; LPM_WIDTH              ; 7           ; Untyped                    ;
+; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                    ;
+; LPM_DIRECTION          ; ADD         ; Untyped                    ;
+; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                    ;
+; LPM_PIPELINE           ; 0           ; Untyped                    ;
+; MAXIMIZE_SPEED         ; 5           ; Untyped                    ;
+; REGISTERED_AT_END      ; 0           ; Untyped                    ;
+; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                    ;
+; USE_CS_BUFFERS         ; 1           ; Untyped                    ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                    ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH         ;
+; DEVICE_FAMILY          ; MAX7000S    ; Untyped                    ;
+; USE_WYS                ; OFF         ; Untyped                    ;
+; STYLE                  ; FAST        ; Untyped                    ;
+; CBXI_PARAMETER         ; add_sub_qnh ; Untyped                    ;
 ; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                 ;
 ; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY               ;
 ; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE               ;
@@ -258,23 +329,27 @@ Note: In order to hide this table in the UI and the text report file, please set
 ; Analysis & Synthesis Messages ;
 +-------------------------------+
 Info: *******************************************************************
-Info: Running Quartus II 32-bit Analysis & Synthesis
+Info: Running Quartus II 64-Bit Analysis & Synthesis
     Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Mon Sep 02 20:55:40 2019
+    Info: Processing started: Tue Sep 03 14:09:15 2019
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
 Warning (20028): Parallel compilation is not licensed and has been disabled
 Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
     Info (12023): Found entity 1: GR8RAM
 Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (3)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (3)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(136): truncated value with size 32 to match size of target (4)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (4)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(160): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(163): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(168): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (7)
 Info (19000): Inferred 1 megafunctions from design logic
     Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0"
-Info (278001): Inferred 2 megafunctions from design logic
+Info (278001): Inferred 4 megafunctions from design logic
     Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add0"
+    Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add4"
     Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add3"
+    Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add5"
 Info (12130): Elaborated megafunction instantiation "lpm_counter:Ref_rtl_0"
 Info (12133): Instantiated megafunction "lpm_counter:Ref_rtl_0" with the following parameter:
     Info (12134): Parameter "LPM_WIDTH" = "4"
@@ -292,17 +367,19 @@ Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:ad
 Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|look_add:look_ahead_unit", which is child of megafunction instantiation "lpm_add_sub:Add0"
 Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
 Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
-Info (12130): Elaborated megafunction instantiation "lpm_add_sub:Add3"
+Info (12130): Elaborated megafunction instantiation "lpm_add_sub:Add5"
-Info (12133): Instantiated megafunction "lpm_add_sub:Add3" with the following parameter:
+Info (12133): Instantiated megafunction "lpm_add_sub:Add5" with the following parameter:
-    Info (12134): Parameter "LPM_WIDTH" = "23"
+    Info (12134): Parameter "LPM_WIDTH" = "7"
     Info (12134): Parameter "LPM_DIRECTION" = "ADD"
     Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
     Info (12134): Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
-Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add3|addcore:adder[2]", which is child of megafunction instantiation "lpm_add_sub:Add3"
+Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add5|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add5"
-Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add3|look_add:look_ahead_unit", which is child of megafunction instantiation "lpm_add_sub:Add3"
+Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add5|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add5"
-Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add3|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add3"
+Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add5"
-Info (13014): Ignored 31 buffer(s)
+Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add5|addcore:adder|addcore:adder[0]", which is child of megafunction instantiation "lpm_add_sub:Add5"
-    Info (13019): Ignored 31 SOFT buffer(s)
+Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add5|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add5"
+Info (13014): Ignored 32 buffer(s)
+    Info (13019): Ignored 32 SOFT buffer(s)
 Info (280013): Promoted pin-driven signal(s) to global signal
     Info (280014): Promoted clock signal driven by pin "C7M" to global clock signal
     Info (280015): Promoted clear signal driven by pin "nRES" to global clear signal
@@ -317,20 +394,21 @@ Warning (21074): Design contains 8 input pin(s) that do not drive logic
     Warning (15610): No output dependent on input pin "A[15]"
 Info (21057): Implemented 165 device resources after synthesis - the final resource count might be different
     Info (21058): Implemented 27 input pins
-    Info (21059): Implemented 20 output pins
+    Info (21059): Implemented 18 output pins
     Info (21060): Implemented 16 bidirectional pins
-    Info (21063): Implemented 102 macrocells
+    Info (21063): Implemented 103 macrocells
-Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
+    Info (21073): Implemented 1 shareable expanders
-Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 14 warnings
+Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg
-    Info: Peak virtual memory: 303 megabytes
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings
-    Info: Processing ended: Mon Sep 02 20:55:48 2019
+    Info: Peak virtual memory: 4587 megabytes
-    Info: Elapsed time: 00:00:08
+    Info: Processing ended: Tue Sep 03 14:09:16 2019
-    Info: Total CPU time (on all processors): 00:00:08
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
 
 
 +------------------------------------------+
 ; Analysis & Synthesis Suppressed Messages ;
 +------------------------------------------+
-The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
+The suppressed messages can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
 
 

cpld/output_files/GR8RAM.map.smsg

@@ -1,3 +1,3 @@
-Warning (10273): Verilog HDL warning at GR8RAM.v(41): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at GR8RAM.v(38): extended using "x" or "z"
-Warning (10273): Verilog HDL warning at GR8RAM.v(49): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at GR8RAM.v(46): extended using "x" or "z"
-Warning (10268): Verilog HDL information at GR8RAM.v(176): always construct contains both blocking and non-blocking assignments
+Warning (10268): Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments

cpld/output_files/GR8RAM.map.summary

@@ -1,7 +1,7 @@
-Analysis & Synthesis Status : Successful - Mon Sep 02 20:55:48 2019
+Analysis & Synthesis Status : Successful - Tue Sep 03 14:09:16 2019
-Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
 Revision Name : GR8RAM
 Top-level Entity Name : GR8RAM
 Family : MAX7000S
-Total macrocells : 102
+Total macrocells : 103
-Total pins : 63
+Total pins : 61

cpld/output_files/GR8RAM.pin

@@ -56,7 +56,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 CHIP  "GR8RAM"  ASSIGNED TO AN: EPM7128SLC84-15
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
@@ -90,8 +90,8 @@ VCCIO                        : 26        : power  :                   : 5.0V
 D[6]                         : 27        : bidir  : TTL               :         :           : Y              
 D[5]                         : 28        : bidir  : TTL               :         :           : Y              
 D[4]                         : 29        : bidir  : TTL               :         :           : Y              
-PHI1out                      : 30        : output : TTL               :         :           : Y              
+RESERVED                     : 30        :        :                   :         :           :                
-C7Mout                       : 31        : output : TTL               :         :           : Y              
+RESERVED                     : 31        :        :                   :         :           :                
 GND                          : 32        : gnd    :                   :         :           :                
 D[3]                         : 33        : bidir  : TTL               :         :           : Y              
 D[2]                         : 34        : bidir  : TTL               :         :           : Y              

cpld/output_files/GR8RAM.sta.summary

@@ -3,8 +3,8 @@ TimeQuest Timing Analyzer Summary
 ------------------------------------------------------------
 
 Type  : Setup 'C7M'
-Slack : -47.000
+Slack : -47.500
-TNS   : -1816.000
+TNS   : -1888.500
 
 Type  : Setup 'C7M_2'
 Slack : -27.500
@@ -24,6 +24,6 @@ TNS   : -22.000
 
 Type  : Minimum Pulse Width 'C7M'
 Slack : -4.500
-TNS   : -432.000
+TNS   : -450.000
 
 ------------------------------------------------------------