mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-12-12 08:30:08 +00:00
Merge branch 'dev' of https://github.com/ZaneKaminski/GR8RAM into dev
This commit is contained in:
Zane Kaminski
commit
6e6813786d
@ -161,4 +161,5 @@ set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1reg
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b0_MC
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to IOROMEN
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set_location_assignment PIN_44 -to nMode
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set_location_assignment PIN_44 -to nMode
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to RAMSEL_MC
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BIN
cpld/GR8RAM.qws
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cpld/GR8RAM.qws
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@ -39,7 +39,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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wire AddrMSELA = A[3:0]==4'h1;
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wire AddrLSELA = A[3:0]==4'h0;
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LCELL BankWR_MC (.in(BankSELA & ~nWE & ~nDEVSEL & REGEN), .out(BankWR)); wire BankWR;
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wire SetWR = SetSELA & ~nWE & ~nDEVSEL & REGEN;
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LCELL SetWR_MC (.in(SetSELA & ~nWE & ~nDEVSEL & REGEN), .out(SetWR)); wire SetWR;
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LCELL RAMSEL_MC (.in(RAMSELA & ~nDEVSEL & REGEN), .out(RAMSEL)); wire RAMSEL;
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LCELL AddrHWR_MC (.in(AddrHSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrHWR)); wire AddrHWR;
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LCELL AddrMWR_MC (.in(AddrMSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrMWR)); wire AddrMWR;
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@ -77,6 +77,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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reg IncAddrL = 0, IncAddrM = 0, IncAddrH = 0;
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/* CAS rising/falling edge components */
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// These are combined to create the CAS outputs.
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reg CASr = 0, CAS0f = 0, CAS1f = 0;
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reg RASr = 0, RASf = 0;
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reg ASel = 0; // DRAM address multiplexer select
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@ -136,6 +137,15 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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REGEN <= 0;
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IOROMEN <= 0;
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end else begin
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// Synchronize state counter to S1 when just entering PHI1
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PHI1reg <= PHI1; // Save old PHI1
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if (~PHI1) PHI0seen <= 1; // PHI0seen set in PHI0
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S <= (PHI1 & ~PHI1reg & PHI0seen) ? 4'h1 :
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S==0 ? 3'h0 :
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S==7 ? 3'h7 : S+1;
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// Refresh counter allows DRAM refresh once every 13 cycles
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if (S==3) Ref <= (Ref[3:2] == 2'b11) ? 4'h0 : Ref+1;
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// Disable IOSTRB ROM when accessing 0xCFFF.
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if (S==3 & ~nIOSTRB & A[10:0]==11'h7FF) IOROMEN <= 1'b0;
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@ -1,5 +1,5 @@
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571425321919 ""}
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||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571425321919 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 18 15:02:01 2019 " "Processing started: Fri Oct 18 15:02:01 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571425321919 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571425321919 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571425321919 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571425324153 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571425324622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 18 15:02:04 2019 " "Processing ended: Fri Oct 18 15:02:04 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571425324622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571425324622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571425324622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571425324622 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571624522334 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571624522335 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:22:02 2019 " "Processing started: Sun Oct 20 22:22:02 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571624522335 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571624522335 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571624522335 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571624522453 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571624522603 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:22:02 2019 " "Processing ended: Sun Oct 20 22:22:02 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571624522603 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571624522603 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571624522603 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571624522603 ""}
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@ -1,3 +1,3 @@
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Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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||||
Version_Index = 302049280
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Creation_Time = Fri Oct 18 15:01:17 2019
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||||
Creation_Time = Sun Oct 20 21:50:21 2019
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||||
|
||||
@ -1,3 +1,3 @@
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571425319684 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571425319700 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571425320231 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 18 15:02:00 2019 " "Processing ended: Fri Oct 18 15:02:00 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571425320231 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571425320231 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571425320231 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571425320231 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571624521309 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571624521311 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571624521519 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:22:01 2019 " "Processing ended: Sun Oct 20 22:22:01 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571624521519 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571624521519 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571624521519 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571624521519 ""}
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||||
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||||
@ -28,35 +28,35 @@ A[0] => Equal2.IN7
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A[0] => Equal3.IN7
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A[0] => Equal4.IN7
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A[0] => Equal5.IN7
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A[0] => Equal10.IN21
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A[0] => Equal12.IN21
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A[1] => Equal0.IN6
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A[1] => Equal1.IN6
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A[1] => Equal2.IN6
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A[1] => Equal3.IN6
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A[1] => Equal4.IN6
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A[1] => Equal5.IN6
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||||
A[1] => Equal10.IN20
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||||
A[1] => Equal12.IN20
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||||
A[2] => Equal0.IN5
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A[2] => Equal1.IN5
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A[2] => Equal2.IN5
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||||
A[2] => Equal3.IN5
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||||
A[2] => Equal4.IN5
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||||
A[2] => Equal5.IN5
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||||
A[2] => Equal10.IN19
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||||
A[2] => Equal12.IN19
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||||
A[3] => Equal0.IN4
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||||
A[3] => Equal1.IN4
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||||
A[3] => Equal2.IN4
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||||
A[3] => Equal3.IN4
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||||
A[3] => Equal4.IN4
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||||
A[3] => Equal5.IN4
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||||
A[3] => Equal10.IN18
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||||
A[4] => Equal10.IN17
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||||
A[5] => Equal10.IN16
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||||
A[6] => Equal10.IN15
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||||
A[7] => Equal10.IN14
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||||
A[8] => Equal10.IN13
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||||
A[9] => Equal10.IN12
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||||
A[10] => Equal10.IN11
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||||
A[3] => Equal12.IN18
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||||
A[4] => Equal12.IN17
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||||
A[5] => Equal12.IN16
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||||
A[6] => Equal12.IN15
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||||
A[7] => Equal12.IN14
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||||
A[8] => Equal12.IN13
|
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A[9] => Equal12.IN12
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||||
A[10] => Equal12.IN11
|
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A[11] => ~NO_FANOUT~
|
||||
A[12] => ~NO_FANOUT~
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A[13] => ~NO_FANOUT~
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@ -79,9 +79,13 @@ nWE => comb.IN0
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nWE => comb.IN0
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nWE => comb.IN0
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nWE => comb.IN0
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nWE => comb.IN0
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nWE => comb.IN1
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nWE => RASr.IN1
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nWE => ASel.IN0
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nWE => CASr.IN1
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nWE => CAS0f.IN1
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nWE => CAS1f.IN1
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D[0] <> D[0]
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D[1] <> D[1]
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D[2] <> D[2]
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@ -109,11 +113,9 @@ nDEVSEL => comb.IN0
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nIOSEL => RA.IN1
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nIOSEL => RA.IN0
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nIOSEL => comb.IN0
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nIOSEL => comb.IN1
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nIOSTRB => RA.IN0
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nIOSTRB => RA.IN1
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nIOSTRB => RA.IN1
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nIOSTRB => comb.IN1
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nINH <= nINH.DB_MAX_OUTPUT_PORT_TYPE
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nRAS <= comb.DB_MAX_OUTPUT_PORT_TYPE
|
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nCAS0 <= comb.DB_MAX_OUTPUT_PORT_TYPE
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@ -1,33 +1,33 @@
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571425306699 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571425306715 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 18 15:01:46 2019 " "Processing started: Fri Oct 18 15:01:46 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571425306715 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571425306715 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571425306715 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571425310715 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571425310840 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571425310840 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(191) " "Verilog HDL information at GR8RAM.v(191): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 191 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1571425310840 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571425310856 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571425310856 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571425311215 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571425311215 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(123) " "Verilog HDL assignment warning at GR8RAM.v(123): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 123 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571425311215 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(128) " "Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 128 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571425311215 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(160) " "Verilog HDL assignment warning at GR8RAM.v(160): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571425311215 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(165) " "Verilog HDL assignment warning at GR8RAM.v(165): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 165 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571425311215 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(171) " "Verilog HDL assignment warning at GR8RAM.v(171): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 171 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571425311215 "|GR8RAM"}
|
||||
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425311543 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571425311543 ""}
|
||||
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425311559 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 165 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425311559 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 160 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425311559 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 171 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425311559 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571425311559 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425311965 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425311965 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425311965 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425311965 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571425311965 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425312246 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312246 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312246 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312246 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312246 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571425312246 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312465 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312653 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312653 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425312903 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425313121 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571425313121 ""}
|
||||
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1571425313559 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1571425313559 ""}
|
||||
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1571425313762 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1571425313762 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1571425313762 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "9 " "Design contains 9 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "C7M_2 " "No output dependent on input pin \"C7M_2\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|C7M_2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571425314121 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1571425314121 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "167 " "Implemented 167 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571425314137 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571425314137 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1571425314137 ""} { "Info" "ICUT_CUT_TM_MCELLS" "105 " "Implemented 105 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1571425314137 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1571425314137 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571425314137 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1571425314418 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "308 " "Peak virtual memory: 308 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571425314559 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 18 15:01:54 2019 " "Processing ended: Fri Oct 18 15:01:54 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571425314559 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571425314559 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571425314559 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571425314559 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571624519346 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571624519347 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:21:59 2019 " "Processing started: Sun Oct 20 22:21:59 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571624519347 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571624519347 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571624519347 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571624519549 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571624519575 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571624519575 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(190) " "Verilog HDL information at GR8RAM.v(190): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 190 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1571624519575 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571624519576 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571624519576 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571624519612 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571624519617 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(122) " "Verilog HDL assignment warning at GR8RAM.v(122): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 122 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571624519619 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(127) " "Verilog HDL assignment warning at GR8RAM.v(127): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 127 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571624519619 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(159) " "Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571624519620 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(164) " "Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571624519620 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(170) " "Verilog HDL assignment warning at GR8RAM.v(170): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 170 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571624519620 "|GR8RAM"}
|
||||
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519747 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571624519747 ""}
|
||||
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519747 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519747 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519747 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 170 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519747 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571624519747 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519772 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519772 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519772 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519772 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571624519772 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519789 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519789 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519789 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519789 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519789 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571624519789 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519803 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519813 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519815 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519828 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519839 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519840 ""}
|
||||
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1571624519917 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1571624519917 ""}
|
||||
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1571624520013 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1571624520013 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1571624520013 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "9 " "Design contains 9 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "C7M_2 " "No output dependent on input pin \"C7M_2\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|C7M_2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1571624520210 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "168 " "Implemented 168 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571624520210 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571624520210 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1571624520210 ""} { "Info" "ICUT_CUT_TM_MCELLS" "106 " "Implemented 106 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1571624520210 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1571624520210 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571624520210 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1571624520252 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571624520292 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:22:00 2019 " "Processing ended: Sun Oct 20 22:22:00 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571624520292 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571624520292 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571624520292 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571624520292 ""}
|
||||
|
||||
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|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571425328372 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571425328388 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 18 15:02:06 2019 " "Processing started: Fri Oct 18 15:02:06 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571425328388 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571425328388 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571425328388 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571425328497 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571425330310 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571425330325 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571425330325 ""}
|
||||
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1571425330403 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571425330450 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571425330450 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330450 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330450 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571425330466 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1571425330560 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -2169.500 C7M " " -47.500 -2169.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 5.000 " "Worst-case hold slack is 5.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571425330575 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571425330622 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571425330638 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.500 " "Worst-case minimum pulse width slack is -4.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330653 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330653 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -486.000 C7M " " -4.500 -486.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571425330653 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571425330653 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1571425330794 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571425330872 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571425330872 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "259 " "Peak virtual memory: 259 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571425331044 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 18 15:02:11 2019 " "Processing ended: Fri Oct 18 15:02:11 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571425331044 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571425331044 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571425331044 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571425331044 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571624523519 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523519 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:22:03 2019 " "Processing started: Sun Oct 20 22:22:03 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571624523519 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571624523519 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571624523520 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571624523576 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571624523668 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571624523675 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571624523678 ""}
|
||||
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1571624523705 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571624523717 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571624523717 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523718 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523718 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571624523720 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1571624523730 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523734 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523734 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -2091.500 C7M " " -47.500 -2091.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523734 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571624523734 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 5.000 " "Worst-case hold slack is 5.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523898 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571624523898 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571624523903 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571624523908 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.500 " "Worst-case minimum pulse width slack is -4.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523913 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523913 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -486.000 C7M " " -4.500 -486.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523913 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571624523913 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1571624523954 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571624523975 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571624523976 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4541 " "Peak virtual memory: 4541 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571624524127 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:22:04 2019 " "Processing ended: Sun Oct 20 22:22:04 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571624524127 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571624524127 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571624524127 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571624524127 ""}
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
start_full_compilation:s:00:00:26
|
||||
start_analysis_synthesis:s:00:00:10-start_full_compilation
|
||||
start_full_compilation:s:00:00:05
|
||||
start_analysis_synthesis:s:00:00:01-start_full_compilation
|
||||
start_analysis_elaboration:s-start_full_compilation
|
||||
start_fitter:s:00:00:05-start_full_compilation
|
||||
start_assembler:s:00:00:05-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:06-start_full_compilation
|
||||
start_fitter:s:00:00:02-start_full_compilation
|
||||
start_assembler:s:00:00:01-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:01-start_full_compilation
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
|
||||
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ VERSION_END
|
||||
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
|
||||
@ -1,72 +1,71 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567909235870 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909235870 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:20:35 2019 " "Processing started: Sat Sep 07 22:20:35 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909235870 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567909235870 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567909235870 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567909236067 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567909236087 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567909236087 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(190) " "Verilog HDL information at GR8RAM.v(190): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 190 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567909236087 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567909236087 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567909236087 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567909236207 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909236207 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(133) " "Verilog HDL assignment warning at GR8RAM.v(133): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 133 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909236207 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909236207 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(159) " "Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909236207 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(164) " "Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909236207 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(170) " "Verilog HDL assignment warning at GR8RAM.v(170): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 170 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909236207 "|GR8RAM"}
|
||||
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236297 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567909236297 ""}
|
||||
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236297 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236297 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236297 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 170 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236297 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567909236297 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236367 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236367 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567909236367 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236387 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236387 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236387 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236387 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236387 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567909236387 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236417 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236487 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236507 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236517 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236527 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236537 ""}
|
||||
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567909236674 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567909236674 ""}
|
||||
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 131 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1567909236681 ""}
|
||||
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567909236777 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567909236777 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567909236777 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567909236968 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "168 " "Implemented 168 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567909236968 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567909236968 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567909236968 ""} { "Info" "ICUT_CUT_TM_MCELLS" "105 " "Implemented 105 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567909236968 ""} { "Info" "ICUT_CUT_TM_SEXPS" "2 " "Implemented 2 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567909236968 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567909236968 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567909237078 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4586 " "Peak virtual memory: 4586 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909237128 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:20:37 2019 " "Processing ended: Sat Sep 07 22:20:37 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909237128 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909237128 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909237128 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567909237128 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567909238337 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909238337 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:20:37 2019 " "Processing started: Sat Sep 07 22:20:37 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909238337 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1567909238337 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1567909238337 ""}
|
||||
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1567909239087 ""}
|
||||
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1567909239087 ""}
|
||||
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1567909239087 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567909239177 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567909239187 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4709 " "Peak virtual memory: 4709 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909239487 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:20:39 2019 " "Processing ended: Sat Sep 07 22:20:39 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909239487 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909239487 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909239487 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567909239487 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1567909240407 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909240407 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:20:40 2019 " "Processing started: Sat Sep 07 22:20:40 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909240407 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567909240407 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567909240407 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567909240527 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4521 " "Peak virtual memory: 4521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909240697 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:20:40 2019 " "Processing ended: Sat Sep 07 22:20:40 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909240697 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909240697 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909240697 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567909240697 ""}
|
||||
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1567909241307 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1567909241748 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241748 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:20:41 2019 " "Processing started: Sat Sep 07 22:20:41 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909241748 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567909241748 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567909241748 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567909241819 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567909241914 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567909241914 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567909241924 ""}
|
||||
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567909241954 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567909241974 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567909241974 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241974 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241974 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241974 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567909241974 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567909241984 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.000 " "Worst-case setup slack is -47.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.000 -2056.000 C7M " " -47.000 -2056.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241994 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567909241994 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242004 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567909242004 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567909242004 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567909242014 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242014 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242014 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242014 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -468.000 C7M " " -4.500 -468.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242014 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567909242014 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567909242084 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567909242100 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567909242100 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909242170 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:20:42 2019 " "Processing ended: Sat Sep 07 22:20:42 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909242170 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909242170 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909242170 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567909242170 ""}
|
||||
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus II Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567909242810 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571623531253 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571623531253 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:05:31 2019 " "Processing started: Sun Oct 20 22:05:31 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571623531253 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571623531253 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571623531253 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571623531456 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571623531485 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571623531485 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(197) " "Verilog HDL information at GR8RAM.v(197): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 197 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1571623531485 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571623531487 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571623531487 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571623531521 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571623531523 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(129) " "Verilog HDL assignment warning at GR8RAM.v(129): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 129 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571623531523 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 134 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571623531523 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(166) " "Verilog HDL assignment warning at GR8RAM.v(166): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 166 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571623531523 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(171) " "Verilog HDL assignment warning at GR8RAM.v(171): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 171 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571623531523 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(177) " "Verilog HDL assignment warning at GR8RAM.v(177): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 177 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571623531523 "|GR8RAM"}
|
||||
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531597 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571623531597 ""}
|
||||
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531597 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 171 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531597 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 166 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531597 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 177 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531597 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571623531597 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531626 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531626 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531626 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531626 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571623531626 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531643 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531644 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531644 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531644 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531644 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571623531644 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531657 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531667 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531668 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531680 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531690 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531691 ""}
|
||||
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1571623531758 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1571623531758 ""}
|
||||
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1571623531853 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1571623531853 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1571623531853 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "9 " "Design contains 9 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "C7M_2 " "No output dependent on input pin \"C7M_2\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|C7M_2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1571623532033 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "168 " "Implemented 168 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571623532034 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571623532034 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1571623532034 ""} { "Info" "ICUT_CUT_TM_MCELLS" "106 " "Implemented 106 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1571623532034 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1571623532034 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571623532034 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1571623532078 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571623532115 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:05:32 2019 " "Processing ended: Sun Oct 20 22:05:32 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571623532115 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571623532115 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571623532115 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571623532115 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571623533057 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571623533058 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:05:32 2019 " "Processing started: Sun Oct 20 22:05:32 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571623533058 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1571623533058 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1571623533058 ""}
|
||||
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1571623533109 ""}
|
||||
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1571623533109 ""}
|
||||
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1571623533109 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571623533148 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571623533150 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571623533356 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:05:33 2019 " "Processing ended: Sun Oct 20 22:05:33 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571623533356 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571623533356 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571623533356 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571623533356 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1571623534188 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571623534188 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:05:34 2019 " "Processing started: Sun Oct 20 22:05:34 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571623534188 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571623534188 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571623534188 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571623534305 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571623534439 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:05:34 2019 " "Processing ended: Sun Oct 20 22:05:34 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571623534439 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571623534439 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571623534439 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571623534439 ""}
|
||||
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1571623535072 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1571623535392 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535392 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:05:35 2019 " "Processing started: Sun Oct 20 22:05:35 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571623535392 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571623535392 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571623535392 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571623535447 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571623535537 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571623535545 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571623535548 ""}
|
||||
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1571623535571 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571623535583 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571623535584 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535584 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535584 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571623535586 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1571623535595 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535600 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535600 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -2078.500 C7M " " -47.500 -2078.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535600 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571623535600 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 5.000 " "Worst-case hold slack is 5.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535763 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571623535763 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571623535769 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571623535773 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.500 " "Worst-case minimum pulse width slack is -4.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -486.000 C7M " " -4.500 -486.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535779 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571623535779 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1571623535819 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571623535842 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571623535843 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571623535997 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:05:35 2019 " "Processing ended: Sun Oct 20 22:05:35 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571623535997 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571623535997 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571623535997 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571623535997 ""}
|
||||
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 22 s " "Quartus II Full Compilation was successful. 0 errors, 22 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571623536620 ""}
|
||||
|
||||
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
Assembler report for GR8RAM
|
||||
Fri Oct 18 15:02:04 2019
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Sun Oct 20 22:22:02 2019
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -10,7 +10,7 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof
|
||||
5. Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof
|
||||
6. Assembler Messages
|
||||
|
||||
|
||||
@ -37,7 +37,7 @@ applicable agreement for further details.
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Fri Oct 18 15:02:04 2019 ;
|
||||
; Assembler Status ; Successful - Sun Oct 20 22:22:02 2019 ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX7000S ;
|
||||
@ -73,39 +73,39 @@ applicable agreement for further details.
|
||||
+-----------------------------------------------------------------------------+----------+---------------+
|
||||
|
||||
|
||||
+----------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+----------------------------------------------+
|
||||
; File Name ;
|
||||
+----------------------------------------------+
|
||||
; Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||
+----------------------------------------------+
|
||||
+--------------------------------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+--------------------------------------------------------------------+
|
||||
; File Name ;
|
||||
+--------------------------------------------------------------------+
|
||||
; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||
+--------------------------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------+
|
||||
; Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||
+----------------+-------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+-------------------------------------------------------+
|
||||
; Device ; EPM7128SLC84-15 ;
|
||||
; JTAG usercode ; 0x00000000 ;
|
||||
; Checksum ; 0x0017D399 ;
|
||||
+----------------+-------------------------------------------------------+
|
||||
+----------------------------------------------------------------------------------------------+
|
||||
; Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||
+----------------+-----------------------------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+-----------------------------------------------------------------------------+
|
||||
; Device ; EPM7128SLC84-15 ;
|
||||
; JTAG usercode ; 0x00000000 ;
|
||||
; Checksum ; 0x0017AD2A ;
|
||||
+----------------+-----------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
; Assembler Messages ;
|
||||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Assembler
|
||||
Info: Running Quartus II 64-Bit Assembler
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Fri Oct 18 15:02:01 2019
|
||||
Info: Processing started: Sun Oct 20 22:22:02 2019
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 277 megabytes
|
||||
Info: Processing ended: Fri Oct 18 15:02:04 2019
|
||||
Info: Elapsed time: 00:00:03
|
||||
Info: Total CPU time (on all processors): 00:00:03
|
||||
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 4522 megabytes
|
||||
Info: Processing ended: Sun Oct 20 22:22:02 2019
|
||||
Info: Elapsed time: 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
|
||||
|
||||
|
||||
@ -1 +1 @@
|
||||
Fri Oct 18 15:02:11 2019
|
||||
Sun Oct 20 22:22:04 2019
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Fitter report for GR8RAM
|
||||
Fri Oct 18 15:02:00 2019
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Sun Oct 20 22:22:01 2019
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -9,26 +9,27 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||
1. Legal Notice
|
||||
2. Fitter Summary
|
||||
3. Fitter Settings
|
||||
4. Pin-Out File
|
||||
5. Fitter Resource Usage Summary
|
||||
6. Input Pins
|
||||
7. Output Pins
|
||||
8. Bidir Pins
|
||||
9. All Package Pins
|
||||
10. I/O Standard
|
||||
11. Dedicated Inputs I/O
|
||||
12. Output Pin Default Load For Reported TCO
|
||||
13. Fitter Resource Utilization by Entity
|
||||
14. Control Signals
|
||||
15. Global & Other Fast Signals
|
||||
16. Non-Global High Fan-Out Signals
|
||||
17. Other Routing Usage Summary
|
||||
18. LAB External Interconnect
|
||||
19. LAB Macrocells
|
||||
20. Shareable Expander
|
||||
21. Logic Cell Interconnection
|
||||
22. Fitter Device Options
|
||||
23. Fitter Messages
|
||||
4. Parallel Compilation
|
||||
5. Pin-Out File
|
||||
6. Fitter Resource Usage Summary
|
||||
7. Input Pins
|
||||
8. Output Pins
|
||||
9. Bidir Pins
|
||||
10. All Package Pins
|
||||
11. I/O Standard
|
||||
12. Dedicated Inputs I/O
|
||||
13. Output Pin Default Load For Reported TCO
|
||||
14. Fitter Resource Utilization by Entity
|
||||
15. Control Signals
|
||||
16. Global & Other Fast Signals
|
||||
17. Non-Global High Fan-Out Signals
|
||||
18. Other Routing Usage Summary
|
||||
19. LAB External Interconnect
|
||||
20. LAB Macrocells
|
||||
21. Shareable Expander
|
||||
22. Logic Cell Interconnection
|
||||
23. Fitter Device Options
|
||||
24. Fitter Messages
|
||||
|
||||
|
||||
|
||||
@ -54,14 +55,14 @@ applicable agreement for further details.
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+---------------------------+-------------------------------------------------+
|
||||
; Fitter Status ; Successful - Fri Oct 18 15:02:00 2019 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Fitter Status ; Successful - Sun Oct 20 22:22:01 2019 ;
|
||||
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX7000S ;
|
||||
; Device ; EPM7128SLC84-15 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total macrocells ; 105 / 128 ( 82 % ) ;
|
||||
; Total macrocells ; 106 / 128 ( 83 % ) ;
|
||||
; Total pins ; 65 / 68 ( 96 % ) ;
|
||||
+---------------------------+-------------------------------------------------+
|
||||
|
||||
@ -86,10 +87,21 @@ applicable agreement for further details.
|
||||
+----------------------------------------------------------------------------+-----------------------+---------------+
|
||||
|
||||
|
||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||
+-------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+--------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+--------+
|
||||
; Number detected on machine ; 8 ;
|
||||
; Maximum allowed ; 1 ;
|
||||
+----------------------------+--------+
|
||||
|
||||
|
||||
+--------------+
|
||||
; Pin-Out File ;
|
||||
+--------------+
|
||||
The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||
The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||
|
||||
|
||||
+---------------------------------------------------+
|
||||
@ -97,9 +109,9 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||
+------------------------------+--------------------+
|
||||
; Resource ; Usage ;
|
||||
+------------------------------+--------------------+
|
||||
; Logic cells ; 105 / 128 ( 82 % ) ;
|
||||
; Logic cells ; 106 / 128 ( 83 % ) ;
|
||||
; Registers ; 54 / 128 ( 42 % ) ;
|
||||
; Number of pterms used ; 272 ;
|
||||
; Number of pterms used ; 274 ;
|
||||
; I/O pins ; 65 / 68 ( 96 % ) ;
|
||||
; -- Clock pins ; 2 / 2 ( 100 % ) ;
|
||||
; -- Dedicated input pins ; 2 / 2 ( 100 % ) ;
|
||||
@ -107,11 +119,11 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||
; Global signals ; 2 ;
|
||||
; Shareable expanders ; 1 / 128 ( < 1 % ) ;
|
||||
; Parallel expanders ; 0 / 120 ( 0 % ) ;
|
||||
; Cells using turbo bit ; 16 / 128 ( 13 % ) ;
|
||||
; Cells using turbo bit ; 17 / 128 ( 13 % ) ;
|
||||
; Maximum fan-out ; 54 ;
|
||||
; Highest non-global fan-out ; 53 ;
|
||||
; Total fan-out ; 866 ;
|
||||
; Average fan-out ; 5.06 ;
|
||||
; Highest non-global fan-out ; 54 ;
|
||||
; Total fan-out ; 864 ;
|
||||
; Average fan-out ; 5.02 ;
|
||||
+------------------------------+--------------------+
|
||||
|
||||
|
||||
@ -141,9 +153,9 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||
; PHI0in ; 8 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
|
||||
; PHI1in ; 2 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ;
|
||||
; Q3 ; 6 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
|
||||
; nDEVSEL ; 21 ; -- ; 2 ; 16 ; 0 ; no ; no ; TTL ; User ;
|
||||
; nIOSEL ; 74 ; -- ; 8 ; 13 ; 0 ; no ; no ; TTL ; User ;
|
||||
; nIOSTRB ; 24 ; -- ; 3 ; 12 ; 0 ; no ; no ; TTL ; User ;
|
||||
; nDEVSEL ; 21 ; -- ; 2 ; 15 ; 0 ; no ; no ; TTL ; User ;
|
||||
; nIOSEL ; 74 ; -- ; 8 ; 12 ; 0 ; no ; no ; TTL ; User ;
|
||||
; nIOSTRB ; 24 ; -- ; 3 ; 11 ; 0 ; no ; no ; TTL ; User ;
|
||||
; nMode ; 44 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ;
|
||||
; nRES ; 1 ; -- ; -- ; 54 ; 0 ; yes ; no ; TTL ; User ;
|
||||
; nWE ; 20 ; -- ; 2 ; 15 ; 0 ; no ; no ; TTL ; User ;
|
||||
@ -331,7 +343,7 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
+----------------------------+------------+------+-------------------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
|
||||
+----------------------------+------------+------+-------------------------------+--------------+
|
||||
; |GR8RAM ; 105 ; 65 ; |GR8RAM ; work ;
|
||||
; |GR8RAM ; 106 ; 65 ; |GR8RAM ; work ;
|
||||
; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ;
|
||||
+----------------------------+------------+------+-------------------------------+--------------+
|
||||
|
||||
@ -341,21 +353,15 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
+-----------+----------+---------+--------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+-----------+----------+---------+--------------+--------+----------------------+------------------+
|
||||
; A[0] ; PIN_75 ; 15 ; Clock enable ; no ; -- ; -- ;
|
||||
; A[1] ; PIN_76 ; 15 ; Clock enable ; no ; -- ; -- ;
|
||||
; A[2] ; PIN_77 ; 15 ; Clock enable ; no ; -- ; -- ;
|
||||
; A[3] ; PIN_79 ; 15 ; Clock enable ; no ; -- ; -- ;
|
||||
; BankWR_MC ; LC110 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; BankWR_MC ; LC44 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; C7M ; PIN_83 ; 54 ; Clock ; yes ; On ; -- ;
|
||||
; PHI1b9_MC ; LC41 ; 5 ; Clock enable ; no ; -- ; -- ;
|
||||
; REGEN ; LC98 ; 7 ; Clock enable ; no ; -- ; -- ;
|
||||
; S[0] ; LC128 ; 52 ; Clock enable ; no ; -- ; -- ;
|
||||
; S[1] ; LC118 ; 51 ; Clock enable ; no ; -- ; -- ;
|
||||
; S[2] ; LC113 ; 53 ; Clock enable ; no ; -- ; -- ;
|
||||
; nDEVSEL ; PIN_21 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
; nIOSEL ; PIN_74 ; 13 ; Clock enable ; no ; -- ; -- ;
|
||||
; PHI1b9_MC ; LC114 ; 5 ; Clock enable ; no ; -- ; -- ;
|
||||
; S[0] ; LC113 ; 52 ; Clock enable ; no ; -- ; -- ;
|
||||
; S[1] ; LC124 ; 51 ; Clock enable ; no ; -- ; -- ;
|
||||
; S[2] ; LC118 ; 54 ; Clock enable ; no ; -- ; -- ;
|
||||
; SetWR_MC ; LC35 ; 1 ; Clock enable ; no ; -- ; -- ;
|
||||
; nIOSEL ; PIN_74 ; 12 ; Clock enable ; no ; -- ; -- ;
|
||||
; nRES ; PIN_1 ; 54 ; Async. clear ; yes ; On ; -- ;
|
||||
; nWE ; PIN_20 ; 15 ; Clock enable ; no ; -- ; -- ;
|
||||
+-----------+----------+---------+--------------+--------+----------------------+------------------+
|
||||
|
||||
|
||||
@ -374,17 +380,17 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
+-------------------------------+---------+
|
||||
; Name ; Fan-Out ;
|
||||
+-------------------------------+---------+
|
||||
; S[2] ; 53 ;
|
||||
; S[2] ; 54 ;
|
||||
; S[0] ; 52 ;
|
||||
; S[1] ; 51 ;
|
||||
; nDEVSEL ; 16 ;
|
||||
; nDEVSEL ; 15 ;
|
||||
; nWE ; 15 ;
|
||||
; A[3] ; 15 ;
|
||||
; A[2] ; 15 ;
|
||||
; A[1] ; 15 ;
|
||||
; A[0] ; 15 ;
|
||||
; nIOSEL ; 13 ;
|
||||
; nIOSTRB ; 12 ;
|
||||
; nIOSEL ; 12 ;
|
||||
; nIOSTRB ; 11 ;
|
||||
; Addr[8] ; 11 ;
|
||||
; Addr[0] ; 11 ;
|
||||
; ASel ; 11 ;
|
||||
@ -399,15 +405,15 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
; Addr[2] ; 9 ;
|
||||
; AddrLWR_MC ; 9 ;
|
||||
; AddrMWR_MC ; 9 ;
|
||||
; RAMSEL_MC ; 9 ;
|
||||
; D[7]~7 ; 8 ;
|
||||
; FullIOEN ; 8 ;
|
||||
; Addr[11] ; 8 ;
|
||||
; Addr[18] ; 8 ;
|
||||
; Addr[3] ; 8 ;
|
||||
; Bank[0] ; 8 ;
|
||||
; BankWR_MC ; 8 ;
|
||||
; AddrHWR_MC ; 8 ;
|
||||
; BankWR_MC ; 8 ;
|
||||
; RAMSEL_MC ; 8 ;
|
||||
; RDOE~1 ; 8 ;
|
||||
; DOE~5 ; 8 ;
|
||||
; Addr[22] ; 7 ;
|
||||
@ -417,8 +423,8 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
; Bank[1] ; 7 ;
|
||||
; lpm_counter:Ref_rtl_0|dffs[3] ; 7 ;
|
||||
; lpm_counter:Ref_rtl_0|dffs[2] ; 7 ;
|
||||
; REGEN ; 7 ;
|
||||
; lpm_counter:Ref_rtl_0|dffs[0] ; 7 ;
|
||||
; REGEN ; 7 ;
|
||||
; D[6]~6 ; 6 ;
|
||||
; D[5]~5 ; 6 ;
|
||||
; D[4]~4 ; 6 ;
|
||||
@ -464,27 +470,29 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
; A[5] ; 1 ;
|
||||
; A[4] ; 1 ;
|
||||
; ~VCC~0 ; 1 ;
|
||||
; RA~120 ; 1 ;
|
||||
; RA~108 ; 1 ;
|
||||
; RA~101 ; 1 ;
|
||||
; RA~94 ; 1 ;
|
||||
; RA~87 ; 1 ;
|
||||
; RA~121 ; 1 ;
|
||||
; RA~109 ; 1 ;
|
||||
; RA~102 ; 1 ;
|
||||
; RA~95 ; 1 ;
|
||||
; RA~88 ; 1 ;
|
||||
; RA~81 ; 1 ;
|
||||
; RA~80 ; 1 ;
|
||||
; RA~79 ; 1 ;
|
||||
; RA~73 ; 1 ;
|
||||
; RA~74 ; 1 ;
|
||||
; Bank[7] ; 1 ;
|
||||
; IncAddrM~9 ; 1 ;
|
||||
; comb~38 ; 1 ;
|
||||
; comb~34 ; 1 ;
|
||||
; comb~30 ; 1 ;
|
||||
; CAS0f ; 1 ;
|
||||
; CAS1f ; 1 ;
|
||||
; RA~68 ; 1 ;
|
||||
; RA~65 ; 1 ;
|
||||
; RA~62 ; 1 ;
|
||||
; comb~31 ; 1 ;
|
||||
; RA~69 ; 1 ;
|
||||
; RA~66 ; 1 ;
|
||||
; RA~63 ; 1 ;
|
||||
; comb~27 ; 1 ;
|
||||
; RASr ; 1 ;
|
||||
; comb~25 ; 1 ;
|
||||
; RASf ; 1 ;
|
||||
; comb~29 ; 1 ;
|
||||
; SetWR_MC ; 1 ;
|
||||
; ASel~10 ; 1 ;
|
||||
; PHI1b8_MC ; 1 ;
|
||||
; PHI1b7_MC ; 1 ;
|
||||
; PHI1b6_MC ; 1 ;
|
||||
@ -492,7 +500,6 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
; PHI1b4_MC ; 1 ;
|
||||
; PHI1b3_MC ; 1 ;
|
||||
; PHI1b2_MC ; 1 ;
|
||||
; comb~25 ; 1 ;
|
||||
; PHI1b1_MC ; 1 ;
|
||||
; nWE~1 ; 1 ;
|
||||
; PHI1b0_MC ; 1 ;
|
||||
@ -521,15 +528,15 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
; Other Routing Resource Type ; Usage ;
|
||||
+-----------------------------+--------------------+
|
||||
; Output enables ; 2 / 6 ( 33 % ) ;
|
||||
; PIA buffers ; 206 / 288 ( 72 % ) ;
|
||||
; PIAs ; 241 / 288 ( 84 % ) ;
|
||||
; PIA buffers ; 227 / 288 ( 79 % ) ;
|
||||
; PIAs ; 255 / 288 ( 89 % ) ;
|
||||
+-----------------------------+--------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+
|
||||
; LAB External Interconnect ;
|
||||
+-----------------------------------------------+-----------------------------+
|
||||
; LAB External Interconnects (Average = 30.13) ; Number of LABs (Total = 8) ;
|
||||
; LAB External Interconnects (Average = 31.88) ; Number of LABs (Total = 8) ;
|
||||
+-----------------------------------------------+-----------------------------+
|
||||
; 0 - 2 ; 0 ;
|
||||
; 3 - 5 ; 0 ;
|
||||
@ -540,15 +547,16 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
; 18 - 20 ; 0 ;
|
||||
; 21 - 23 ; 0 ;
|
||||
; 24 - 26 ; 0 ;
|
||||
; 27 - 29 ; 3 ;
|
||||
; 27 - 29 ; 0 ;
|
||||
; 30 - 32 ; 5 ;
|
||||
; 33 - 35 ; 3 ;
|
||||
+-----------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; LAB Macrocells ;
|
||||
+-----------------------------------------+-----------------------------+
|
||||
; Number of Macrocells (Average = 13.13) ; Number of LABs (Total = 8) ;
|
||||
; Number of Macrocells (Average = 13.25) ; Number of LABs (Total = 8) ;
|
||||
+-----------------------------------------+-----------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
@ -559,14 +567,14 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 0 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 1 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 1 ;
|
||||
; 13 ; 0 ;
|
||||
; 12 ; 2 ;
|
||||
; 13 ; 1 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 0 ;
|
||||
; 16 ; 4 ;
|
||||
; 16 ; 3 ;
|
||||
+-----------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
@ -580,117 +588,118 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
+-------------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Logic Cell Interconnection ;
|
||||
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; LAB ; Logic Cell ; Input ; Output ;
|
||||
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[0], S[2], S[1], Addr[3], IncAddrL, Addr[2], Addr[1], Addr[0] ; Dout[3]~96, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~80 ;
|
||||
; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[0], S[2], S[1], Addr[1], IncAddrL, Addr[0] ; Dout[1]~84, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~120 ;
|
||||
; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[0], S[2], S[1], Addr[6], IncAddrL, Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[6]~114, Addr[6], Addr[7], IncAddrM, RA~101 ;
|
||||
; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], IncAddrM ; Dout[0]~78, Addr[8], Addr[9], Addr[10], Addr[11], RA~62, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
|
||||
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[0], S[2], S[1], Addr[4], IncAddrL, Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[4]~102, Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~87 ;
|
||||
; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[0], S[2], S[1], Addr[2], IncAddrL, Addr[1], Addr[0] ; Dout[2]~90, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~79 ;
|
||||
; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[0], S[2], S[1], Addr[0], IncAddrL ; Dout[0]~78, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~73 ;
|
||||
; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[0], S[2], S[1], Addr[5], IncAddrL, Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[5]~108, Addr[5], Addr[6], Addr[7], IncAddrM, RA~94 ;
|
||||
; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[0], S[2], S[1], Addr[7], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[7]~120, Addr[7], IncAddrM, RA~108 ;
|
||||
; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], IncAddrM, Addr[9], Addr[8] ; Dout[2]~90, Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], RA~68, Addr[15], IncAddrH ;
|
||||
; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], IncAddrM, Addr[8] ; Dout[1]~84, Addr[9], Addr[10], Addr[11], RA~65, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
|
||||
; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], IncAddrM, Addr[10], Addr[9], Addr[8] ; Dout[3]~96, Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~73 ;
|
||||
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], IncAddrM, Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[6]~114, Addr[14], Addr[15], IncAddrH, RA~80 ;
|
||||
; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], IncAddrM, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[7]~120, Addr[15], IncAddrH, RA~87 ;
|
||||
; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], IncAddrM, Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[5]~108, Addr[13], Addr[14], Addr[15], IncAddrH, RA~79 ;
|
||||
; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], IncAddrM, Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[4]~102, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~120 ;
|
||||
; B ; LC26 ; C7M, nRES, D[4], BankWR_MC, S[0], S[2], S[1] ; RA~87, RA~94, RA~101, RA~108 ;
|
||||
; B ; LC20 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[0], S[1], Addr[17], IncAddrH, Addr[16] ; Dout[1]~84, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~101 ;
|
||||
; B ; LC28 ; C7M, nRES, D[2], BankWR_MC, S[0], S[2], S[1] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108 ;
|
||||
; B ; LC24 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[0], S[1], Addr[18], IncAddrH, Addr[17], Addr[16] ; Dout[2]~90, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~108 ;
|
||||
; B ; LC25 ; C7M, nRES, D[1], BankWR_MC, S[0], S[2], S[1] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
|
||||
; B ; LC22 ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[0], S[1], Addr[22], IncAddrH, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[6]~114, Addr[22], CAS1f, CAS0f, comb~34, comb~38, Addr[23] ;
|
||||
; B ; LC19 ; C7M, nRES, D[6], BankWR_MC, S[0], S[2], S[1] ; RA~101, RA~108 ;
|
||||
; B ; LC27 ; C7M, nRES, D[7], AddrMWR_MC, Addr[15], S[1], S[2], S[0], IncAddrH, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], IncAddrH, Addr[23] ;
|
||||
; B ; LC18 ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[0], S[1], Addr[21], IncAddrH, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[5]~108, Addr[21], RA~68, Addr[22], Addr[23] ;
|
||||
; B ; LC30 ; C7M, nRES, D[7], AddrHWR_MC, S[2], S[0], S[1], Addr[23], IncAddrH, Addr[22], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[7]~120, Addr[23] ;
|
||||
; B ; LC31 ; C7M, nRES, D[5], BankWR_MC, S[0], S[2], S[1] ; RA~94, RA~101, RA~108 ;
|
||||
; B ; LC17 ; ; nINH ;
|
||||
; B ; LC23 ; PHI1b0_MC ; PHI1b2_MC ;
|
||||
; B ; LC21 ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[0], S[1], Addr[20], IncAddrH, Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[4]~102, Addr[20], RA~65, Addr[21], Addr[22], Addr[23] ;
|
||||
; B ; LC32 ; C7M, nRES, D[3], BankWR_MC, S[0], S[2], S[1] ; RA~80, RA~87, RA~94, RA~101, RA~108 ;
|
||||
; B ; LC29 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[0], S[1], Addr[19], IncAddrH, Addr[18], Addr[17], Addr[16] ; Dout[3]~96, Addr[19], RA~62, Addr[20], Addr[21], Addr[22], Addr[23] ;
|
||||
; C ; LC38 ; RD[4], nDEVSEL, A[0], A[1], A[2], A[3], Addr[12], Addr[20], Addr[4] ; D[4] ;
|
||||
; C ; LC40 ; RD[5], nDEVSEL, A[0], A[1], A[2], A[3], Addr[13], Addr[21], Addr[5] ; D[5] ;
|
||||
; C ; LC43 ; RD[6], nDEVSEL, A[0], A[1], A[2], A[3], Addr[14], Addr[22], Addr[6] ; D[6] ;
|
||||
; C ; LC39 ; PHI1b4_MC ; PHI1b6_MC ;
|
||||
; C ; LC36 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1], IncAddrL ; IncAddrL, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM~9, IncAddrM ;
|
||||
; C ; LC48 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
|
||||
; C ; LC41 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, S[0], S[1], S[2] ;
|
||||
; C ; LC33 ; PHI1in ; PHI1b1_MC ;
|
||||
; C ; LC45 ; RD[7], nDEVSEL, A[0], A[1], A[2], A[3], Addr[15], Addr[23], Addr[7] ; D[7] ;
|
||||
; C ; LC37 ; PHI1b7_MC ; PHI1b9_MC ;
|
||||
; C ; LC35 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
|
||||
; C ; LC34 ; PHI1b3_MC ; PHI1b5_MC ;
|
||||
; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ;
|
||||
; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ;
|
||||
; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ;
|
||||
; D ; LC56 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ;
|
||||
; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ;
|
||||
; D ; LC63 ; PHI1b6_MC ; PHI1b8_MC ;
|
||||
; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ;
|
||||
; D ; LC53 ; Addr[22], CASr, RAMSEL_MC, CAS0f ; nCAS0 ;
|
||||
; D ; LC51 ; Addr[22], CASr, RAMSEL_MC, CAS1f ; nCAS1 ;
|
||||
; E ; LC72 ; Addr[21], ASel, Addr[10] ; RA[10] ;
|
||||
; E ; LC78 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~29 ;
|
||||
; E ; LC69 ; Addr[20], ASel, Addr[9] ; RA[9] ;
|
||||
; E ; LC67 ; nWE ; nROE ;
|
||||
; E ; LC71 ; C7M, nRES, D[0], BankWR_MC, S[0], S[2], S[1] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
|
||||
; E ; LC68 ; C7M, nRES, D[0], AddrHWR_MC, S[1], S[2], Addr[16], S[0], IncAddrH ; Dout[0]~78, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~94 ;
|
||||
; E ; LC79 ; C7M, nRES, D[7], BankWR_MC, S[0], S[2], S[1] ; RA~108 ;
|
||||
; E ; LC80 ; Bank[0], FullIOEN, nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0] ; RA[0] ;
|
||||
; E ; LC75 ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2] ; RA[2] ;
|
||||
; E ; LC73 ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ;
|
||||
; E ; LC77 ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ;
|
||||
; F ; LC91 ; Addr[19], ASel, Addr[8] ; RA[8] ;
|
||||
; F ; LC94 ; D[7] ; RD[7] ;
|
||||
; F ; LC87 ; PHI1b1_MC ; PHI1b3_MC ;
|
||||
; F ; LC85 ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ;
|
||||
; F ; LC89 ; PHI1b5_MC ; PHI1b7_MC ;
|
||||
; F ; LC88 ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ;
|
||||
; F ; LC86 ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ;
|
||||
; F ; LC83 ; Addr[12], ASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0] ; RA[1] ;
|
||||
; F ; LC93 ; RASr, RASf ; nRAS ;
|
||||
; G ; LC104 ; nDEVSEL, nIOSEL, nIOSTRB, nWE ; nRWE ;
|
||||
; G ; LC99 ; D[6] ; RD[6] ;
|
||||
; G ; LC97 ; D[5] ; RD[5] ;
|
||||
; G ; LC101 ; D[4] ; RD[4] ;
|
||||
; G ; LC107 ; D[2] ; RD[2] ;
|
||||
; G ; LC109 ; D[1] ; RD[1] ;
|
||||
; G ; LC112 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
|
||||
; G ; LC110 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ;
|
||||
; G ; LC100 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ;
|
||||
; G ; LC111 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
|
||||
; G ; LC108 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23] ;
|
||||
; G ; LC106 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; IncAddrL, CASr, ASel, RASf, RASr, CAS1f, CAS0f, comb~34, comb~38 ;
|
||||
; G ; LC102 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[0], S[2], S[1], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
|
||||
; G ; LC103 ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~29 ;
|
||||
; G ; LC98 ; C7M, nRES, nIOSEL, S[2], S[1], S[0] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, FullIOEN ;
|
||||
; G ; LC105 ; D[3] ; RD[3] ;
|
||||
; H ; LC114 ; PHI1b2_MC ; PHI1b4_MC ;
|
||||
; H ; LC115 ; D[0] ; RD[0] ;
|
||||
; H ; LC116 ; C7M, nRES, nWE, S[0], RAMSEL_MC, S[2], S[1] ; comb~31 ;
|
||||
; H ; LC125 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0], Addr[22], nWE, RAMSEL_MC ; comb~38 ;
|
||||
; H ; LC122 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0], Addr[22], nWE, RAMSEL_MC ; comb~34 ;
|
||||
; H ; LC120 ; C7M, nRES, nWE, S[0], RAMSEL_MC, S[2], S[1] ; RA~62, RA~65, RA~68, RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
|
||||
; H ; LC119 ; C7M, nRES, S[1], S[2], nWE, RAMSEL_MC, S[0] ; comb~34, comb~38 ;
|
||||
; H ; LC126 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ;
|
||||
; H ; LC121 ; C7M, nRES, D[7], AddrLWR_MC, Addr[7], S[2], S[1], S[0], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrM, IncAddrM~9 ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrM, Addr[15], IncAddrH ;
|
||||
; H ; LC123 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ;
|
||||
; H ; LC124 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ;
|
||||
; H ; LC127 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ;
|
||||
; H ; LC113 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, lpm_counter:Ref_rtl_0|dffs[2], CASr, Addr[16], ASel, RASf, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS1f, CAS0f, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
|
||||
; H ; LC118 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, lpm_counter:Ref_rtl_0|dffs[2], CASr, Addr[16], ASel, RASf, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS1f, CAS0f, Bank[6], Addr[6], Addr[7], IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
|
||||
; H ; LC128 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[2], S[1] ; S[0], S[1], S[2], lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, lpm_counter:Ref_rtl_0|dffs[2], CASr, Addr[16], ASel, RASf, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS1f, CAS0f, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
|
||||
; H ; LC117 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0], nWE, RAMSEL_MC ; comb~31 ;
|
||||
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Logic Cell Interconnection ;
|
||||
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; LAB ; Logic Cell ; Input ; Output ;
|
||||
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[0], S[2], S[1], Addr[5], IncAddrL, Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[5]~108, Addr[5], Addr[6], Addr[7], IncAddrM, RA~95 ;
|
||||
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[0], S[2], S[1], Addr[4], IncAddrL, Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[4]~102, Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~88 ;
|
||||
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[0], S[2], S[1], Addr[3], IncAddrL, Addr[2], Addr[1], Addr[0] ; Dout[3]~96, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~81 ;
|
||||
; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], IncAddrM, Addr[8] ; Dout[1]~84, Addr[9], Addr[10], Addr[11], RA~66, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
|
||||
; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[0], S[2], S[1], Addr[2], IncAddrL, Addr[1], Addr[0] ; Dout[2]~90, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~80 ;
|
||||
; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], IncAddrM ; Dout[0]~78, Addr[8], Addr[9], Addr[10], Addr[11], RA~63, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
|
||||
; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[0], S[2], S[1], Addr[1], IncAddrL, Addr[0] ; Dout[1]~84, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~121 ;
|
||||
; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[0], S[2], S[1], Addr[7], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[7]~120, Addr[7], IncAddrM, RA~109 ;
|
||||
; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[0], S[2], S[1], Addr[6], IncAddrL, Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[6]~114, Addr[6], Addr[7], IncAddrM, RA~102 ;
|
||||
; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[0], S[2], S[1], Addr[0], IncAddrL ; Dout[0]~78, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~74 ;
|
||||
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], IncAddrM, Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[6]~114, Addr[14], Addr[15], IncAddrH, RA~81 ;
|
||||
; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], IncAddrM, Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[5]~108, Addr[13], Addr[14], Addr[15], IncAddrH, RA~80 ;
|
||||
; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], IncAddrM, Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[4]~102, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~121 ;
|
||||
; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], IncAddrM, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[7]~120, Addr[15], IncAddrH, RA~88 ;
|
||||
; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], IncAddrM, Addr[10], Addr[9], Addr[8] ; Dout[3]~96, Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~74 ;
|
||||
; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], IncAddrM, Addr[9], Addr[8] ; Dout[2]~90, Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], RA~69, Addr[15], IncAddrH ;
|
||||
; B ; LC17 ; ; nINH ;
|
||||
; B ; LC25 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[0], S[1], Addr[18], IncAddrH, Addr[17], Addr[16] ; Dout[2]~90, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~109 ;
|
||||
; B ; LC24 ; C7M, nRES, D[1], BankWR_MC, S[0], S[2], S[1] ; RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ;
|
||||
; B ; LC31 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[0], S[1], Addr[17], IncAddrH, Addr[16] ; Dout[1]~84, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~102 ;
|
||||
; B ; LC32 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[0], S[1], Addr[19], IncAddrH, Addr[18], Addr[17], Addr[16] ; Dout[3]~96, Addr[19], RA~63, Addr[20], Addr[21], Addr[22], Addr[23] ;
|
||||
; B ; LC20 ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[0], S[1], Addr[20], IncAddrH, Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[4]~102, Addr[20], RA~66, Addr[21], Addr[22], Addr[23] ;
|
||||
; B ; LC27 ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[0], S[1], Addr[21], IncAddrH, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[5]~108, Addr[21], RA~69, Addr[22], Addr[23] ;
|
||||
; B ; LC19 ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[0], S[1], Addr[22], IncAddrH, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[6]~114, Addr[22], CAS1f, CAS0f, comb~30, comb~34, Addr[23] ;
|
||||
; B ; LC28 ; C7M, nRES, D[6], BankWR_MC, S[0], S[2], S[1] ; RA~102, RA~109 ;
|
||||
; B ; LC21 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~25 ;
|
||||
; B ; LC29 ; C7M, nRES, D[7], AddrLWR_MC, Addr[7], S[2], S[1], S[0], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrM, IncAddrM~9 ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrM, Addr[15], IncAddrH ;
|
||||
; B ; LC30 ; C7M, nRES, D[7], AddrHWR_MC, S[2], S[0], S[1], Addr[23], IncAddrH, Addr[22], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[7]~120, Addr[23] ;
|
||||
; C ; LC34 ; C7M, nRES, D[0], AddrHWR_MC, S[1], S[2], Addr[16], S[0], IncAddrH ; Dout[0]~78, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~95 ;
|
||||
; C ; LC46 ; A[0], A[1], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ;
|
||||
; C ; LC44 ; nWE, REGEN, nDEVSEL, A[0], A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ;
|
||||
; C ; LC33 ; C7M, nRES, S[0], nWE, RAMSEL_MC, S[1], S[2] ; comb~27 ;
|
||||
; C ; LC42 ; PHI1b0_MC ; PHI1b2_MC ;
|
||||
; C ; LC38 ; RD[4], nDEVSEL, A[1], A[0], A[2], A[3], Addr[20], Addr[12], Addr[4] ; D[4] ;
|
||||
; C ; LC40 ; RD[5], nDEVSEL, A[1], A[0], A[2], A[3], Addr[21], Addr[13], Addr[5] ; D[5] ;
|
||||
; C ; LC43 ; RD[6], nDEVSEL, A[1], A[0], A[2], A[3], Addr[22], Addr[14], Addr[6] ; D[6] ;
|
||||
; C ; LC45 ; RD[7], nDEVSEL, A[1], A[0], A[2], A[3], Addr[23], Addr[15], Addr[7] ; D[7] ;
|
||||
; C ; LC35 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; FullIOEN ;
|
||||
; C ; LC36 ; REGEN, nDEVSEL, A[0], A[1], A[2], A[3] ; IncAddrL, ASel, RASf, RASr, CAS1f, CAS0f, comb~30, comb~34 ;
|
||||
; C ; LC48 ; A[0], A[1], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23] ;
|
||||
; C ; LC41 ; A[0], A[1], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
|
||||
; D ; LC56 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
|
||||
; D ; LC59 ; RD[1], nDEVSEL, A[1], A[0], A[2], A[3], Addr[17], Addr[9], Addr[1] ; D[1] ;
|
||||
; D ; LC61 ; RD[2], nDEVSEL, A[1], A[0], A[2], A[3], Addr[18], Addr[10], Addr[2] ; D[2] ;
|
||||
; D ; LC64 ; RD[3], nDEVSEL, A[1], A[0], A[2], A[3], Addr[19], Addr[11], Addr[3] ; D[3] ;
|
||||
; D ; LC57 ; RD[0], nDEVSEL, A[1], A[0], A[2], A[3], Addr[16], Addr[8], Addr[0] ; D[0] ;
|
||||
; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ;
|
||||
; D ; LC51 ; CASr, Addr[22], RAMSEL_MC, CAS1f ; nCAS1 ;
|
||||
; D ; LC53 ; CASr, Addr[22], RAMSEL_MC, CAS0f ; nCAS0 ;
|
||||
; D ; LC62 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
|
||||
; D ; LC52 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
|
||||
; E ; LC79 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1], IncAddrL ; IncAddrL, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM~9, IncAddrM ;
|
||||
; E ; LC75 ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2] ; RA[2] ;
|
||||
; E ; LC72 ; Addr[21], ASel, Addr[10] ; RA[10] ;
|
||||
; E ; LC78 ; C7M, nRES, D[0], BankWR_MC, S[0], S[2], S[1] ; RA~74, RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ;
|
||||
; E ; LC73 ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ;
|
||||
; E ; LC74 ; C7M, nRES, S[1], S[2], nWE, S[0] ; comb~30, comb~34 ;
|
||||
; E ; LC68 ; C7M, nRES, D[7], BankWR_MC, S[0], S[2], S[1] ; RA~109 ;
|
||||
; E ; LC77 ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ;
|
||||
; E ; LC67 ; nWE ; nROE ;
|
||||
; E ; LC69 ; Addr[20], ASel, Addr[9] ; RA[9] ;
|
||||
; E ; LC80 ; Bank[0], FullIOEN, nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0] ; RA[0] ;
|
||||
; F ; LC88 ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ;
|
||||
; F ; LC86 ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ;
|
||||
; F ; LC83 ; Addr[12], ASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0] ; RA[1] ;
|
||||
; F ; LC94 ; D[7] ; RD[7] ;
|
||||
; F ; LC82 ; C7M, nRES, S[2], nIOSEL, S[1], S[0] ; DOE~5, RAMSEL_MC, BankWR_MC, SetWR_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC ;
|
||||
; F ; LC87 ; C7M, nRES, D[4], BankWR_MC, S[0], S[2], S[1] ; RA~88, RA~95, RA~102, RA~109 ;
|
||||
; F ; LC89 ; C7M, nRES, D[2], BankWR_MC, S[0], S[2], S[1] ; RA~80, RA~81, RA~88, RA~95, RA~102, RA~109 ;
|
||||
; F ; LC92 ; C7M, nRES, D[3], BankWR_MC, S[0], S[2], S[1] ; RA~81, RA~88, RA~95, RA~102, RA~109 ;
|
||||
; F ; LC93 ; RASr, RASf ; nRAS ;
|
||||
; F ; LC91 ; Addr[19], ASel, Addr[8] ; RA[8] ;
|
||||
; F ; LC84 ; C7M, nRES, D[5], BankWR_MC, S[0], S[2], S[1] ; RA~95, RA~102, RA~109 ;
|
||||
; F ; LC85 ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ;
|
||||
; G ; LC109 ; D[1] ; RD[1] ;
|
||||
; G ; LC107 ; D[2] ; RD[2] ;
|
||||
; G ; LC108 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ;
|
||||
; G ; LC110 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ;
|
||||
; G ; LC100 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ;
|
||||
; G ; LC111 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], S[2], S[1], nWE, Addr[22], RAMSEL_MC ; comb~34 ;
|
||||
; G ; LC103 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], S[2], S[1], nWE, Addr[22], RAMSEL_MC ; comb~30 ;
|
||||
; G ; LC105 ; D[3] ; RD[3] ;
|
||||
; G ; LC106 ; C7M, nRES, D[7], AddrMWR_MC, Addr[15], S[1], S[2], S[0], IncAddrH, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], IncAddrH, Addr[23] ;
|
||||
; G ; LC112 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], SetWR_MC, S[0], S[2], S[1] ; RA~74, RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ;
|
||||
; G ; LC99 ; D[6] ; RD[6] ;
|
||||
; G ; LC97 ; D[5] ; RD[5] ;
|
||||
; G ; LC102 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[1], S[0], S[2], RAMSEL_MC, nWE ; comb~27 ;
|
||||
; G ; LC101 ; D[4] ; RD[4] ;
|
||||
; G ; LC104 ; S[2], nWE ; nRWE ;
|
||||
; G ; LC98 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ;
|
||||
; H ; LC120 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ;
|
||||
; H ; LC124 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], REGEN, lpm_counter:Ref_rtl_0|dffs[0], CASr, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, ASel, RASf, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], Addr[0], lpm_counter:Ref_rtl_0|dffs[3], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS1f, CAS0f, Bank[6], Addr[6], Addr[7], IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
|
||||
; H ; LC114 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, S[0], S[1], S[2] ;
|
||||
; H ; LC119 ; PHI1b7_MC ; PHI1b9_MC ;
|
||||
; H ; LC128 ; PHI1b6_MC ; PHI1b8_MC ;
|
||||
; H ; LC127 ; PHI1b5_MC ; PHI1b7_MC ;
|
||||
; H ; LC123 ; PHI1b4_MC ; PHI1b6_MC ;
|
||||
; H ; LC122 ; PHI1b3_MC ; PHI1b5_MC ;
|
||||
; H ; LC126 ; C7M, nRES, S[2], nIOSEL, S[1], S[0], IOROMEN, A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[0], A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~25 ;
|
||||
; H ; LC117 ; PHI1b2_MC ; PHI1b4_MC ;
|
||||
; H ; LC125 ; PHI1b1_MC ; PHI1b3_MC ;
|
||||
; H ; LC121 ; C7M, nRES, S[0], nWE, RAMSEL_MC, S[1], S[2] ; RA~63, RA~66, RA~69, RA~74, RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ;
|
||||
; H ; LC115 ; D[0] ; RD[0] ;
|
||||
; H ; LC116 ; PHI1in ; PHI1b1_MC ;
|
||||
; H ; LC118 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, ASel~10, REGEN, lpm_counter:Ref_rtl_0|dffs[0], CASr, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, ASel, RASf, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], Addr[0], lpm_counter:Ref_rtl_0|dffs[3], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS1f, CAS0f, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
|
||||
; H ; LC113 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[2], S[1] ; S[0], S[1], S[2], REGEN, lpm_counter:Ref_rtl_0|dffs[0], CASr, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, ASel, RASf, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], Addr[0], lpm_counter:Ref_rtl_0|dffs[3], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS1f, CAS0f, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
|
||||
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------+
|
||||
@ -713,10 +722,10 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
+-----------------+
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM"
|
||||
Info: Quartus II 32-bit Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 287 megabytes
|
||||
Info: Processing ended: Fri Oct 18 15:02:00 2019
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 4708 megabytes
|
||||
Info: Processing ended: Sun Oct 20 22:22:01 2019
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
|
||||
|
||||
|
||||
@ -1,9 +1,9 @@
|
||||
Fitter Status : Successful - Fri Oct 18 15:02:00 2019
|
||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Fitter Status : Successful - Sun Oct 20 22:22:01 2019
|
||||
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : GR8RAM
|
||||
Top-level Entity Name : GR8RAM
|
||||
Family : MAX7000S
|
||||
Device : EPM7128SLC84-15
|
||||
Timing Models : Final
|
||||
Total macrocells : 105 / 128 ( 82 % )
|
||||
Total macrocells : 106 / 128 ( 83 % )
|
||||
Total pins : 65 / 68 ( 96 % )
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Flow report for GR8RAM
|
||||
Fri Oct 18 15:02:10 2019
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Sun Oct 20 22:22:04 2019
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -40,14 +40,14 @@ applicable agreement for further details.
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+---------------------------+-------------------------------------------------+
|
||||
; Flow Status ; Successful - Fri Oct 18 15:02:04 2019 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Flow Status ; Successful - Sun Oct 20 22:22:02 2019 ;
|
||||
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX7000S ;
|
||||
; Device ; EPM7128SLC84-15 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total macrocells ; 105 / 128 ( 82 % ) ;
|
||||
; Total macrocells ; 106 / 128 ( 83 % ) ;
|
||||
; Total pins ; 65 / 68 ( 96 % ) ;
|
||||
+---------------------------+-------------------------------------------------+
|
||||
|
||||
@ -57,40 +57,40 @@ applicable agreement for further details.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 10/18/2019 15:01:50 ;
|
||||
; Start date & time ; 10/20/2019 22:21:59 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
+-------------------+---------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Non-Default Global Settings ;
|
||||
+--------------------------------------------+-----------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+--------------------------------------------+-----------------------------+---------------+-------------+------------+
|
||||
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
|
||||
; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ;
|
||||
; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ;
|
||||
; AUTO_TURBO_BIT ; Off ; On ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 52238299365.157142531003212 ; -- ; -- ; -- ;
|
||||
; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ;
|
||||
; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ;
|
||||
; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ;
|
||||
; EXTRACT_VHDL_STATE_MACHINES ; Off ; On ; -- ; -- ;
|
||||
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
|
||||
; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ;
|
||||
; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ;
|
||||
; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ;
|
||||
; PRE_MAPPING_RESYNTHESIS ; On ; Off ; -- ; -- ;
|
||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||
; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ;
|
||||
; STATE_MACHINE_PROCESSING ; User-Encoded ; Auto ; -- ; -- ;
|
||||
; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ;
|
||||
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
|
||||
+--------------------------------------------+-----------------------------+---------------+-------------+------------+
|
||||
+-------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Non-Default Global Settings ;
|
||||
+--------------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+--------------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
|
||||
; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ;
|
||||
; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ;
|
||||
; AUTO_TURBO_BIT ; Off ; On ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 207120313862967.157162451910916 ; -- ; -- ; -- ;
|
||||
; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ;
|
||||
; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ;
|
||||
; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ;
|
||||
; EXTRACT_VHDL_STATE_MACHINES ; Off ; On ; -- ; -- ;
|
||||
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
|
||||
; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ;
|
||||
; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ;
|
||||
; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ;
|
||||
; PRE_MAPPING_RESYNTHESIS ; On ; Off ; -- ; -- ;
|
||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||
; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ;
|
||||
; STATE_MACHINE_PROCESSING ; User-Encoded ; Auto ; -- ; -- ;
|
||||
; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ;
|
||||
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
|
||||
+--------------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------+
|
||||
@ -98,24 +98,24 @@ applicable agreement for further details.
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:08 ; 1.0 ; 308 MB ; 00:00:08 ;
|
||||
; Fitter ; 00:00:05 ; 1.0 ; 287 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:03 ; 1.0 ; 275 MB ; 00:00:03 ;
|
||||
; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 259 MB ; 00:00:05 ;
|
||||
; Total ; 00:00:20 ; -- ; -- ; 00:00:20 ;
|
||||
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4587 MB ; 00:00:01 ;
|
||||
; Fitter ; 00:00:01 ; 1.0 ; 4708 MB ; 00:00:00 ;
|
||||
; Assembler ; 00:00:00 ; 1.0 ; 4522 MB ; 00:00:00 ;
|
||||
; TimeQuest Timing Analyzer ; 00:00:00 ; 1.0 ; 4541 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:02 ; -- ; -- ; 00:00:02 ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------+
|
||||
; Flow OS Summary ;
|
||||
+---------------------------+------------------+------------+------------+----------------+
|
||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||
+---------------------------+------------------+------------+------------+----------------+
|
||||
; Analysis & Synthesis ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
|
||||
; Fitter ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
|
||||
; Assembler ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
|
||||
; TimeQuest Timing Analyzer ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
|
||||
+---------------------------+------------------+------------+------------+----------------+
|
||||
+----------------------------------------------------------------------------------------+
|
||||
; Flow OS Summary ;
|
||||
+---------------------------+------------------+-----------+------------+----------------+
|
||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||
+---------------------------+------------------+-----------+------------+----------------+
|
||||
; Analysis & Synthesis ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; Fitter ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; Assembler ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; TimeQuest Timing Analyzer ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
+---------------------------+------------------+-----------+------------+----------------+
|
||||
|
||||
|
||||
------------
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="053b98ea9c3c88706d49"/>
|
||||
<hash md5_digest_80b="4badf67548bfa7a0e186"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Analysis & Synthesis report for GR8RAM
|
||||
Fri Oct 18 15:01:54 2019
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Sun Oct 20 22:22:00 2019
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -9,16 +9,17 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||
1. Legal Notice
|
||||
2. Analysis & Synthesis Summary
|
||||
3. Analysis & Synthesis Settings
|
||||
4. Analysis & Synthesis Source Files Read
|
||||
5. Analysis & Synthesis Resource Usage Summary
|
||||
6. Analysis & Synthesis Resource Utilization by Entity
|
||||
7. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0
|
||||
8. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0
|
||||
9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4
|
||||
10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3
|
||||
11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5
|
||||
12. Analysis & Synthesis Messages
|
||||
13. Analysis & Synthesis Suppressed Messages
|
||||
4. Parallel Compilation
|
||||
5. Analysis & Synthesis Source Files Read
|
||||
6. Analysis & Synthesis Resource Usage Summary
|
||||
7. Analysis & Synthesis Resource Utilization by Entity
|
||||
8. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0
|
||||
9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0
|
||||
10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4
|
||||
11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3
|
||||
12. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5
|
||||
13. Analysis & Synthesis Messages
|
||||
14. Analysis & Synthesis Suppressed Messages
|
||||
|
||||
|
||||
|
||||
@ -44,12 +45,12 @@ applicable agreement for further details.
|
||||
+-------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+-------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Fri Oct 18 15:01:54 2019 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Analysis & Synthesis Status ; Successful - Sun Oct 20 22:22:00 2019 ;
|
||||
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX7000S ;
|
||||
; Total macrocells ; 105 ;
|
||||
; Total macrocells ; 106 ;
|
||||
; Total pins ; 61 ;
|
||||
+-----------------------------+-------------------------------------------------+
|
||||
|
||||
@ -118,12 +119,23 @@ applicable agreement for further details.
|
||||
+----------------------------------------------------------------------------+-----------------+---------------+
|
||||
|
||||
|
||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||
+-------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+--------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+--------+
|
||||
; Number detected on machine ; 8 ;
|
||||
; Maximum allowed ; 1 ;
|
||||
+----------------------------+--------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
|
||||
; GR8RAM.v ; yes ; User Verilog HDL File ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ; ;
|
||||
; GR8RAM.v ; yes ; User Verilog HDL File ; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ; ;
|
||||
; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ;
|
||||
; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ;
|
||||
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
|
||||
@ -153,14 +165,14 @@ applicable agreement for further details.
|
||||
+----------------------+----------------------+
|
||||
; Resource ; Usage ;
|
||||
+----------------------+----------------------+
|
||||
; Logic cells ; 105 ;
|
||||
; Logic cells ; 106 ;
|
||||
; Total registers ; 54 ;
|
||||
; I/O pins ; 61 ;
|
||||
; Shareable expanders ; 1 ;
|
||||
; Maximum fan-out node ; C7M ;
|
||||
; Maximum fan-out node ; S[2] ;
|
||||
; Maximum fan-out ; 54 ;
|
||||
; Total fan-out ; 866 ;
|
||||
; Average fan-out ; 5.19 ;
|
||||
; Total fan-out ; 864 ;
|
||||
; Average fan-out ; 5.14 ;
|
||||
+----------------------+----------------------+
|
||||
|
||||
|
||||
@ -169,7 +181,7 @@ applicable agreement for further details.
|
||||
+----------------------------+------------+------+-------------------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
|
||||
+----------------------------+------------+------+-------------------------------+--------------+
|
||||
; |GR8RAM ; 105 ; 61 ; |GR8RAM ; work ;
|
||||
; |GR8RAM ; 106 ; 61 ; |GR8RAM ; work ;
|
||||
; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ;
|
||||
+----------------------------+------------+------+-------------------------------+--------------+
|
||||
|
||||
@ -317,20 +329,20 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||
; Analysis & Synthesis Messages ;
|
||||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Analysis & Synthesis
|
||||
Info: Running Quartus II 64-Bit Analysis & Synthesis
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Fri Oct 18 15:01:46 2019
|
||||
Info: Processing started: Sun Oct 20 22:21:59 2019
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
||||
Info (12023): Found entity 1: GR8RAM
|
||||
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(123): truncated value with size 32 to match size of target (3)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (4)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(160): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(165): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(171): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(122): truncated value with size 32 to match size of target (3)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(127): truncated value with size 32 to match size of target (4)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(170): truncated value with size 32 to match size of target (8)
|
||||
Info (19000): Inferred 1 megafunctions from design logic
|
||||
Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0"
|
||||
Info (278001): Inferred 4 megafunctions from design logic
|
||||
@ -370,23 +382,23 @@ Warning (21074): Design contains 9 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "A[13]"
|
||||
Warning (15610): No output dependent on input pin "A[14]"
|
||||
Warning (15610): No output dependent on input pin "A[15]"
|
||||
Info (21057): Implemented 167 device resources after synthesis - the final resource count might be different
|
||||
Info (21057): Implemented 168 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 27 input pins
|
||||
Info (21059): Implemented 18 output pins
|
||||
Info (21060): Implemented 16 bidirectional pins
|
||||
Info (21063): Implemented 105 macrocells
|
||||
Info (21063): Implemented 106 macrocells
|
||||
Info (21073): Implemented 1 shareable expanders
|
||||
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 17 warnings
|
||||
Info: Peak virtual memory: 308 megabytes
|
||||
Info: Processing ended: Fri Oct 18 15:01:54 2019
|
||||
Info: Elapsed time: 00:00:08
|
||||
Info: Total CPU time (on all processors): 00:00:08
|
||||
Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
||||
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 17 warnings
|
||||
Info: Peak virtual memory: 4587 megabytes
|
||||
Info: Processing ended: Sun Oct 20 22:22:00 2019
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Analysis & Synthesis Suppressed Messages ;
|
||||
+------------------------------------------+
|
||||
The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
||||
The suppressed messages can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
||||
|
||||
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
Warning (10273): Verilog HDL warning at GR8RAM.v(52): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at GR8RAM.v(60): extended using "x" or "z"
|
||||
Warning (10268): Verilog HDL information at GR8RAM.v(191): always construct contains both blocking and non-blocking assignments
|
||||
Warning (10268): Verilog HDL information at GR8RAM.v(190): always construct contains both blocking and non-blocking assignments
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
Analysis & Synthesis Status : Successful - Fri Oct 18 15:01:54 2019
|
||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Analysis & Synthesis Status : Successful - Sun Oct 20 22:22:00 2019
|
||||
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : GR8RAM
|
||||
Top-level Entity Name : GR8RAM
|
||||
Family : MAX7000S
|
||||
Total macrocells : 105
|
||||
Total macrocells : 106
|
||||
Total pins : 61
|
||||
|
||||
@ -56,7 +56,7 @@
|
||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
CHIP "GR8RAM" ASSIGNED TO AN: EPM7128SLC84-15
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
|
||||
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
TimeQuest Timing Analyzer report for GR8RAM
|
||||
Fri Oct 18 15:02:11 2019
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Sun Oct 20 22:22:04 2019
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -8,32 +8,33 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. TimeQuest Timing Analyzer Summary
|
||||
3. Clocks
|
||||
4. Fmax Summary
|
||||
5. Setup Summary
|
||||
6. Hold Summary
|
||||
7. Recovery Summary
|
||||
8. Removal Summary
|
||||
9. Minimum Pulse Width Summary
|
||||
10. Setup: 'C7M'
|
||||
11. Hold: 'C7M'
|
||||
12. Minimum Pulse Width: 'C7M'
|
||||
13. Setup Times
|
||||
14. Hold Times
|
||||
15. Clock to Output Times
|
||||
16. Minimum Clock to Output Times
|
||||
17. Propagation Delay
|
||||
18. Minimum Propagation Delay
|
||||
19. Output Enable Times
|
||||
20. Minimum Output Enable Times
|
||||
21. Output Disable Times
|
||||
22. Minimum Output Disable Times
|
||||
23. Setup Transfers
|
||||
24. Hold Transfers
|
||||
25. Report TCCS
|
||||
26. Report RSKM
|
||||
27. Unconstrained Paths
|
||||
28. TimeQuest Timing Analyzer Messages
|
||||
3. Parallel Compilation
|
||||
4. Clocks
|
||||
5. Fmax Summary
|
||||
6. Setup Summary
|
||||
7. Hold Summary
|
||||
8. Recovery Summary
|
||||
9. Removal Summary
|
||||
10. Minimum Pulse Width Summary
|
||||
11. Setup: 'C7M'
|
||||
12. Hold: 'C7M'
|
||||
13. Minimum Pulse Width: 'C7M'
|
||||
14. Setup Times
|
||||
15. Hold Times
|
||||
16. Clock to Output Times
|
||||
17. Minimum Clock to Output Times
|
||||
18. Propagation Delay
|
||||
19. Minimum Propagation Delay
|
||||
20. Output Enable Times
|
||||
21. Minimum Output Enable Times
|
||||
22. Output Disable Times
|
||||
23. Minimum Output Disable Times
|
||||
24. Setup Transfers
|
||||
25. Hold Transfers
|
||||
26. Report TCCS
|
||||
27. Report RSKM
|
||||
28. Unconstrained Paths
|
||||
29. TimeQuest Timing Analyzer Messages
|
||||
|
||||
|
||||
|
||||
@ -69,6 +70,17 @@ applicable agreement for further details.
|
||||
+--------------------+-------------------------------------------------------------------+
|
||||
|
||||
|
||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||
+-------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+--------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+--------+
|
||||
; Number detected on machine ; 8 ;
|
||||
; Maximum allowed ; 1 ;
|
||||
+----------------------------+--------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Clocks ;
|
||||
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
|
||||
@ -93,7 +105,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; C7M ; -47.500 ; -2169.500 ;
|
||||
; C7M ; -47.500 ; -2091.500 ;
|
||||
+-------+---------+---------------+
|
||||
|
||||
|
||||
@ -132,50 +144,50 @@ No paths to report.
|
||||
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||
; -47.500 ; REGEN ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[14] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[14] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[7] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[23] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; RASf ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Bank[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Bank[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Bank[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Bank[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Bank[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Bank[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; CAS1f ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; CAS0f ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Bank[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Bank[7] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.000 ; REGEN ; CASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||
; -47.000 ; REGEN ; ASel ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||
; -47.000 ; REGEN ; RASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; FullIOEN ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -46.500 ; S[2] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ;
|
||||
; -46.500 ; S[0] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ;
|
||||
; -46.000 ; IncAddrL ; IncAddrM ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ;
|
||||
; -34.500 ; REGEN ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ;
|
||||
; -34.500 ; REGEN ; RASf ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ;
|
||||
; -34.500 ; REGEN ; CAS1f ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ;
|
||||
; -34.500 ; REGEN ; CAS0f ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ;
|
||||
; -34.000 ; REGEN ; ASel ; C7M ; C7M ; 1.000 ; 0.000 ; 31.000 ;
|
||||
; -34.000 ; REGEN ; RASr ; C7M ; C7M ; 1.000 ; 0.000 ; 31.000 ;
|
||||
; -25.500 ; S[0] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
@ -185,53 +197,53 @@ No paths to report.
|
||||
; -25.500 ; S[0] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
@ -265,28 +277,28 @@ No paths to report.
|
||||
; 5.000 ; IncAddrL ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[1] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[16] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[17] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[8] ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[9] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[10] ; Addr[10] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[17] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[18] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[10] ; Addr[10] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[2] ; Addr[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[3] ; Addr[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[19] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[11] ; Addr[11] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[12] ; Addr[12] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[19] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[20] ; Addr[20] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[12] ; Addr[12] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[4] ; Addr[4] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[5] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[21] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[13] ; Addr[13] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[14] ; Addr[14] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[21] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[22] ; Addr[22] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[14] ; Addr[14] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[6] ; Addr[6] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[23] ; Addr[23] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[8] ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[16] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 18.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
@ -318,28 +330,28 @@ No paths to report.
|
||||
; 18.000 ; S[1] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrL ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrL ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[0] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrM ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[14] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[13] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[12] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[11] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[10] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[9] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[8] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrH ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrM ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrM ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[8] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrH ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[16] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrH ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[17] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[16] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrM ; Addr[10] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
@ -456,11 +468,11 @@ No paths to report.
|
||||
+-----------+------------+---------+---------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+---------+---------+------------+-----------------+
|
||||
; A[*] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
|
||||
; A[0] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
|
||||
; A[1] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
|
||||
; A[2] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
|
||||
; A[3] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
|
||||
; A[*] ; C7M ; 33.000 ; 33.000 ; Rise ; C7M ;
|
||||
; A[0] ; C7M ; 33.000 ; 33.000 ; Rise ; C7M ;
|
||||
; A[1] ; C7M ; 33.000 ; 33.000 ; Rise ; C7M ;
|
||||
; A[2] ; C7M ; 33.000 ; 33.000 ; Rise ; C7M ;
|
||||
; A[3] ; C7M ; 33.000 ; 33.000 ; Rise ; C7M ;
|
||||
; A[4] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
||||
; A[5] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
||||
; A[6] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
||||
@ -469,7 +481,7 @@ No paths to report.
|
||||
; A[9] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
||||
; A[10] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
||||
; PHI1in ; C7M ; 101.000 ; 101.000 ; Rise ; C7M ;
|
||||
; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
|
||||
; nDEVSEL ; C7M ; 33.000 ; 33.000 ; Rise ; C7M ;
|
||||
; nIOSEL ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
||||
; nIOSTRB ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
||||
; nWE ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
||||
@ -510,15 +522,15 @@ No paths to report.
|
||||
; A[9] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
||||
; A[10] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
||||
; PHI1in ; C7M ; -12.000 ; -12.000 ; Rise ; C7M ;
|
||||
; nDEVSEL ; C7M ; -38.000 ; -38.000 ; Rise ; C7M ;
|
||||
; nDEVSEL ; C7M ; -25.000 ; -25.000 ; Rise ; C7M ;
|
||||
; nIOSEL ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
||||
; nIOSTRB ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
||||
; nWE ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||
; A[*] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; A[0] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; A[1] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; A[2] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; A[3] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; A[*] ; C7M ; -25.000 ; -25.000 ; Fall ; C7M ;
|
||||
; A[0] ; C7M ; -25.000 ; -25.000 ; Fall ; C7M ;
|
||||
; A[1] ; C7M ; -25.000 ; -25.000 ; Fall ; C7M ;
|
||||
; A[2] ; C7M ; -25.000 ; -25.000 ; Fall ; C7M ;
|
||||
; A[3] ; C7M ; -25.000 ; -25.000 ; Fall ; C7M ;
|
||||
; D[*] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[0] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[1] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
@ -528,7 +540,7 @@ No paths to report.
|
||||
; D[5] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[6] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[7] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; nDEVSEL ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; nDEVSEL ; C7M ; -25.000 ; -25.000 ; Fall ; C7M ;
|
||||
; nWE ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
+-----------+------------+---------+---------+------------+-----------------+
|
||||
|
||||
@ -550,10 +562,11 @@ No paths to report.
|
||||
; RA[8] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; RA[9] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; RA[10] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; nCAS0 ; C7M ; 56.000 ; 56.000 ; Rise ; C7M ;
|
||||
; nCAS1 ; C7M ; 56.000 ; 56.000 ; Rise ; C7M ;
|
||||
; nCAS0 ; C7M ; 43.000 ; 43.000 ; Rise ; C7M ;
|
||||
; nCAS1 ; C7M ; 43.000 ; 43.000 ; Rise ; C7M ;
|
||||
; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; nRWE ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; D[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
||||
; D[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
||||
; D[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
||||
@ -602,6 +615,7 @@ No paths to report.
|
||||
; nCAS1 ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; nRWE ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; D[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
||||
; D[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
||||
; D[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
||||
@ -642,8 +656,8 @@ No paths to report.
|
||||
; A[0] ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[0] ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[0] ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[0] ; nCAS0 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[0] ; nCAS1 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[0] ; nCAS0 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[0] ; nCAS1 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[1] ; D[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[1] ; D[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[1] ; D[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
@ -652,8 +666,8 @@ No paths to report.
|
||||
; A[1] ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[1] ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[1] ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[1] ; nCAS0 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[1] ; nCAS1 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[1] ; nCAS0 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[1] ; nCAS1 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[2] ; D[0] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[2] ; D[1] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[2] ; D[2] ; ; 32.000 ; 32.000 ; ;
|
||||
@ -662,8 +676,8 @@ No paths to report.
|
||||
; A[2] ; D[5] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[2] ; D[6] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[2] ; D[7] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[2] ; nCAS0 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[2] ; nCAS1 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[2] ; nCAS0 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[2] ; nCAS1 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[3] ; D[0] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[3] ; D[1] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[3] ; D[2] ; ; 32.000 ; 32.000 ; ;
|
||||
@ -672,8 +686,8 @@ No paths to report.
|
||||
; A[3] ; D[5] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[3] ; D[6] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[3] ; D[7] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[3] ; nCAS0 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[3] ; nCAS1 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[3] ; nCAS0 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[3] ; nCAS1 ; ; 41.000 ; 41.000 ; ;
|
||||
; D[0] ; RD[0] ; 32.000 ; ; ; 32.000 ;
|
||||
; D[1] ; RD[1] ; 32.000 ; ; ; 32.000 ;
|
||||
; D[2] ; RD[2] ; 32.000 ; ; ; 32.000 ;
|
||||
@ -698,9 +712,8 @@ No paths to report.
|
||||
; nDEVSEL ; D[5] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ;
|
||||
; nDEVSEL ; D[6] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ;
|
||||
; nDEVSEL ; D[7] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ;
|
||||
; nDEVSEL ; nCAS0 ; ; 54.000 ; 54.000 ; ;
|
||||
; nDEVSEL ; nCAS1 ; ; 54.000 ; 54.000 ; ;
|
||||
; nDEVSEL ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nDEVSEL ; nCAS0 ; ; 41.000 ; 41.000 ; ;
|
||||
; nDEVSEL ; nCAS1 ; ; 41.000 ; 41.000 ; ;
|
||||
; nIOSEL ; D[0] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[1] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[2] ; ; 39.000 ; 39.000 ; ;
|
||||
@ -718,7 +731,6 @@ No paths to report.
|
||||
; nIOSEL ; RA[6] ; 32.000 ; ; ; 32.000 ;
|
||||
; nIOSEL ; RA[7] ; 32.000 ; ; ; 32.000 ;
|
||||
; nIOSEL ; nRCS ; ; 32.000 ; 32.000 ; ;
|
||||
; nIOSEL ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nIOSTRB ; D[0] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[1] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[2] ; ; 39.000 ; 39.000 ; ;
|
||||
@ -736,7 +748,6 @@ No paths to report.
|
||||
; nIOSTRB ; RA[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; nIOSTRB ; RA[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; nIOSTRB ; nRCS ; ; 32.000 ; 32.000 ; ;
|
||||
; nIOSTRB ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nWE ; D[0] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[1] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[2] ; 39.000 ; ; ; 39.000 ;
|
||||
@ -754,7 +765,7 @@ No paths to report.
|
||||
; nWE ; RD[6] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[7] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; nROE ; ; 32.000 ; 32.000 ; ;
|
||||
; nWE ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nWE ; nRWE ; ; 32.000 ; 32.000 ; ;
|
||||
+------------+-------------+--------+--------+--------+--------+
|
||||
|
||||
|
||||
@ -771,8 +782,8 @@ No paths to report.
|
||||
; A[0] ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[0] ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[0] ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[0] ; nCAS0 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[0] ; nCAS1 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[0] ; nCAS0 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[0] ; nCAS1 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[1] ; D[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[1] ; D[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[1] ; D[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
@ -781,8 +792,8 @@ No paths to report.
|
||||
; A[1] ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[1] ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[1] ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; A[1] ; nCAS0 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[1] ; nCAS1 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[1] ; nCAS0 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[1] ; nCAS1 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[2] ; D[0] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[2] ; D[1] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[2] ; D[2] ; ; 32.000 ; 32.000 ; ;
|
||||
@ -791,8 +802,8 @@ No paths to report.
|
||||
; A[2] ; D[5] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[2] ; D[6] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[2] ; D[7] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[2] ; nCAS0 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[2] ; nCAS1 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[2] ; nCAS0 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[2] ; nCAS1 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[3] ; D[0] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[3] ; D[1] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[3] ; D[2] ; ; 32.000 ; 32.000 ; ;
|
||||
@ -801,8 +812,8 @@ No paths to report.
|
||||
; A[3] ; D[5] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[3] ; D[6] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[3] ; D[7] ; ; 32.000 ; 32.000 ; ;
|
||||
; A[3] ; nCAS0 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[3] ; nCAS1 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[3] ; nCAS0 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[3] ; nCAS1 ; ; 41.000 ; 41.000 ; ;
|
||||
; D[0] ; RD[0] ; 32.000 ; ; ; 32.000 ;
|
||||
; D[1] ; RD[1] ; 32.000 ; ; ; 32.000 ;
|
||||
; D[2] ; RD[2] ; 32.000 ; ; ; 32.000 ;
|
||||
@ -827,9 +838,8 @@ No paths to report.
|
||||
; nDEVSEL ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; nDEVSEL ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; nDEVSEL ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; nDEVSEL ; nCAS0 ; ; 54.000 ; 54.000 ; ;
|
||||
; nDEVSEL ; nCAS1 ; ; 54.000 ; 54.000 ; ;
|
||||
; nDEVSEL ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nDEVSEL ; nCAS0 ; ; 41.000 ; 41.000 ; ;
|
||||
; nDEVSEL ; nCAS1 ; ; 41.000 ; 41.000 ; ;
|
||||
; nIOSEL ; D[0] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[1] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[2] ; ; 39.000 ; 39.000 ; ;
|
||||
@ -847,7 +857,6 @@ No paths to report.
|
||||
; nIOSEL ; RA[6] ; 32.000 ; ; ; 32.000 ;
|
||||
; nIOSEL ; RA[7] ; 32.000 ; ; ; 32.000 ;
|
||||
; nIOSEL ; nRCS ; ; 32.000 ; 32.000 ; ;
|
||||
; nIOSEL ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nIOSTRB ; D[0] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[1] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[2] ; ; 39.000 ; 39.000 ; ;
|
||||
@ -865,7 +874,6 @@ No paths to report.
|
||||
; nIOSTRB ; RA[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; nIOSTRB ; RA[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||
; nIOSTRB ; nRCS ; ; 32.000 ; 32.000 ; ;
|
||||
; nIOSTRB ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nWE ; D[0] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[1] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[2] ; 39.000 ; ; ; 39.000 ;
|
||||
@ -883,7 +891,7 @@ No paths to report.
|
||||
; nWE ; RD[6] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[7] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; nROE ; ; 32.000 ; 32.000 ; ;
|
||||
; nWE ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nWE ; nRWE ; ; 32.000 ; 32.000 ; ;
|
||||
+------------+-------------+--------+--------+--------+--------+
|
||||
|
||||
|
||||
@ -996,7 +1004,7 @@ No paths to report.
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; C7M ; C7M ; 95 ; 0 ; 362 ; 213 ;
|
||||
; C7M ; C7M ; 93 ; 0 ; 370 ; 215 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||
|
||||
@ -1006,7 +1014,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; C7M ; C7M ; 95 ; 0 ; 362 ; 213 ;
|
||||
; C7M ; C7M ; 93 ; 0 ; 370 ; 215 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||
|
||||
@ -1031,9 +1039,9 @@ No dedicated SERDES Receiver circuitry present in device or used in design
|
||||
; Illegal Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Input Ports ; 33 ; 33 ;
|
||||
; Unconstrained Input Port Paths ; 487 ; 487 ;
|
||||
; Unconstrained Input Port Paths ; 479 ; 479 ;
|
||||
; Unconstrained Output Ports ; 33 ; 33 ;
|
||||
; Unconstrained Output Port Paths ; 266 ; 266 ;
|
||||
; Unconstrained Output Port Paths ; 264 ; 264 ;
|
||||
+---------------------------------+-------+------+
|
||||
|
||||
|
||||
@ -1041,9 +1049,9 @@ No dedicated SERDES Receiver circuitry present in device or used in design
|
||||
; TimeQuest Timing Analyzer Messages ;
|
||||
+------------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
|
||||
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Fri Oct 18 15:02:06 2019
|
||||
Info: Processing started: Sun Oct 20 22:22:03 2019
|
||||
Info: Command: quartus_sta GR8RAM -c GR8RAM
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
@ -1059,7 +1067,7 @@ Critical Warning (332148): Timing requirements not met
|
||||
Info (332146): Worst-case setup slack is -47.500
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): -47.500 -2169.500 C7M
|
||||
Info (332119): -47.500 -2091.500 C7M
|
||||
Info (332146): Worst-case hold slack is 5.000
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
@ -1073,10 +1081,10 @@ Info (332146): Worst-case minimum pulse width slack is -4.500
|
||||
Info (332001): The selected device family is not supported by the report_metastability command.
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
|
||||
Info: Peak virtual memory: 259 megabytes
|
||||
Info: Processing ended: Fri Oct 18 15:02:11 2019
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:05
|
||||
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
|
||||
Info: Peak virtual memory: 4541 megabytes
|
||||
Info: Processing ended: Sun Oct 20 22:22:04 2019
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@ TimeQuest Timing Analyzer Summary
|
||||
|
||||
Type : Setup 'C7M'
|
||||
Slack : -47.500
|
||||
TNS : -2169.500
|
||||
TNS : -2091.500
|
||||
|
||||
Type : Hold 'C7M'
|
||||
Slack : 5.000
|
||||
|
||||
Loading…
Reference in New Issue
Block a user