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72851cefc5
GR8RAM/cpld/db/GR8RAM.map.qmsg
Zane Kaminski 72851cefc5 ugh
2021-03-19 02:56:20 -04:00

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616136944860 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 02:55:44 2021 " "Processing started: Fri Mar 19 02:55:44 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616136946282 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136946532 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136946548 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(126) " "Verilog HDL warning at gr8ram.v(126): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136946845 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(410) " "Verilog HDL warning at gr8ram.v(410): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136946845 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(545) " "Verilog HDL Expression warning at gr8ram.v(545): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 545 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136946845 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(558) " "Verilog HDL Expression warning at gr8ram.v(558): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 558 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136946845 ""}
{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946860 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616136946860 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(275) " "Verilog HDL Implicit Net warning at gr8ram.v(275): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136946860 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(278) " "Verilog HDL Implicit Net warning at gr8ram.v(278): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136946860 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616136946892 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "REGEN gr8ram.v(112) " "Verilog HDL or VHDL warning at gr8ram.v(112): object \"REGEN\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 112 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(127) " "Verilog HDL warning at gr8ram.v(127): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(280) " "Verilog HDL or VHDL warning at gr8ram.v(280): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 280 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(282) " "Verilog HDL or VHDL warning at gr8ram.v(282): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 282 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(39) " "Verilog HDL assignment warning at gr8ram.v(39): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(147) " "Verilog HDL assignment warning at gr8ram.v(147): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 147 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(154) " "Verilog HDL assignment warning at gr8ram.v(154): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(160) " "Verilog HDL assignment warning at gr8ram.v(160): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(426) " "Verilog HDL assignment warning at gr8ram.v(426): truncated value with size 32 to match size of target (4)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 426 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(547) " "Verilog HDL assignment warning at gr8ram.v(547): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 547 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(635) " "Verilog HDL assignment warning at gr8ram.v(635): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 635 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946938 "|GR8RAM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(127) " "Net \"RDout\" at gr8ram.v(127) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616136946938 "|GR8RAM"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616136947142 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616136947204 ""}
{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 181 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616136948751 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616136948751 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 88 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "RDdir VCC " "Pin \"RDdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RDdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "RCKE VCC " "Pin \"RCKE\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 448 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RCKE"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616136949454 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nIOSEL " "No output dependent on input pin \"nIOSEL\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136950063 "|GR8RAM|nIOSEL"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nIOSTRB " "No output dependent on input pin \"nIOSTRB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136950063 "|GR8RAM|nIOSTRB"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1616136950063 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "417 " "Implemented 417 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_LCELLS" "343 " "Implemented 343 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616136950095 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616136950095 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616136950376 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 02:55:50 2021 " "Processing ended: Fri Mar 19 02:55:50 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""}
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