Apple-2-HW
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GR8RAM
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Fixed previous problem, working again

This commit is contained in:
Zane Kaminski 2020-02-16 00:11:12 -05:00
parent c5f1e637ac
commit 88a4169ab6
43 changed files with 454 additions and 459 deletions
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cpld/GR8RAM.qws
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cpld/GR8RAM.v
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@ -8,7 +8,8 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
input nRES, nMode; // Reset, mode
/* PHI1 Delay */
wire [8:0] PHI1b; wire PHI1;
wire [8:0] PHI1b;
wire PHI1;
LCELL PHI1b0_MC (.in(PHI1in), .out(PHI1b[0]));
LCELL PHI1b1_MC (.in(PHI1b[0]), .out(PHI1b[1]));
LCELL PHI1b2_MC (.in(PHI1b[1]), .out(PHI1b[2]));
@ -25,11 +26,11 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
input [15:0] A; // 6502 address bus
input nWE; // 6502 R/W
output [10:0] RA; // DRAM/ROM address
assign RA[10:8] = ColAddrSel ? Addr[21:19] : Addr[10:8];
assign RA[10:8] = CASel ? Addr[21:19] : Addr[10:8];
assign RA[7:0] = (~nIOSTRB & FullIOEN) ? Bank+1 :
(~nIOSTRB & ~FullIOEN) ? {7'b0000001, Bank[0]} :
(~ColAddrSel & nIOSEL & nIOSTRB) ? Addr[18:11] :
(ColAddrSel & nIOSEL & nIOSTRB) ? Addr[7:0] : 8'h00;
(~CASel & nIOSEL & nIOSTRB) ? Addr[18:11] :
(CASel & nIOSEL & nIOSTRB) ? Addr[7:0] : 8'h00;
/* Select Signals */
wire BankSELA = A[3:0]==4'hF;
@ -48,8 +49,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
/* Data Bus Routing */
// DRAM/ROM data bus
wire RDOE = DBEN & ~nWE;
inout [7:0] RD = RDOE ? RDout : 8'bZ;
reg [7:0] RDout;
inout [7:0] RD = RDOE ? D[7:0] : 8'bZ;
// Apple II data bus
wire DOE = DBEN & nWE &
((~nDEVSEL & REGEN) | ~nIOSEL | (~nIOSTRB & IOROMEN));
@ -59,13 +59,13 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
AddrLSELA ? Addr[7:0] : 8'h00;
inout [7:0] D = DOE ? Dout : 8'bZ;
/* Inhibit output */
/* Inhibit output */
output nINH = 1'bZ;
/* DRAM and ROM Control Signals */
output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSEN); // ROM chip select
output nROE = ~nWE; // need this for flash ROM
output nRWE = ColAddrSel ? nWE : 1'b1; // for ROM & DRAM
output nRWE = CASel ? nWE : 1'b1; // for ROM & DRAM
output nRAS = ~(RASr | RASf);
output nCAS0 = ~(CAS0f | (CASr & RAMSEL & ~Addr[22])); // DRAM CAS bank 0
output nCAS1 = ~(CAS1f | (CASr & RAMSEL & Addr[22])); // DRAM CAS bank 1
@ -81,7 +81,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
// These are combined to create the CAS outputs.
reg CASr = 0, CAS0f = 0, CAS1f = 0;
reg RASr = 0, RASf = 0;
reg ColAddrSel = 0; // DRAM address multiplexer select
reg CASel = 0; // DRAM address multiplexer select
/* State Counters */
reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
@ -92,7 +92,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
/* Misc. */
reg REGEN = 0; // Register enable
reg IOROMEN = 0; // IOSTRB ROM enable
reg FullIOEN = 0; // Set to enable full IOROM space
reg FullIOEN = 0; // Set to enable full I/O ROM space
reg DBEN = 0; // Data bus driver gating
reg CSEN = 0; // ROM CS enable gating
@ -106,7 +106,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
// all 3 falling edges of C7M in PHI0 (S4, S5, S6)
// Can sample /IOSTRB at same times as /IOSEL, plus:
// 1st rising edge of C7M in PHI0 (S3)
/* State counters */
always @(posedge C7M) begin
// Synchronize state counter to S1 when just entering PHI1
@ -119,7 +119,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
// Refresh counter allows DRAM refresh once every 13 cycles
if (S==3) Ref <= (Ref[3:2]==2'b11) ? 4'h0 : Ref+1;
end
/* State-based data bus and ROM CS gating */
always @(posedge C7M, negedge nRES) begin
if (~nRES) begin
@ -139,8 +139,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
CSEN <= (S==4 & nWE) | S==5 | S==6 | S==7;
end
end
/* State-based data bus and ROM CS gating */
always @(posedge C7M, negedge nRES) begin
if (~nRES) begin
REGEN <= 0;
@ -156,7 +155,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
end
end
/* Set memory-mapped registers */
always @(negedge C7M, negedge nRES) begin
if (~nRES) begin
Addr <= 0;
@ -182,11 +180,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
Addr[23:16] <= Addr[23:16]+1;
end
// Latch 6502 write data to RD in middle of S5
if (S==5) begin
RDout[7:0] <= D[7:0];
end
// Set register in middle of S6 if accessed.
if (S==6) begin
if (BankWR) Bank[7:0] <= D[7:0]; // Bank
@ -205,24 +198,22 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
/* DRAM RAS/CAS */
always @(posedge C7M) begin
RASr <= (S==1 & Ref==0) | // Refresh
(S==4 & RAMSEL & nWE) | // Read: Early RAS
(S==5 & RAMSEL & ~nWE); // Write: Late RAS
// Multiplex DRAM address
ColAddrSel = (RAMSEL & nWE & S==4) | // Read: mux address early
(RAMSEL & ~nWE & S==5); // Write: mux address late
// Read: long, early CAS, gated later by RAMSEL
CASr <= (RAMSEL & ~nWE & (S==5 | S==6 | S==7));
RASr <= (S==1 & Ref==0) | // Refresh
(S==4 & RAMSEL & nWE) | // Read: Early RAS
(S==5 & RAMSEL & ~nWE); // Write: Late RAS
CASel = (RAMSEL & nWE & S==4) | // Read: mux address early
(RAMSEL & ~nWE & S==5); // Write: mux address late
// Read: long, early CAS, gated later by RAMSEL
CASr <= (nWE & (S==5 | S==6 | S==7));
end
always @(negedge C7M) begin
RASf <= (S==4 & RAMSEL & nWE) | // Read: Early RAS
(S==5 & RAMSEL & ~nWE); // Write: Late RAS
CAS0f <= (S==1 & Ref==0) | // Refresh
(S==6 & RAMSEL & ~Addr[22] & ~nWE); // Write: Late CAS
CAS1f <= (S==1 & Ref==0) | // Refresh
(S==6 & RAMSEL & Addr[22] & ~nWE); // Write: Late CAS
RASf <= (S==4 & RAMSEL & nWE) | // Read: Early RAS
(S==5 & RAMSEL & ~nWE); // Write: Late RAS
CAS0f <= (S==1 & Ref==0) | // Refresh
(S==5 & RAMSEL & ~Addr[22] & nWE) | // Read: Early CAS
(S==6 & RAMSEL & ~Addr[22] & ~nWE); // Write: Late CAS
CAS1f <= (S==1 & Ref==0) | // Refresh
(S==5 & RAMSEL & Addr[22] & nWE) | // Read: Early CAS
(S==6 & RAMSEL & Addr[22] & ~nWE); // Write: Late CAS
end
endmodule
endmodule

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cpld/db/GR8RAM.asm.qmsg
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@ -1,5 +1,5 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571624522334 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571624522335 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:22:02 2019 " "Processing started: Sun Oct 20 22:22:02 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571624522335 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571624522335 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571624522335 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571624522453 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571624522603 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:22:02 2019 " "Processing ended: Sun Oct 20 22:22:02 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571624522603 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571624522603 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571624522603 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571624522603 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581829847188 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581829847188 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 16 00:10:47 2020 " "Processing started: Sun Feb 16 00:10:47 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581829847188 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1581829847188 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1581829847188 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1581829847318 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581829847468 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 00:10:47 2020 " "Processing ended: Sun Feb 16 00:10:47 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581829847468 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581829847468 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581829847468 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1581829847468 ""}

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cpld/db/GR8RAM.db_info
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@ -1,3 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Sun Oct 20 21:50:21 2019
Creation_Time = Sat Feb 15 22:14:18 2020

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cpld/db/GR8RAM.fit.qmsg
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@ -1,3 +1,3 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571624521309 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571624521311 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571624521519 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:22:01 2019 " "Processing ended: Sun Oct 20 22:22:01 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571624521519 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571624521519 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571624521519 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571624521519 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1581829846147 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1581829846157 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581829846367 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 00:10:46 2020 " "Processing ended: Sun Feb 16 00:10:46 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581829846367 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581829846367 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581829846367 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1581829846367 ""}

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cpld/db/GR8RAM.hier_info
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@ -1,11 +1,12 @@
|GR8RAM
C7M => always1.IN0
C7M => always3.IN0
C7M => CASr.CLK
C7M => CASel.CLK
C7M => RASr.CLK
C7M => ASel.CLK
C7M => CSDBEN.CLK
C7M => IOROMEN.CLK
C7M => REGEN.CLK
C7M => CSEN.CLK
C7M => DBEN.CLK
C7M => Ref[0].CLK
C7M => Ref[1].CLK
C7M => Ref[2].CLK
@ -20,7 +21,7 @@ Q3 => ~NO_FANOUT~
PHI0in => ~NO_FANOUT~
PHI1in => comb.IN0
PHI1in => PHI1b0_MC.DATAIN
nRES => always0.IN0
nRES => always1.IN0
nMode => ~NO_FANOUT~
A[0] => Equal0.IN7
A[0] => Equal1.IN7
@ -28,35 +29,35 @@ A[0] => Equal2.IN7
A[0] => Equal3.IN7
A[0] => Equal4.IN7
A[0] => Equal5.IN7
A[0] => Equal12.IN21
A[0] => Equal13.IN21
A[1] => Equal0.IN6
A[1] => Equal1.IN6
A[1] => Equal2.IN6
A[1] => Equal3.IN6
A[1] => Equal4.IN6
A[1] => Equal5.IN6
A[1] => Equal12.IN20
A[1] => Equal13.IN20
A[2] => Equal0.IN5
A[2] => Equal1.IN5
A[2] => Equal2.IN5
A[2] => Equal3.IN5
A[2] => Equal4.IN5
A[2] => Equal5.IN5
A[2] => Equal12.IN19
A[2] => Equal13.IN19
A[3] => Equal0.IN4
A[3] => Equal1.IN4
A[3] => Equal2.IN4
A[3] => Equal3.IN4
A[3] => Equal4.IN4
A[3] => Equal5.IN4
A[3] => Equal12.IN18
A[4] => Equal12.IN17
A[5] => Equal12.IN16
A[6] => Equal12.IN15
A[7] => Equal12.IN14
A[8] => Equal12.IN13
A[9] => Equal12.IN12
A[10] => Equal12.IN11
A[3] => Equal13.IN18
A[4] => Equal13.IN17
A[5] => Equal13.IN16
A[6] => Equal13.IN15
A[7] => Equal13.IN14
A[8] => Equal13.IN13
A[9] => Equal13.IN12
A[10] => Equal13.IN11
A[11] => ~NO_FANOUT~
A[12] => ~NO_FANOUT~
A[13] => ~NO_FANOUT~
@ -80,9 +81,10 @@ nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN1
nWE => comb.DATAB
nWE => CSEN.IN1
nWE => RASr.IN1
nWE => ASel.IN0
nWE => CASel.IN0
nWE => CASr.IN1
nWE => CAS0f.IN1
nWE => CAS1f.IN1

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@ -1,33 +1,33 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571624519346 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571624519347 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:21:59 2019 " "Processing started: Sun Oct 20 22:21:59 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571624519347 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571624519347 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571624519347 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571624519549 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571624519575 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571624519575 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(190) " "Verilog HDL information at GR8RAM.v(190): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 190 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1571624519575 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571624519576 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571624519576 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571624519612 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571624519617 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(122) " "Verilog HDL assignment warning at GR8RAM.v(122): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 122 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571624519619 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(127) " "Verilog HDL assignment warning at GR8RAM.v(127): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 127 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571624519619 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(159) " "Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571624519620 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(164) " "Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571624519620 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(170) " "Verilog HDL assignment warning at GR8RAM.v(170): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 170 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571624519620 "|GR8RAM"}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519747 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571624519747 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519747 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519747 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519747 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 170 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519747 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571624519747 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519772 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519772 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519772 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519772 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571624519772 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624519789 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519789 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519789 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519789 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519789 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571624519789 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519803 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519813 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519815 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519828 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519839 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571624519840 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1571624519917 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1571624519917 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1571624520013 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1571624520013 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1571624520013 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "9 " "Design contains 9 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "C7M_2 " "No output dependent on input pin \"C7M_2\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|C7M_2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571624520210 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1571624520210 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "168 " "Implemented 168 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571624520210 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571624520210 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1571624520210 ""} { "Info" "ICUT_CUT_TM_MCELLS" "106 " "Implemented 106 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1571624520210 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1571624520210 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571624520210 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1571624520252 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571624520292 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:22:00 2019 " "Processing ended: Sun Oct 20 22:22:00 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571624520292 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571624520292 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571624520292 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571624520292 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581829844214 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581829844214 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 16 00:10:44 2020 " "Processing started: Sun Feb 16 00:10:44 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581829844214 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1581829844214 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1581829844214 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1581829844423 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1581829844453 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1581829844453 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(200) " "Verilog HDL information at GR8RAM.v(200): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 200 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1581829844453 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1581829844453 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1581829844453 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1581829844488 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581829844493 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(115) " "Verilog HDL assignment warning at GR8RAM.v(115): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 115 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581829844493 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(120) " "Verilog HDL assignment warning at GR8RAM.v(120): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 120 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581829844493 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(169) " "Verilog HDL assignment warning at GR8RAM.v(169): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 169 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581829844493 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581829844493 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(180) " "Verilog HDL assignment warning at GR8RAM.v(180): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 180 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581829844493 "|GR8RAM"}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844565 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1581829844565 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844565 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844565 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 169 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844565 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 180 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844565 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1581829844565 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844593 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844593 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844593 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844593 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1581829844593 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844613 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844613 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844613 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844613 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844613 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1581829844613 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844623 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844633 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844633 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844653 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844663 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844665 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1581829844723 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1581829844723 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1581829844823 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1581829844823 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1581829844823 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "9 " "Design contains 9 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "C7M_2 " "No output dependent on input pin \"C7M_2\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|C7M_2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1581829845013 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "169 " "Implemented 169 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1581829845013 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1581829845013 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1581829845013 ""} { "Info" "ICUT_CUT_TM_MCELLS" "107 " "Implemented 107 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1581829845013 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1581829845013 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1581829845013 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1581829845053 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581829845103 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 00:10:45 2020 " "Processing ended: Sun Feb 16 00:10:45 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581829845103 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581829845103 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581829845103 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581829845103 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571624523519 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523519 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:22:03 2019 " "Processing started: Sun Oct 20 22:22:03 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571624523519 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571624523519 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571624523520 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571624523576 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571624523668 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571624523675 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571624523678 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1571624523705 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571624523717 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571624523717 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523718 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523718 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571624523720 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1571624523730 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523734 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523734 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -2091.500 C7M " " -47.500 -2091.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523734 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571624523734 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 5.000 " "Worst-case hold slack is 5.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523898 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571624523898 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571624523903 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571624523908 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.500 " "Worst-case minimum pulse width slack is -4.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523913 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523913 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -486.000 C7M " " -4.500 -486.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571624523913 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571624523913 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1571624523954 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571624523975 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571624523976 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4541 " "Peak virtual memory: 4541 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571624524127 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:22:04 2019 " "Processing ended: Sun Oct 20 22:22:04 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571624524127 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571624524127 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571624524127 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571624524127 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581829848408 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848408 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 16 00:10:48 2020 " "Processing started: Sun Feb 16 00:10:48 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581829848408 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1581829848408 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1581829848408 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1581829848468 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1581829848558 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1581829848568 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1581829848568 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1581829848588 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1581829848613 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1581829848614 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848614 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848614 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1581829848616 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1581829848627 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848630 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848630 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -2116.500 C7M " " -47.500 -2116.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848630 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581829848630 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 5.000 " "Worst-case hold slack is 5.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848633 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848633 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848633 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581829848633 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1581829848637 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1581829848640 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.500 " "Worst-case minimum pulse width slack is -4.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848644 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848644 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -495.000 C7M " " -4.500 -495.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848644 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581829848644 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1581829848693 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1581829848718 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1581829848718 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581829848889 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 00:10:48 2020 " "Processing ended: Sun Feb 16 00:10:48 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581829848889 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581829848889 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581829848889 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581829848889 ""}

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start_full_compilation:s:00:00:05
start_analysis_synthesis:s:00:00:01-start_full_compilation
start_full_compilation:s:00:00:06
start_analysis_synthesis:s:00:00:02-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:02-start_full_compilation
start_assembler:s:00:00:01-start_full_compilation
start_fitter:s:00:00:01-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation
start_timing_analyzer:s:00:00:01-start_full_compilation

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@ -1,71 +1,71 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571623531253 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571623531253 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:05:31 2019 " "Processing started: Sun Oct 20 22:05:31 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571623531253 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571623531253 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571623531253 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571623531456 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571623531485 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571623531485 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(197) " "Verilog HDL information at GR8RAM.v(197): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 197 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1571623531485 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571623531487 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571623531487 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571623531521 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571623531523 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(129) " "Verilog HDL assignment warning at GR8RAM.v(129): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 129 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571623531523 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 134 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571623531523 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(166) " "Verilog HDL assignment warning at GR8RAM.v(166): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 166 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571623531523 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(171) " "Verilog HDL assignment warning at GR8RAM.v(171): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 171 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571623531523 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(177) " "Verilog HDL assignment warning at GR8RAM.v(177): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 177 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571623531523 "|GR8RAM"}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531597 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571623531597 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531597 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 171 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531597 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 166 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531597 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 177 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531597 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571623531597 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531626 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531626 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531626 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531626 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571623531626 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623531643 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531644 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531644 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531644 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531644 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571623531644 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531657 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531667 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531668 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531680 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531690 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571623531691 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1571623531758 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1571623531758 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1571623531853 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1571623531853 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1571623531853 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "9 " "Design contains 9 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "C7M_2 " "No output dependent on input pin \"C7M_2\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|C7M_2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571623532033 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1571623532033 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "168 " "Implemented 168 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571623532034 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571623532034 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1571623532034 ""} { "Info" "ICUT_CUT_TM_MCELLS" "106 " "Implemented 106 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1571623532034 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1571623532034 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571623532034 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1571623532078 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571623532115 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:05:32 2019 " "Processing ended: Sun Oct 20 22:05:32 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571623532115 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571623532115 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571623532115 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571623532115 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571623533057 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571623533058 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:05:32 2019 " "Processing started: Sun Oct 20 22:05:32 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571623533058 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1571623533058 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1571623533058 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1571623533109 ""}
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1571623533109 ""}
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1571623533109 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571623533148 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571623533150 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571623533356 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:05:33 2019 " "Processing ended: Sun Oct 20 22:05:33 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571623533356 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571623533356 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571623533356 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571623533356 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1571623534188 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571623534188 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:05:34 2019 " "Processing started: Sun Oct 20 22:05:34 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571623534188 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571623534188 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571623534188 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571623534305 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571623534439 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:05:34 2019 " "Processing ended: Sun Oct 20 22:05:34 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571623534439 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571623534439 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571623534439 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571623534439 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1571623535072 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1571623535392 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535392 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 20 22:05:35 2019 " "Processing started: Sun Oct 20 22:05:35 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571623535392 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571623535392 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571623535392 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571623535447 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571623535537 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571623535545 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571623535548 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1571623535571 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571623535583 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571623535584 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535584 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535584 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571623535586 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1571623535595 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535600 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535600 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -2078.500 C7M " " -47.500 -2078.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535600 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571623535600 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 5.000 " "Worst-case hold slack is 5.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535763 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571623535763 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571623535769 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571623535773 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.500 " "Worst-case minimum pulse width slack is -4.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -486.000 C7M " " -4.500 -486.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571623535779 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571623535779 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1571623535819 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571623535842 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571623535843 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571623535997 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 20 22:05:35 2019 " "Processing ended: Sun Oct 20 22:05:35 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571623535997 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571623535997 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571623535997 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571623535997 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 22 s " "Quartus II Full Compilation was successful. 0 errors, 22 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571623536620 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581827612363 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581827612363 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 15 23:33:32 2020 " "Processing started: Sat Feb 15 23:33:32 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581827612363 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1581827612363 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1581827612363 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1581827612572 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1581827612602 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1581827612602 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(200) " "Verilog HDL information at GR8RAM.v(200): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 200 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1581827612602 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1581827612607 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1581827612607 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1581827612642 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581827612642 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(115) " "Verilog HDL assignment warning at GR8RAM.v(115): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 115 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581827612642 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(120) " "Verilog HDL assignment warning at GR8RAM.v(120): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 120 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581827612642 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(169) " "Verilog HDL assignment warning at GR8RAM.v(169): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 169 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581827612642 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581827612642 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(180) " "Verilog HDL assignment warning at GR8RAM.v(180): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 180 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581827612642 "|GR8RAM"}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612737 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1581827612737 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612743 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612743 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 169 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612743 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 180 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612743 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1581827612743 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612763 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612763 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612763 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612763 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1581827612763 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612787 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612787 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1581827612787 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612802 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612813 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612813 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612827 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612832 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612832 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1581827612902 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1581827612902 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1581827613002 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1581827613002 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1581827613002 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "9 " "Design contains 9 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "C7M_2 " "No output dependent on input pin \"C7M_2\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|C7M_2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1581827613192 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "169 " "Implemented 169 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1581827613192 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1581827613192 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1581827613192 ""} { "Info" "ICUT_CUT_TM_MCELLS" "107 " "Implemented 107 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1581827613192 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1581827613192 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1581827613192 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1581827613227 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4588 " "Peak virtual memory: 4588 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581827613272 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 15 23:33:33 2020 " "Processing ended: Sat Feb 15 23:33:33 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581827613272 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581827613272 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581827613272 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581827613272 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581827614218 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581827614218 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 15 23:33:33 2020 " "Processing started: Sat Feb 15 23:33:33 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581827614218 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1581827614218 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1581827614218 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1581827614268 ""}
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1581827614278 ""}
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1581827614278 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1581827614308 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1581827614318 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581827614528 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 15 23:33:34 2020 " "Processing ended: Sat Feb 15 23:33:34 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581827614528 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581827614528 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581827614528 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1581827614528 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1581827615368 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581827615368 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 15 23:33:35 2020 " "Processing started: Sat Feb 15 23:33:35 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581827615368 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1581827615368 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1581827615368 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1581827615488 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581827615618 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 15 23:33:35 2020 " "Processing ended: Sat Feb 15 23:33:35 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581827615618 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581827615618 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581827615618 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1581827615618 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1581827616228 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1581827616568 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616568 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 15 23:33:36 2020 " "Processing started: Sat Feb 15 23:33:36 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581827616568 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1581827616568 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1581827616568 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1581827616618 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1581827616718 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1581827616718 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1581827616718 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1581827616748 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1581827616758 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1581827616758 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616758 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616758 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1581827616758 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1581827616768 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -2116.500 C7M " " -47.500 -2116.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 5.000 " "Worst-case hold slack is 5.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1581827616778 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1581827616788 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.500 " "Worst-case minimum pulse width slack is -4.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616788 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616788 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -495.000 C7M " " -4.500 -495.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616788 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581827616788 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1581827616828 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1581827616848 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1581827616848 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581827617058 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 15 23:33:37 2020 " "Processing ended: Sat Feb 15 23:33:37 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581827617058 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581827617058 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581827617058 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581827617058 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 22 s " "Quartus II Full Compilation was successful. 0 errors, 22 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581827617678 ""}

10
cpld/output_files/GR8RAM.asm.rpt
View File

@ -1,5 +1,5 @@
Assembler report for GR8RAM
Sun Oct 20 22:22:02 2019
Sun Feb 16 00:10:47 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Oct 20 22:22:02 2019 ;
; Assembler Status ; Successful - Sun Feb 16 00:10:47 2020 ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX7000S ;
@ -89,7 +89,7 @@ applicable agreement for further details.
+----------------+-----------------------------------------------------------------------------+
; Device ; EPM7128SLC84-15 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x0017AD2A ;
; Checksum ; 0x0017BCCA ;
+----------------+-----------------------------------------------------------------------------+
@ -99,12 +99,12 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun Oct 20 22:22:02 2019
Info: Processing started: Sun Feb 16 00:10:47 2020
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4522 megabytes
Info: Processing ended: Sun Oct 20 22:22:02 2019
Info: Processing ended: Sun Feb 16 00:10:47 2020
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

4
cpld/output_files/GR8RAM.cdf
View File

@ -3,8 +3,8 @@ JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPM7128SL84) Path("C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(3));
P ActionCode(Vfy)
Device PartName(EPM7128SL84) Path("C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(2));
ChainEnd;

2
cpld/output_files/GR8RAM.done
View File

@ -1 +1 @@
Sun Oct 20 22:22:04 2019
Sun Feb 16 00:10:49 2020

324
cpld/output_files/GR8RAM.fit.rpt
View File

@ -1,5 +1,5 @@
Fitter report for GR8RAM
Sun Oct 20 22:22:01 2019
Sun Feb 16 00:10:46 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -55,14 +55,14 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Sun Oct 20 22:22:01 2019 ;
; Fitter Status ; Successful - Sun Feb 16 00:10:46 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX7000S ;
; Device ; EPM7128SLC84-15 ;
; Timing Models ; Final ;
; Total macrocells ; 106 / 128 ( 83 % ) ;
; Total macrocells ; 107 / 128 ( 84 % ) ;
; Total pins ; 65 / 68 ( 96 % ) ;
+---------------------------+-------------------------------------------------+
@ -109,9 +109,9 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/outp
+------------------------------+--------------------+
; Resource ; Usage ;
+------------------------------+--------------------+
; Logic cells ; 106 / 128 ( 83 % ) ;
; Registers ; 54 / 128 ( 42 % ) ;
; Number of pterms used ; 274 ;
; Logic cells ; 107 / 128 ( 84 % ) ;
; Registers ; 55 / 128 ( 43 % ) ;
; Number of pterms used ; 281 ;
; I/O pins ; 65 / 68 ( 96 % ) ;
; -- Clock pins ; 2 / 2 ( 100 % ) ;
; -- Dedicated input pins ; 2 / 2 ( 100 % ) ;
@ -120,10 +120,10 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/outp
; Shareable expanders ; 1 / 128 ( < 1 % ) ;
; Parallel expanders ; 0 / 120 ( 0 % ) ;
; Cells using turbo bit ; 17 / 128 ( 13 % ) ;
; Maximum fan-out ; 54 ;
; Maximum fan-out ; 55 ;
; Highest non-global fan-out ; 54 ;
; Total fan-out ; 864 ;
; Average fan-out ; 5.02 ;
; Total fan-out ; 855 ;
; Average fan-out ; 4.94 ;
+------------------------------+--------------------+
@ -148,7 +148,7 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/outp
; A[7] ; 5 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
; A[8] ; 9 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
; A[9] ; 10 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
; C7M ; 83 ; -- ; -- ; 54 ; 0 ; yes ; no ; TTL ; User ;
; C7M ; 83 ; -- ; -- ; 55 ; 0 ; yes ; no ; TTL ; User ;
; C7M_2 ; 84 ; -- ; -- ; 0 ; 0 ; no ; no ; TTL ; User ;
; PHI0in ; 8 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
; PHI1in ; 2 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ;
@ -157,8 +157,8 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/outp
; nIOSEL ; 74 ; -- ; 8 ; 12 ; 0 ; no ; no ; TTL ; User ;
; nIOSTRB ; 24 ; -- ; 3 ; 11 ; 0 ; no ; no ; TTL ; User ;
; nMode ; 44 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ;
; nRES ; 1 ; -- ; -- ; 54 ; 0 ; yes ; no ; TTL ; User ;
; nWE ; 20 ; -- ; 2 ; 15 ; 0 ; no ; no ; TTL ; User ;
; nRES ; 1 ; -- ; -- ; 40 ; 0 ; yes ; no ; TTL ; User ;
; nWE ; 20 ; -- ; 2 ; 16 ; 0 ; no ; no ; TTL ; User ;
+---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
@ -343,7 +343,7 @@ Note: User assignments will override these defaults. The user specified values a
+----------------------------+------------+------+-------------------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+-------------------------------+--------------+
; |GR8RAM ; 106 ; 65 ; |GR8RAM ; work ;
; |GR8RAM ; 107 ; 65 ; |GR8RAM ; work ;
; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ;
+----------------------------+------------+------+-------------------------------+--------------+
@ -353,15 +353,15 @@ Note: User assignments will override these defaults. The user specified values a
+-----------+----------+---------+--------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-----------+----------+---------+--------------+--------+----------------------+------------------+
; BankWR_MC ; LC44 ; 8 ; Clock enable ; no ; -- ; -- ;
; C7M ; PIN_83 ; 54 ; Clock ; yes ; On ; -- ;
; PHI1b9_MC ; LC114 ; 5 ; Clock enable ; no ; -- ; -- ;
; S[0] ; LC113 ; 52 ; Clock enable ; no ; -- ; -- ;
; S[1] ; LC124 ; 51 ; Clock enable ; no ; -- ; -- ;
; S[2] ; LC118 ; 54 ; Clock enable ; no ; -- ; -- ;
; SetWR_MC ; LC35 ; 1 ; Clock enable ; no ; -- ; -- ;
; BankWR_MC ; LC33 ; 8 ; Clock enable ; no ; -- ; -- ;
; C7M ; PIN_83 ; 55 ; Clock ; yes ; On ; -- ;
; PHI1b9_MC ; LC46 ; 5 ; Clock enable ; no ; -- ; -- ;
; S[0] ; LC114 ; 52 ; Clock enable ; no ; -- ; -- ;
; S[1] ; LC118 ; 53 ; Clock enable ; no ; -- ; -- ;
; S[2] ; LC113 ; 54 ; Clock enable ; no ; -- ; -- ;
; SetWR_MC ; LC42 ; 1 ; Clock enable ; no ; -- ; -- ;
; nIOSEL ; PIN_74 ; 12 ; Clock enable ; no ; -- ; -- ;
; nRES ; PIN_1 ; 54 ; Async. clear ; yes ; On ; -- ;
; nRES ; PIN_1 ; 40 ; Async. clear ; yes ; On ; -- ;
+-----------+----------+---------+--------------+--------+----------------------+------------------+
@ -370,8 +370,8 @@ Note: User assignments will override these defaults. The user specified values a
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; C7M ; PIN_83 ; 54 ; On ; -- ;
; nRES ; PIN_1 ; 54 ; On ; -- ;
; C7M ; PIN_83 ; 55 ; On ; -- ;
; nRES ; PIN_1 ; 40 ; On ; -- ;
+------+----------+---------+----------------------+------------------+
@ -381,19 +381,19 @@ Note: User assignments will override these defaults. The user specified values a
; Name ; Fan-Out ;
+-------------------------------+---------+
; S[2] ; 54 ;
; S[1] ; 53 ;
; S[0] ; 52 ;
; S[1] ; 51 ;
; nWE ; 16 ;
; nDEVSEL ; 15 ;
; nWE ; 15 ;
; A[3] ; 15 ;
; A[2] ; 15 ;
; A[1] ; 15 ;
; A[0] ; 15 ;
; nIOSEL ; 12 ;
; CASel ; 12 ;
; nIOSTRB ; 11 ;
; Addr[8] ; 11 ;
; Addr[0] ; 11 ;
; ASel ; 11 ;
; IncAddrL ; 11 ;
; IncAddrM ; 10 ;
; Addr[9] ; 10 ;
@ -423,8 +423,8 @@ Note: User assignments will override these defaults. The user specified values a
; Bank[1] ; 7 ;
; lpm_counter:Ref_rtl_0|dffs[3] ; 7 ;
; lpm_counter:Ref_rtl_0|dffs[2] ; 7 ;
; lpm_counter:Ref_rtl_0|dffs[0] ; 7 ;
; REGEN ; 7 ;
; lpm_counter:Ref_rtl_0|dffs[0] ; 7 ;
; D[6]~6 ; 6 ;
; D[5]~5 ; 6 ;
; D[4]~4 ; 6 ;
@ -447,13 +447,13 @@ Note: User assignments will override these defaults. The user specified values a
; Bank[4] ; 4 ;
; Bank[5] ; 3 ;
; IOROMEN ; 3 ;
; CSDBEN ; 3 ;
; PHI0seen ; 3 ;
; PHI1reg ; 3 ;
; PHI0seen ; 3 ;
; PHI1in ; 2 ;
; Addr[23] ; 2 ;
; Bank[6] ; 2 ;
; CASr ; 2 ;
; DBEN ; 2 ;
; RD[7]~7 ; 1 ;
; RD[6]~6 ; 1 ;
; RD[5]~5 ; 1 ;
@ -480,19 +480,20 @@ Note: User assignments will override these defaults. The user specified values a
; RA~74 ; 1 ;
; Bank[7] ; 1 ;
; IncAddrM~9 ; 1 ;
; comb~38 ; 1 ;
; comb~34 ; 1 ;
; comb~30 ; 1 ;
; CAS0f ; 1 ;
; CAS1f ; 1 ;
; CAS0f ; 1 ;
; RA~69 ; 1 ;
; RA~66 ; 1 ;
; RA~63 ; 1 ;
; comb~27 ; 1 ;
; comb~31 ; 1 ;
; RASr ; 1 ;
; comb~25 ; 1 ;
; comb~28 ; 1 ;
; RASf ; 1 ;
; comb~26 ; 1 ;
; SetWR_MC ; 1 ;
; ASel~10 ; 1 ;
; CSEN ; 1 ;
; PHI1b8_MC ; 1 ;
; PHI1b7_MC ; 1 ;
; PHI1b6_MC ; 1 ;
@ -528,15 +529,15 @@ Note: User assignments will override these defaults. The user specified values a
; Other Routing Resource Type ; Usage ;
+-----------------------------+--------------------+
; Output enables ; 2 / 6 ( 33 % ) ;
; PIA buffers ; 227 / 288 ( 79 % ) ;
; PIAs ; 255 / 288 ( 89 % ) ;
; PIA buffers ; 219 / 288 ( 76 % ) ;
; PIAs ; 246 / 288 ( 85 % ) ;
+-----------------------------+--------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 31.88) ; Number of LABs (Total = 8) ;
; LAB External Interconnects (Average = 30.75) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ;
@ -545,10 +546,10 @@ Note: User assignments will override these defaults. The user specified values a
; 12 - 14 ; 0 ;
; 15 - 17 ; 0 ;
; 18 - 20 ; 0 ;
; 21 - 23 ; 0 ;
; 21 - 23 ; 1 ;
; 24 - 26 ; 0 ;
; 27 - 29 ; 0 ;
; 30 - 32 ; 5 ;
; 27 - 29 ; 1 ;
; 30 - 32 ; 3 ;
; 33 - 35 ; 3 ;
+-----------------------------------------------+-----------------------------+
@ -556,7 +557,7 @@ Note: User assignments will override these defaults. The user specified values a
+-----------------------------------------------------------------------+
; LAB Macrocells ;
+-----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 13.25) ; Number of LABs (Total = 8) ;
; Number of Macrocells (Average = 13.38) ; Number of LABs (Total = 8) ;
+-----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
@ -566,15 +567,15 @@ Note: User assignments will override these defaults. The user specified values a
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 1 ;
; 12 ; 2 ;
; 13 ; 1 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 3 ;
; 16 ; 5 ;
+-----------------------------------------+-----------------------------+
@ -588,118 +589,119 @@ Note: User assignments will override these defaults. The user specified values a
+-------------------------------------------------+-----------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[0], S[2], S[1], Addr[5], IncAddrL, Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[5]~108, Addr[5], Addr[6], Addr[7], IncAddrM, RA~95 ;
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[0], S[2], S[1], Addr[4], IncAddrL, Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[4]~102, Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~88 ;
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[0], S[2], S[1], Addr[3], IncAddrL, Addr[2], Addr[1], Addr[0] ; Dout[3]~96, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~81 ;
; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], IncAddrM, Addr[8] ; Dout[1]~84, Addr[9], Addr[10], Addr[11], RA~66, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[0], S[2], S[1], Addr[2], IncAddrL, Addr[1], Addr[0] ; Dout[2]~90, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~80 ;
; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], IncAddrM ; Dout[0]~78, Addr[8], Addr[9], Addr[10], Addr[11], RA~63, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[0], S[2], S[1], Addr[1], IncAddrL, Addr[0] ; Dout[1]~84, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~121 ;
; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[0], S[2], S[1], Addr[7], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[7]~120, Addr[7], IncAddrM, RA~109 ;
; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[0], S[2], S[1], Addr[6], IncAddrL, Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[6]~114, Addr[6], Addr[7], IncAddrM, RA~102 ;
; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[0], S[2], S[1], Addr[0], IncAddrL ; Dout[0]~78, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~74 ;
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], IncAddrM, Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[6]~114, Addr[14], Addr[15], IncAddrH, RA~81 ;
; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], IncAddrM, Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[5]~108, Addr[13], Addr[14], Addr[15], IncAddrH, RA~80 ;
; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], IncAddrM, Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[4]~102, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~121 ;
; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], IncAddrM, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[7]~120, Addr[15], IncAddrH, RA~88 ;
; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], IncAddrM, Addr[10], Addr[9], Addr[8] ; Dout[3]~96, Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~74 ;
; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], IncAddrM, Addr[9], Addr[8] ; Dout[2]~90, Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], RA~69, Addr[15], IncAddrH ;
; B ; LC17 ; ; nINH ;
; B ; LC25 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[0], S[1], Addr[18], IncAddrH, Addr[17], Addr[16] ; Dout[2]~90, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~109 ;
; B ; LC24 ; C7M, nRES, D[1], BankWR_MC, S[0], S[2], S[1] ; RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ;
; B ; LC31 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[0], S[1], Addr[17], IncAddrH, Addr[16] ; Dout[1]~84, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~102 ;
; B ; LC32 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[0], S[1], Addr[19], IncAddrH, Addr[18], Addr[17], Addr[16] ; Dout[3]~96, Addr[19], RA~63, Addr[20], Addr[21], Addr[22], Addr[23] ;
; B ; LC20 ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[0], S[1], Addr[20], IncAddrH, Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[4]~102, Addr[20], RA~66, Addr[21], Addr[22], Addr[23] ;
; B ; LC27 ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[0], S[1], Addr[21], IncAddrH, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[5]~108, Addr[21], RA~69, Addr[22], Addr[23] ;
; B ; LC19 ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[0], S[1], Addr[22], IncAddrH, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[6]~114, Addr[22], CAS1f, CAS0f, comb~30, comb~34, Addr[23] ;
; B ; LC28 ; C7M, nRES, D[6], BankWR_MC, S[0], S[2], S[1] ; RA~102, RA~109 ;
; B ; LC21 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~25 ;
; B ; LC29 ; C7M, nRES, D[7], AddrLWR_MC, Addr[7], S[2], S[1], S[0], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrM, IncAddrM~9 ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrM, Addr[15], IncAddrH ;
; B ; LC30 ; C7M, nRES, D[7], AddrHWR_MC, S[2], S[0], S[1], Addr[23], IncAddrH, Addr[22], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[7]~120, Addr[23] ;
; C ; LC34 ; C7M, nRES, D[0], AddrHWR_MC, S[1], S[2], Addr[16], S[0], IncAddrH ; Dout[0]~78, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~95 ;
; C ; LC46 ; A[0], A[1], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ;
; C ; LC44 ; nWE, REGEN, nDEVSEL, A[0], A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ;
; C ; LC33 ; C7M, nRES, S[0], nWE, RAMSEL_MC, S[1], S[2] ; comb~27 ;
; C ; LC42 ; PHI1b0_MC ; PHI1b2_MC ;
; C ; LC38 ; RD[4], nDEVSEL, A[1], A[0], A[2], A[3], Addr[20], Addr[12], Addr[4] ; D[4] ;
; C ; LC40 ; RD[5], nDEVSEL, A[1], A[0], A[2], A[3], Addr[21], Addr[13], Addr[5] ; D[5] ;
; C ; LC43 ; RD[6], nDEVSEL, A[1], A[0], A[2], A[3], Addr[22], Addr[14], Addr[6] ; D[6] ;
; C ; LC45 ; RD[7], nDEVSEL, A[1], A[0], A[2], A[3], Addr[23], Addr[15], Addr[7] ; D[7] ;
; C ; LC35 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; FullIOEN ;
; C ; LC36 ; REGEN, nDEVSEL, A[0], A[1], A[2], A[3] ; IncAddrL, ASel, RASf, RASr, CAS1f, CAS0f, comb~30, comb~34 ;
; C ; LC48 ; A[0], A[1], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23] ;
; C ; LC41 ; A[0], A[1], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
; D ; LC56 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
; D ; LC59 ; RD[1], nDEVSEL, A[1], A[0], A[2], A[3], Addr[17], Addr[9], Addr[1] ; D[1] ;
; D ; LC61 ; RD[2], nDEVSEL, A[1], A[0], A[2], A[3], Addr[18], Addr[10], Addr[2] ; D[2] ;
; D ; LC64 ; RD[3], nDEVSEL, A[1], A[0], A[2], A[3], Addr[19], Addr[11], Addr[3] ; D[3] ;
; D ; LC57 ; RD[0], nDEVSEL, A[1], A[0], A[2], A[3], Addr[16], Addr[8], Addr[0] ; D[0] ;
; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ;
; D ; LC51 ; CASr, Addr[22], RAMSEL_MC, CAS1f ; nCAS1 ;
; D ; LC53 ; CASr, Addr[22], RAMSEL_MC, CAS0f ; nCAS0 ;
; D ; LC62 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; D ; LC52 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; E ; LC79 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1], IncAddrL ; IncAddrL, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM~9, IncAddrM ;
; E ; LC75 ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2] ; RA[2] ;
; E ; LC72 ; Addr[21], ASel, Addr[10] ; RA[10] ;
; E ; LC78 ; C7M, nRES, D[0], BankWR_MC, S[0], S[2], S[1] ; RA~74, RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ;
; E ; LC73 ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ;
; E ; LC74 ; C7M, nRES, S[1], S[2], nWE, S[0] ; comb~30, comb~34 ;
; E ; LC68 ; C7M, nRES, D[7], BankWR_MC, S[0], S[2], S[1] ; RA~109 ;
; E ; LC77 ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ;
; E ; LC67 ; nWE ; nROE ;
; E ; LC69 ; Addr[20], ASel, Addr[9] ; RA[9] ;
; E ; LC80 ; Bank[0], FullIOEN, nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0] ; RA[0] ;
; F ; LC88 ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ;
; F ; LC86 ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ;
; F ; LC83 ; Addr[12], ASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0] ; RA[1] ;
; F ; LC94 ; D[7] ; RD[7] ;
; F ; LC82 ; C7M, nRES, S[2], nIOSEL, S[1], S[0] ; DOE~5, RAMSEL_MC, BankWR_MC, SetWR_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC ;
; F ; LC87 ; C7M, nRES, D[4], BankWR_MC, S[0], S[2], S[1] ; RA~88, RA~95, RA~102, RA~109 ;
; F ; LC89 ; C7M, nRES, D[2], BankWR_MC, S[0], S[2], S[1] ; RA~80, RA~81, RA~88, RA~95, RA~102, RA~109 ;
; F ; LC92 ; C7M, nRES, D[3], BankWR_MC, S[0], S[2], S[1] ; RA~81, RA~88, RA~95, RA~102, RA~109 ;
; F ; LC93 ; RASr, RASf ; nRAS ;
; F ; LC91 ; Addr[19], ASel, Addr[8] ; RA[8] ;
; F ; LC84 ; C7M, nRES, D[5], BankWR_MC, S[0], S[2], S[1] ; RA~95, RA~102, RA~109 ;
; F ; LC85 ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ;
; G ; LC109 ; D[1] ; RD[1] ;
; G ; LC107 ; D[2] ; RD[2] ;
; G ; LC108 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ;
; G ; LC110 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ;
; G ; LC100 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ;
; G ; LC111 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], S[2], S[1], nWE, Addr[22], RAMSEL_MC ; comb~34 ;
; G ; LC103 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], S[2], S[1], nWE, Addr[22], RAMSEL_MC ; comb~30 ;
; G ; LC105 ; D[3] ; RD[3] ;
; G ; LC106 ; C7M, nRES, D[7], AddrMWR_MC, Addr[15], S[1], S[2], S[0], IncAddrH, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], IncAddrH, Addr[23] ;
; G ; LC112 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], SetWR_MC, S[0], S[2], S[1] ; RA~74, RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ;
; G ; LC99 ; D[6] ; RD[6] ;
; G ; LC97 ; D[5] ; RD[5] ;
; G ; LC102 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[1], S[0], S[2], RAMSEL_MC, nWE ; comb~27 ;
; G ; LC101 ; D[4] ; RD[4] ;
; G ; LC104 ; S[2], nWE ; nRWE ;
; G ; LC98 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS1f, CAS0f ;
; H ; LC120 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ;
; H ; LC124 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], REGEN, lpm_counter:Ref_rtl_0|dffs[0], CASr, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, ASel, RASf, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], Addr[0], lpm_counter:Ref_rtl_0|dffs[3], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS1f, CAS0f, Bank[6], Addr[6], Addr[7], IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
; H ; LC114 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, S[0], S[1], S[2] ;
; H ; LC119 ; PHI1b7_MC ; PHI1b9_MC ;
; H ; LC128 ; PHI1b6_MC ; PHI1b8_MC ;
; H ; LC127 ; PHI1b5_MC ; PHI1b7_MC ;
; H ; LC123 ; PHI1b4_MC ; PHI1b6_MC ;
; H ; LC122 ; PHI1b3_MC ; PHI1b5_MC ;
; H ; LC126 ; C7M, nRES, S[2], nIOSEL, S[1], S[0], IOROMEN, A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[0], A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~25 ;
; H ; LC117 ; PHI1b2_MC ; PHI1b4_MC ;
; H ; LC125 ; PHI1b1_MC ; PHI1b3_MC ;
; H ; LC121 ; C7M, nRES, S[0], nWE, RAMSEL_MC, S[1], S[2] ; RA~63, RA~66, RA~69, RA~74, RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ;
; H ; LC115 ; D[0] ; RD[0] ;
; H ; LC116 ; PHI1in ; PHI1b1_MC ;
; H ; LC118 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, ASel~10, REGEN, lpm_counter:Ref_rtl_0|dffs[0], CASr, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, ASel, RASf, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], Addr[0], lpm_counter:Ref_rtl_0|dffs[3], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS1f, CAS0f, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
; H ; LC113 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[2], S[1] ; S[0], S[1], S[2], REGEN, lpm_counter:Ref_rtl_0|dffs[0], CASr, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, ASel, RASf, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], Addr[0], lpm_counter:Ref_rtl_0|dffs[3], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS1f, CAS0f, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[0], S[2], S[1], Addr[5], IncAddrL, Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[5]~108, Addr[5], Addr[6], Addr[7], IncAddrM, RA~95 ;
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[0], S[2], S[1], Addr[3], IncAddrL, Addr[2], Addr[1], Addr[0] ; Dout[3]~96, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~81 ;
; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[1], S[0], S[2], Addr[9], IncAddrM, Addr[8] ; Dout[1]~84, Addr[9], Addr[10], Addr[11], RA~66, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[0], S[2], S[1], Addr[2], IncAddrL, Addr[1], Addr[0] ; Dout[2]~90, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~80 ;
; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[0], S[1], Addr[8], IncAddrM ; Dout[0]~78, Addr[8], Addr[9], Addr[10], Addr[11], RA~63, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[0], S[2], S[1], Addr[1], IncAddrL, Addr[0] ; Dout[1]~84, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~121 ;
; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[0], S[2], S[1], Addr[0], IncAddrL ; Dout[0]~78, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~74 ;
; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[0], S[2], S[1], Addr[7], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[7]~120, Addr[7], IncAddrM, RA~109 ;
; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[0], S[2], S[1], Addr[6], IncAddrL, Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[6]~114, Addr[6], Addr[7], IncAddrM, RA~102 ;
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[0], S[2], S[1], Addr[4], IncAddrL, Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[4]~102, Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~88 ;
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[1], S[0], S[2], Addr[14], IncAddrM, Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13] ; Dout[6]~114, Addr[14], Addr[15], IncAddrH, RA~81 ;
; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[1], S[0], S[2], Addr[13], IncAddrM, Addr[8], Addr[9], Addr[10], Addr[11], Addr[12] ; Dout[5]~108, Addr[13], Addr[14], Addr[15], IncAddrH, RA~80 ;
; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[1], S[0], S[2], Addr[12], IncAddrM, Addr[8], Addr[9], Addr[10], Addr[11] ; Dout[4]~102, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~121 ;
; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[1], S[0], S[2], Addr[15], IncAddrM, Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14] ; Dout[7]~120, Addr[15], IncAddrH, RA~88 ;
; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[1], S[0], S[2], Addr[11], IncAddrM, Addr[8], Addr[9], Addr[10] ; Dout[3]~96, Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~74 ;
; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[1], S[0], S[2], Addr[10], IncAddrM, Addr[8], Addr[9] ; Dout[2]~90, Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], RA~69, Addr[15], IncAddrH ;
; B ; LC19 ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[0], S[1], Addr[22], IncAddrH, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[6]~114, Addr[22], CAS0f, CAS1f, comb~34, comb~38, Addr[23] ;
; B ; LC27 ; C7M, nRES, D[6], BankWR_MC, S[0], S[1], S[2] ; RA~102, RA~109 ;
; B ; LC20 ; C7M, nRES, D[7], AddrHWR_MC, S[2], S[0], S[1], Addr[23], IncAddrH, Addr[22], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[7]~120, Addr[23] ;
; B ; LC22 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], SetWR_MC, S[0], S[1], S[2] ; RA~74, RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ;
; B ; LC17 ; ; nINH ;
; B ; LC24 ; C7M, nRES, D[0], AddrHWR_MC, S[2], S[0], S[1], Addr[16], IncAddrH ; Dout[0]~78, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~95 ;
; B ; LC30 ; C7M, nRES, D[1], BankWR_MC, S[0], S[1], S[2] ; RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ;
; B ; LC21 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[0], S[1], Addr[17], IncAddrH, Addr[16] ; Dout[1]~84, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~102 ;
; B ; LC26 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[0], S[1], Addr[18], IncAddrH, Addr[17], Addr[16] ; Dout[2]~90, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~109 ;
; B ; LC18 ; C7M, nRES, D[2], BankWR_MC, S[0], S[1], S[2] ; RA~80, RA~81, RA~88, RA~95, RA~102, RA~109 ;
; B ; LC28 ; C7M, nRES, D[3], BankWR_MC, S[0], S[1], S[2] ; RA~81, RA~88, RA~95, RA~102, RA~109 ;
; B ; LC23 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[0], S[1], Addr[19], IncAddrH, Addr[18], Addr[17], Addr[16] ; Dout[3]~96, Addr[19], RA~63, Addr[20], Addr[21], Addr[22], Addr[23] ;
; B ; LC25 ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[0], S[1], Addr[20], IncAddrH, Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[4]~102, Addr[20], RA~66, Addr[21], Addr[22], Addr[23] ;
; B ; LC32 ; C7M, nRES, D[4], BankWR_MC, S[0], S[1], S[2] ; RA~88, RA~95, RA~102, RA~109 ;
; B ; LC31 ; C7M, nRES, D[5], BankWR_MC, S[0], S[1], S[2] ; RA~95, RA~102, RA~109 ;
; B ; LC29 ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[0], S[1], Addr[21], IncAddrH, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[5]~108, Addr[21], RA~69, Addr[22], Addr[23] ;
; C ; LC42 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; FullIOEN ;
; C ; LC37 ; C7M, nRES, nIOSEL, S[2], S[0], S[1] ; DOE~5, RAMSEL_MC, BankWR_MC, SetWR_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC ;
; C ; LC34 ; REGEN, nDEVSEL, A[0], A[1], A[2], A[3] ; IncAddrL, CASel, RASf, RASr, CAS0f, CAS1f, comb~34, comb~38 ;
; C ; LC33 ; nWE, REGEN, nDEVSEL, A[0], A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ;
; C ; LC39 ; A[0], A[1], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23] ;
; C ; LC38 ; RD[4], nDEVSEL, A[1], A[0], A[2], A[3], Addr[20], Addr[12], Addr[4] ; D[4] ;
; C ; LC40 ; RD[5], nDEVSEL, A[1], A[0], A[2], A[3], Addr[21], Addr[13], Addr[5] ; D[5] ;
; C ; LC43 ; RD[6], nDEVSEL, A[1], A[0], A[2], A[3], Addr[22], Addr[14], Addr[6] ; D[6] ;
; C ; LC45 ; RD[7], nDEVSEL, A[1], A[0], A[2], A[3], Addr[23], Addr[15], Addr[7] ; D[7] ;
; C ; LC36 ; C7M, nRES, S[2] ; DOE~5, RDOE~1 ;
; C ; LC44 ; C7M, nRES, nWE, S[2], S[0], S[1] ; comb~26 ;
; C ; LC47 ; A[0], A[1], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
; C ; LC48 ; C7M, S[0], S[2], nWE, S[1] ; comb~34, comb~38 ;
; C ; LC35 ; A[0], A[1], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ;
; C ; LC41 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1], IncAddrL ; IncAddrL, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM~9, IncAddrM ;
; C ; LC46 ; PHI1in, PHI1b8_MC ; PHI0seen, PHI1reg, S[1], S[0], S[2] ;
; D ; LC57 ; RD[0], nDEVSEL, A[1], A[0], A[2], A[3], Addr[16], Addr[8], Addr[0] ; D[0] ;
; D ; LC56 ; REGEN, nDEVSEL, DBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
; D ; LC59 ; RD[1], nDEVSEL, A[1], A[0], A[2], A[3], Addr[17], Addr[9], Addr[1] ; D[1] ;
; D ; LC61 ; RD[2], nDEVSEL, A[1], A[0], A[2], A[3], Addr[18], Addr[10], Addr[2] ; D[2] ;
; D ; LC64 ; RD[3], nDEVSEL, A[1], A[0], A[2], A[3], Addr[19], Addr[11], Addr[3] ; D[3] ;
; D ; LC52 ; C7M, PHI1b9_MC ; S[1], S[0], S[2] ;
; D ; LC49 ; CSEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ;
; D ; LC53 ; CASr, Addr[22], RAMSEL_MC, CAS0f ; nCAS0 ;
; D ; LC58 ; C7M, PHI1b9_MC ; S[1], S[0], S[2] ;
; D ; LC51 ; CASr, Addr[22], RAMSEL_MC, CAS1f ; nCAS1 ;
; E ; LC72 ; Addr[21], CASel, Addr[10] ; RA[10] ;
; E ; LC69 ; Addr[20], CASel, Addr[9] ; RA[9] ;
; E ; LC73 ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], CASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ;
; E ; LC77 ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], CASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ;
; E ; LC75 ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], CASel, nIOSEL, Addr[2] ; RA[2] ;
; E ; LC80 ; Bank[0], FullIOEN, nIOSTRB, Addr[11], CASel, nIOSEL, Addr[0] ; RA[0] ;
; E ; LC67 ; nWE ; nROE ;
; E ; LC79 ; C7M, nRES, D[7], AddrLWR_MC, Addr[7], S[2], S[1], S[0], IncAddrM, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrL, IncAddrM~9 ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrM, Addr[15], IncAddrH ;
; F ; LC94 ; D[7] ; RD[7] ;
; F ; LC91 ; Addr[19], CASel, Addr[8] ; RA[8] ;
; F ; LC96 ; C7M, nWE, S[0], RAMSEL_MC, S[2], S[1] ; comb~28, RA~63, RA~66, RA~69, RA~74, RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ;
; F ; LC93 ; RASr, RASf ; nRAS ;
; F ; LC86 ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], CASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ;
; F ; LC88 ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], CASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ;
; F ; LC85 ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], CASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ;
; F ; LC87 ; C7M, nRES, D[7], BankWR_MC, S[0], S[1], S[2] ; RA~109 ;
; F ; LC83 ; Addr[12], CASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0] ; RA[1] ;
; G ; LC107 ; D[2] ; RD[2] ;
; G ; LC101 ; D[4] ; RD[4] ;
; G ; LC97 ; D[5] ; RD[5] ;
; G ; LC99 ; D[6] ; RD[6] ;
; G ; LC103 ; C7M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[0], S[1] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS0f, CAS1f ;
; G ; LC110 ; C7M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[0], S[1] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS0f, CAS1f ;
; G ; LC112 ; C7M, nWE, S[0], RAMSEL_MC, S[2], S[1] ; comb~31 ;
; G ; LC98 ; C7M, nRES, D[7], AddrMWR_MC, Addr[15], S[0], S[2], S[1], IncAddrH, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], IncAddrH, Addr[23] ;
; G ; LC100 ; C7M, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[0], S[1] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS0f, CAS1f ;
; G ; LC106 ; C7M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], S[1], S[2], nWE, Addr[22], RAMSEL_MC ; comb~34 ;
; G ; LC111 ; C7M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], S[1], S[2], nWE, Addr[22], RAMSEL_MC ; comb~38 ;
; G ; LC104 ; CASel, nWE ; nRWE ;
; G ; LC105 ; D[3] ; RD[3] ;
; G ; LC108 ; C7M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[0], S[1] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS0f, CAS1f ;
; G ; LC109 ; D[1] ; RD[1] ;
; G ; LC102 ; C7M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[0], S[1], nWE, RAMSEL_MC ; comb~31 ;
; H ; LC123 ; PHI1b5_MC ; PHI1b7_MC ;
; H ; LC118 ; C7M, PHI0seen, PHI1reg, PHI1b9_MC, S[1], S[0], S[2] ; S[1], S[0], S[2], CSEN, lpm_counter:Ref_rtl_0|dffs[0], REGEN, CASr, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, CASel, RASf, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS0f, CAS1f, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
; H ; LC113 ; C7M, PHI0seen, PHI1reg, PHI1b9_MC, S[0], S[2], S[1] ; S[1], S[0], S[2], DBEN, CSEN, lpm_counter:Ref_rtl_0|dffs[0], REGEN, CASr, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, CASel, RASf, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS0f, CAS1f, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
; H ; LC114 ; C7M, PHI0seen, PHI1reg, PHI1b9_MC, S[0], S[2], S[1] ; S[1], S[0], S[2], CSEN, lpm_counter:Ref_rtl_0|dffs[0], REGEN, CASr, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, CASel, RASf, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS0f, CAS1f, Bank[6], Addr[6], Addr[7], IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
; H ; LC122 ; PHI1b6_MC ; PHI1b8_MC ;
; H ; LC125 ; C7M, nRES, D[0], BankWR_MC, S[0], S[1], S[2] ; RA~74, RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ;
; H ; LC124 ; PHI1b4_MC ; PHI1b6_MC ;
; H ; LC127 ; PHI1b3_MC ; PHI1b5_MC ;
; H ; LC128 ; PHI1b2_MC ; PHI1b4_MC ;
; H ; LC120 ; DBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ;
; H ; LC116 ; PHI1b1_MC ; PHI1b3_MC ;
; H ; LC126 ; PHI1b0_MC ; PHI1b2_MC ;
; H ; LC115 ; D[0] ; RD[0] ;
; H ; LC121 ; PHI1in ; PHI1b1_MC ;
; H ; LC119 ; PHI1b7_MC ; PHI1b9_MC ;
; H ; LC117 ; C7M, nRES, A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[0], A[1], A[2], A[3], S[2], S[0], S[1], IOROMEN, nIOSEL ; DOE~5, IOROMEN, comb~26 ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------+
@ -724,8 +726,8 @@ Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM"
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4708 megabytes
Info: Processing ended: Sun Oct 20 22:22:01 2019
Info: Processing ended: Sun Feb 16 00:10:46 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00
Info: Total CPU time (on all processors): 00:00:01

4
cpld/output_files/GR8RAM.fit.summary
View File

@ -1,9 +1,9 @@
Fitter Status : Successful - Sun Oct 20 22:22:01 2019
Fitter Status : Successful - Sun Feb 16 00:10:46 2020
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM
Family : MAX7000S
Device : EPM7128SLC84-15
Timing Models : Final
Total macrocells : 106 / 128 ( 83 % )
Total macrocells : 107 / 128 ( 84 % )
Total pins : 65 / 68 ( 96 % )

14
cpld/output_files/GR8RAM.flow.rpt
View File

@ -1,5 +1,5 @@
Flow report for GR8RAM
Sun Oct 20 22:22:04 2019
Sun Feb 16 00:10:48 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -40,14 +40,14 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------+-------------------------------------------------+
; Flow Status ; Successful - Sun Oct 20 22:22:02 2019 ;
; Flow Status ; Successful - Sun Feb 16 00:10:47 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX7000S ;
; Device ; EPM7128SLC84-15 ;
; Timing Models ; Final ;
; Total macrocells ; 106 / 128 ( 83 % ) ;
; Total macrocells ; 107 / 128 ( 84 % ) ;
; Total pins ; 65 / 68 ( 96 % ) ;
+---------------------------+-------------------------------------------------+
@ -57,7 +57,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 10/20/2019 22:21:59 ;
; Start date & time ; 02/16/2020 00:10:44 ;
; Main task ; Compilation ;
; Revision Name ; GR8RAM ;
+-------------------+---------------------+
@ -72,7 +72,7 @@ applicable agreement for further details.
; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ;
; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ;
; AUTO_TURBO_BIT ; Off ; On ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 207120313862967.157162451910916 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 207120313862967.158182984416660 ; -- ; -- ; -- ;
; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ;
; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ;
; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ;
@ -101,8 +101,8 @@ applicable agreement for further details.
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4587 MB ; 00:00:01 ;
; Fitter ; 00:00:01 ; 1.0 ; 4708 MB ; 00:00:00 ;
; Assembler ; 00:00:00 ; 1.0 ; 4522 MB ; 00:00:00 ;
; TimeQuest Timing Analyzer ; 00:00:00 ; 1.0 ; 4541 MB ; 00:00:01 ;
; Total ; 00:00:02 ; -- ; -- ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:00 ; 1.0 ; 4530 MB ; 00:00:00 ;
; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+

2
cpld/output_files/GR8RAM.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="4badf67548bfa7a0e186"/>
<hash md5_digest_80b="82bc2f8550dba50c20ab"/>
</project>
<file_info>
<file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>

38
cpld/output_files/GR8RAM.map.rpt
View File

@ -1,5 +1,5 @@
Analysis & Synthesis report for GR8RAM
Sun Oct 20 22:22:00 2019
Sun Feb 16 00:10:45 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -45,12 +45,12 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Oct 20 22:22:00 2019 ;
; Analysis & Synthesis Status ; Successful - Sun Feb 16 00:10:45 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX7000S ;
; Total macrocells ; 106 ;
; Total macrocells ; 107 ;
; Total pins ; 61 ;
+-----------------------------+-------------------------------------------------+
@ -165,14 +165,14 @@ Parallel compilation was disabled, but you have multiple processors available. E
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 106 ;
; Total registers ; 54 ;
; Logic cells ; 107 ;
; Total registers ; 55 ;
; I/O pins ; 61 ;
; Shareable expanders ; 1 ;
; Maximum fan-out node ; S[2] ;
; Maximum fan-out ; 54 ;
; Total fan-out ; 864 ;
; Average fan-out ; 5.14 ;
; Maximum fan-out node ; C7M ;
; Maximum fan-out ; 55 ;
; Total fan-out ; 855 ;
; Average fan-out ; 5.06 ;
+----------------------+----------------------+
@ -181,7 +181,7 @@ Parallel compilation was disabled, but you have multiple processors available. E
+----------------------------+------------+------+-------------------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+-------------------------------+--------------+
; |GR8RAM ; 106 ; 61 ; |GR8RAM ; work ;
; |GR8RAM ; 107 ; 61 ; |GR8RAM ; work ;
; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ;
+----------------------------+------------+------+-------------------------------+--------------+
@ -331,18 +331,18 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun Oct 20 22:21:59 2019
Info: Processing started: Sun Feb 16 00:10:44 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
Info (12023): Found entity 1: GR8RAM
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(122): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(127): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(170): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(115): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(120): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(169): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(180): truncated value with size 32 to match size of target (8)
Info (19000): Inferred 1 megafunctions from design logic
Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0"
Info (278001): Inferred 4 megafunctions from design logic
@ -382,16 +382,16 @@ Warning (21074): Design contains 9 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "A[13]"
Warning (15610): No output dependent on input pin "A[14]"
Warning (15610): No output dependent on input pin "A[15]"
Info (21057): Implemented 168 device resources after synthesis - the final resource count might be different
Info (21057): Implemented 169 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 27 input pins
Info (21059): Implemented 18 output pins
Info (21060): Implemented 16 bidirectional pins
Info (21063): Implemented 106 macrocells
Info (21063): Implemented 107 macrocells
Info (21073): Implemented 1 shareable expanders
Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 17 warnings
Info: Peak virtual memory: 4587 megabytes
Info: Processing ended: Sun Oct 20 22:22:00 2019
Info: Processing ended: Sun Feb 16 00:10:45 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

2
cpld/output_files/GR8RAM.map.smsg
View File

@ -1,3 +1,3 @@
Warning (10273): Verilog HDL warning at GR8RAM.v(52): extended using "x" or "z"
Warning (10273): Verilog HDL warning at GR8RAM.v(60): extended using "x" or "z"
Warning (10268): Verilog HDL information at GR8RAM.v(190): always construct contains both blocking and non-blocking assignments
Warning (10268): Verilog HDL information at GR8RAM.v(200): always construct contains both blocking and non-blocking assignments

4
cpld/output_files/GR8RAM.map.summary
View File

@ -1,7 +1,7 @@
Analysis & Synthesis Status : Successful - Sun Oct 20 22:22:00 2019
Analysis & Synthesis Status : Successful - Sun Feb 16 00:10:45 2020
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM
Family : MAX7000S
Total macrocells : 106
Total macrocells : 107
Total pins : 61

BIN
cpld/output_files/GR8RAM.pof
View File

Binary file not shown.

124
cpld/output_files/GR8RAM.sta.rpt
View File

@ -1,5 +1,5 @@
TimeQuest Timing Analyzer report for GR8RAM
Sun Oct 20 22:22:04 2019
Sun Feb 16 00:10:48 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -105,7 +105,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+---------+---------------+
; C7M ; -47.500 ; -2091.500 ;
; C7M ; -47.500 ; -2116.500 ;
+-------+---------+---------------+
@ -135,7 +135,7 @@ No paths to report.
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; C7M ; -4.500 ; -486.000 ;
; C7M ; -4.500 ; -495.000 ;
+-------+--------+---------------+
@ -146,6 +146,7 @@ No paths to report.
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
; -47.500 ; REGEN ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -47.500 ; REGEN ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -47.500 ; REGEN ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -47.500 ; REGEN ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -47.500 ; REGEN ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -47.500 ; REGEN ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
@ -167,7 +168,6 @@ No paths to report.
; -47.500 ; REGEN ; Addr[7] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -47.500 ; REGEN ; Addr[23] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -47.500 ; REGEN ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -47.500 ; REGEN ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -47.500 ; REGEN ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -47.500 ; REGEN ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -47.500 ; REGEN ; Bank[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
@ -180,13 +180,13 @@ No paths to report.
; -47.500 ; REGEN ; Bank[7] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -47.500 ; REGEN ; FullIOEN ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
; -46.500 ; S[2] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ;
; -46.500 ; S[0] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ;
; -46.500 ; S[1] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ;
; -46.000 ; IncAddrL ; IncAddrM ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ;
; -34.500 ; REGEN ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ;
; -34.500 ; REGEN ; RASf ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ;
; -34.500 ; REGEN ; CAS1f ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ;
; -34.500 ; REGEN ; CAS0f ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ;
; -34.000 ; REGEN ; ASel ; C7M ; C7M ; 1.000 ; 0.000 ; 31.000 ;
; -34.500 ; REGEN ; CAS1f ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ;
; -34.000 ; REGEN ; CASel ; C7M ; C7M ; 1.000 ; 0.000 ; 31.000 ;
; -34.000 ; REGEN ; RASr ; C7M ; C7M ; 1.000 ; 0.000 ; 31.000 ;
; -25.500 ; S[0] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
@ -197,53 +197,53 @@ No paths to report.
; -25.500 ; S[0] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[1] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[2] ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
; -25.500 ; S[0] ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
@ -252,24 +252,24 @@ No paths to report.
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
; 5.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI0seen ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI1reg ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[2] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[2] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI1reg ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI0seen ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[2] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI1reg ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI0seen ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[2] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI1reg ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[2] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[2] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
@ -300,58 +300,58 @@ No paths to report.
; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[16] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 18.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; CSDBEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; DBEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; CSEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; CSEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; CSEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; CASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; CASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; CASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; IncAddrL ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; IncAddrL ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[0] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; IncAddrM ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; IncAddrM ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[8] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; IncAddrH ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[16] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; IncAddrH ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[17] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[16] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; IncAddrM ; Addr[10] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; IncAddrM ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[7] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[6] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[5] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[4] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[3] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
@ -360,8 +360,6 @@ No paths to report.
+--------+--------------+----------------+------------------+-------+------------+----------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+------------------+-------+------------+----------+
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; ASel ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; ASel ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[0] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[0] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[10] ;
@ -430,10 +428,14 @@ No paths to report.
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; CAS0f ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; CAS1f ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; CAS1f ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CASel ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CASel ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CASr ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CASr ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CSDBEN ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CSDBEN ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CSEN ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CSEN ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; DBEN ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; DBEN ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; FullIOEN ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; FullIOEN ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IOROMEN ;
@ -458,8 +460,6 @@ No paths to report.
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; S[0] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; S[1] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; S[1] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; S[2] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; S[2] ;
+--------+--------------+----------------+------------------+-------+------------+----------+
@ -1004,7 +1004,7 @@ No paths to report.
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C7M ; C7M ; 93 ; 0 ; 370 ; 215 ;
; C7M ; C7M ; 99 ; 0 ; 371 ; 224 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -1014,7 +1014,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C7M ; C7M ; 93 ; 0 ; 370 ; 215 ;
; C7M ; C7M ; 99 ; 0 ; 371 ; 224 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -1039,7 +1039,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 33 ; 33 ;
; Unconstrained Input Port Paths ; 479 ; 479 ;
; Unconstrained Input Port Paths ; 466 ; 466 ;
; Unconstrained Output Ports ; 33 ; 33 ;
; Unconstrained Output Port Paths ; 264 ; 264 ;
+---------------------------------+-------+------+
@ -1051,7 +1051,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun Oct 20 22:22:03 2019
Info: Processing started: Sun Feb 16 00:10:48 2020
Info: Command: quartus_sta GR8RAM -c GR8RAM
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
@ -1067,7 +1067,7 @@ Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -47.500
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -47.500 -2091.500 C7M
Info (332119): -47.500 -2116.500 C7M
Info (332146): Worst-case hold slack is 5.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
@ -1077,14 +1077,14 @@ Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -4.500
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -4.500 -486.000 C7M
Info (332119): -4.500 -495.000 C7M
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 4541 megabytes
Info: Processing ended: Sun Oct 20 22:22:04 2019
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info: Peak virtual memory: 4530 megabytes
Info: Processing ended: Sun Feb 16 00:10:48 2020
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

4
cpld/output_files/GR8RAM.sta.summary
View File

@ -4,7 +4,7 @@ TimeQuest Timing Analyzer Summary
Type : Setup 'C7M'
Slack : -47.500
TNS : -2091.500
TNS : -2116.500
Type : Hold 'C7M'
Slack : 5.000
@ -12,6 +12,6 @@ TNS : 0.000
Type : Minimum Pulse Width 'C7M'
Slack : -4.500
TNS : -486.000
TNS : -495.000
------------------------------------------------------------