mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-12-11 16:49:17 +00:00
Recompile
This commit is contained in:
Zane Kaminski
parent
7eb62dbe5a
commit
97943bc2e7
@ -1,6 +1,6 @@
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Assembler report for GR8RAM
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Tue Feb 28 11:21:26 2023
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||||
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
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||||
Fri Feb 16 20:46:17 2024
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||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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||||
|
||||
|
||||
---------------------
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||||
@ -10,7 +10,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
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2. Assembler Summary
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3. Assembler Settings
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4. Assembler Generated Files
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5. Assembler Device Options: /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof
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5. Assembler Device Options: /Repos/GR8RAM/cpld/output_files/GR8RAM.pof
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6. Assembler Messages
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@ -18,7 +18,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
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||||
----------------
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; Legal Notice ;
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||||
----------------
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||||
Copyright (C) 2022 Intel Corporation. All rights reserved.
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||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
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+---------------------------------------------------------------+
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; Assembler Summary ;
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+-----------------------+---------------------------------------+
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; Assembler Status ; Successful - Tue Feb 28 11:21:26 2023 ;
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; Assembler Status ; Successful - Fri Feb 16 20:46:17 2024 ;
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; Revision Name ; GR8RAM ;
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; Top-level Entity Name ; GR8RAM ;
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; Family ; MAX II ;
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@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
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+--------+---------+---------------+
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+----------------------------------------------+
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; Assembler Generated Files ;
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+----------------------------------------------+
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; File Name ;
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+----------------------------------------------+
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; /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof ;
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+----------------------------------------------+
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+--------------------------------------------+
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; Assembler Generated Files ;
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+--------------------------------------------+
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; File Name ;
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+--------------------------------------------+
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; /Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
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+--------------------------------------------+
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+------------------------------------------------------------------------+
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; Assembler Device Options: /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof ;
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+----------------+-------------------------------------------------------+
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; Option ; Setting ;
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+----------------+-------------------------------------------------------+
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; JTAG usercode ; 0x00163AA4 ;
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; Checksum ; 0x00163E9C ;
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+----------------+-------------------------------------------------------+
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+----------------------------------------------------------------------+
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; Assembler Device Options: /Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
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+----------------+-----------------------------------------------------+
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; Option ; Setting ;
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+----------------+-----------------------------------------------------+
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; JTAG usercode ; 0x00163AA4 ;
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; Checksum ; 0x00163E9C ;
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+----------------+-----------------------------------------------------+
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+--------------------+
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@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
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+--------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime Assembler
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Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
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Info: Processing started: Tue Feb 28 11:21:25 2023
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Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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Info: Processing started: Fri Feb 16 20:46:16 2024
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Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (115031): Writing out detailed assembly data for power analysis
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Info (115030): Assembler is generating device programming files
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Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 13100 megabytes
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Info: Processing ended: Tue Feb 28 11:21:26 2023
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Info: Peak virtual memory: 13096 megabytes
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Info: Processing ended: Fri Feb 16 20:46:17 2024
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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@ -1 +1 @@
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Tue Feb 28 11:21:32 2023
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Fri Feb 16 20:46:20 2024
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@ -1,6 +1,6 @@
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Fitter report for GR8RAM
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Tue Feb 28 11:21:23 2023
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Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
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Fri Feb 16 20:46:15 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
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||||
@ -38,7 +38,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 2022 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
@ -55,21 +55,21 @@ https://fpgasoftware.intel.com/eula.
|
||||
|
||||
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+------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
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||||
+-----------------------+------------------------------------------------+
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||||
; Fitter Status ; Successful - Tue Feb 28 11:21:23 2023 ;
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; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
|
||||
; Revision Name ; GR8RAM ;
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; Top-level Entity Name ; GR8RAM ;
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; Family ; MAX II ;
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; Device ; EPM240T100C5 ;
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; Timing Models ; Final ;
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; Total logic elements ; 233 / 240 ( 97 % ) ;
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; Total pins ; 80 / 80 ( 100 % ) ;
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; Total virtual pins ; 0 ;
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; UFM blocks ; 0 / 1 ( 0 % ) ;
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+-----------------------+------------------------------------------------+
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+---------------------------------------------------------------------+
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; Fitter Summary ;
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||||
+-----------------------+---------------------------------------------+
|
||||
; Fitter Status ; Successful - Fri Feb 16 20:46:15 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; GR8RAM ;
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||||
; Top-level Entity Name ; GR8RAM ;
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; Family ; MAX II ;
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; Device ; EPM240T100C5 ;
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; Timing Models ; Final ;
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; Total logic elements ; 233 / 240 ( 97 % ) ;
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; Total pins ; 80 / 80 ( 100 % ) ;
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; Total virtual pins ; 0 ;
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; UFM blocks ; 0 / 1 ( 0 % ) ;
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+-----------------------+---------------------------------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------+
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@ -134,15 +134,15 @@ https://fpgasoftware.intel.com/eula.
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 0.7% ;
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; Processors 3-4 ; 0.5% ;
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; Processor 2 ; 1.0% ;
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; Processors 3-4 ; 0.7% ;
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+----------------------------+-------------+
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+--------------+
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; Pin-Out File ;
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+--------------+
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The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin.
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The pin-out file can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
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+---------------------------------------------------------------------+
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@ -741,13 +741,13 @@ Info (332111): Found 2 clocks
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Info (332111): 40.000 C25M
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Info (332111): 978.000 PHI0
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Info (186079): Completed User Assigned Global Signals Promotion Operation
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Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9
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Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9
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Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
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Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
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Info (186217): Destination "comb~0" may be non-global or may not use global clock
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Info (186217): Destination "PHI0r1" may be non-global or may not use global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 10
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Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9
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Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 16
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Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 94
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Info (186217): Destination "PHI0r1" may be non-global or may not use global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 10
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Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
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Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 16
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Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 94
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Info (186079): Completed Auto Global Promotion Operation
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Info (176234): Starting register packing
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Info (186468): Started processing fast register assignments
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@ -760,13 +760,13 @@ Info (176215): I/O bank details before I/O pin placement
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Info (176214): Statistics of I/O banks
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Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available
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Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available
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||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
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||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
|
||||
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
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||||
Info (170189): Fitter placement preparation operations beginning
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||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
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||||
Info (170191): Fitter placement operations beginning
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||||
Info (170137): Fitter placement was successful
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||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
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||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
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||||
Info (170193): Fitter routing operations beginning
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||||
Info (170195): Router estimated average interconnect usage is 30% of the available device resources
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||||
Info (170196): Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
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||||
@ -774,20 +774,20 @@ Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were
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Info (170201): Optimizations that may affect the design's routability were skipped
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||||
Info (170200): Optimizations that may affect the design's timing were skipped
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||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
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||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds.
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.16 seconds.
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||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
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||||
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
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||||
Info (144001): Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg
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||||
Info (144001): Generated suppressed messages file /Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings
|
||||
Info: Peak virtual memory: 13746 megabytes
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||||
Info: Processing ended: Tue Feb 28 11:21:23 2023
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info: Total CPU time (on all processors): 00:00:05
|
||||
Info: Peak virtual memory: 13772 megabytes
|
||||
Info: Processing ended: Fri Feb 16 20:46:15 2024
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||||
Info: Elapsed time: 00:00:03
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||||
Info: Total CPU time (on all processors): 00:00:03
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||||
|
||||
|
||||
+----------------------------+
|
||||
; Fitter Suppressed Messages ;
|
||||
+----------------------------+
|
||||
The suppressed messages can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg.
|
||||
The suppressed messages can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg.
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||||
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|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Fitter Status : Successful - Tue Feb 28 11:21:23 2023
|
||||
Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||
Fitter Status : Successful - Fri Feb 16 20:46:15 2024
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : GR8RAM
|
||||
Top-level Entity Name : GR8RAM
|
||||
Family : MAX II
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|
||||
@ -1,6 +1,6 @@
|
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Flow report for GR8RAM
|
||||
Tue Feb 28 11:21:31 2023
|
||||
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||
Fri Feb 16 20:46:19 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -21,7 +21,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 2022 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+------------------------------------------------+
|
||||
; Flow Status ; Successful - Tue Feb 28 11:21:31 2023 ;
|
||||
; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 233 / 240 ( 97 % ) ;
|
||||
; Total pins ; 80 / 80 ( 100 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||
+-----------------------+------------------------------------------------+
|
||||
+---------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Fri Feb 16 20:46:17 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 233 / 240 ( 97 % ) ;
|
||||
; Total pins ; 80 / 80 ( 100 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
@ -60,33 +60,25 @@ https://fpgasoftware.intel.com/eula.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 02/28/2023 11:20:54 ;
|
||||
; Start date & time ; 02/16/2024 20:45:52 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
+-------------------+---------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Non-Default Global Settings ;
|
||||
+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.167760125411500 ; -- ; -- ; -- ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
|
||||
; EDA_NETLIST_WRITER_OUTPUT_DIR ; simulation/questa ; -- ; -- ; eda_simulation ;
|
||||
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
|
||||
; EDA_SIMULATION_TOOL ; Questa Intel FPGA (Verilog) ; <None> ; -- ; -- ;
|
||||
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
|
||||
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ;
|
||||
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 2 ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
|
||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||
+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
+---------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Non-Default Global Settings ;
|
||||
+---------------------------------------+----------------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+---------------------------------------+----------------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121380219419.170813435209448 ; -- ; -- ; -- ;
|
||||
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ;
|
||||
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 2 ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
|
||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||
+---------------------------------------+----------------------------------------+---------------+-------------+------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------+
|
||||
@ -94,12 +86,11 @@ https://fpgasoftware.intel.com/eula.
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:23 ; 1.0 ; 13114 MB ; 00:00:48 ;
|
||||
; Fitter ; 00:00:06 ; 1.0 ; 13746 MB ; 00:00:05 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13099 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13081 MB ; 00:00:01 ;
|
||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 13024 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:33 ; -- ; -- ; 00:00:56 ;
|
||||
; Analysis & Synthesis ; 00:00:19 ; 1.0 ; 13145 MB ; 00:00:41 ;
|
||||
; Fitter ; 00:00:03 ; 1.0 ; 13772 MB ; 00:00:03 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13092 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:01 ; 1.0 ; 13094 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:24 ; -- ; -- ; 00:00:46 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
@ -112,7 +103,6 @@ https://fpgasoftware.intel.com/eula.
|
||||
; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
|
||||
; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
|
||||
; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
|
||||
; EDA Netlist Writer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
|
||||
+----------------------+------------------+------------+------------+----------------+
|
||||
|
||||
|
||||
@ -123,7 +113,6 @@ quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
||||
quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||
quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||
quartus_sta GR8RAM -c GR8RAM
|
||||
quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||
|
||||
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="e669c88e609b9ce1c5b6"/>
|
||||
<hash md5_digest_80b="1794c049bdbd51a27b8f"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Analysis & Synthesis report for GR8RAM
|
||||
Tue Feb 28 11:21:16 2023
|
||||
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||
Fri Feb 16 20:46:11 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -26,7 +26,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 2022 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Tue Feb 28 11:21:16 2023 ;
|
||||
; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 253 ;
|
||||
; Total pins ; 80 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||
+-----------------------------+------------------------------------------------+
|
||||
+---------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Fri Feb 16 20:46:11 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 253 ;
|
||||
; Total pins ; 80 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
@ -145,13 +145,13 @@ https://fpgasoftware.intel.com/eula.
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+
|
||||
; gr8ram.v ; yes ; Auto-Found Verilog HDL File ; //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v ; ;
|
||||
+----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+
|
||||
+-------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------+---------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+------------------------+---------------------------------------+---------+
|
||||
; GR8RAM.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v ; ;
|
||||
+----------------------------------+-----------------+------------------------+---------------------------------------+---------+
|
||||
|
||||
|
||||
+-----------------------------------------------------+
|
||||
@ -279,44 +279,44 @@ Encoding Type: One-Hot
|
||||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||
Info: Processing started: Tue Feb 28 11:20:53 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Fri Feb 16 20:45:52 2024
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||
Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
|
||||
Info (12023): Found entity 1: GR8RAM File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 1
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
||||
Info (12023): Found entity 1: GR8RAM File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 1
|
||||
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
||||
Warning (10230): Verilog HDL assignment warning at gr8ram.v(42): truncated value with size 32 to match size of target (4) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 42
|
||||
Warning (10230): Verilog HDL assignment warning at gr8ram.v(47): truncated value with size 32 to match size of target (14) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 47
|
||||
Warning (10230): Verilog HDL assignment warning at gr8ram.v(134): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 134
|
||||
Warning (10230): Verilog HDL assignment warning at gr8ram.v(142): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 142
|
||||
Warning (10230): Verilog HDL assignment warning at gr8ram.v(149): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 149
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 42
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 47
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 134
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 142
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 149
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "nNMIout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 563
|
||||
Warning (13410): Pin "nIRQout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 566
|
||||
Warning (13410): Pin "nRDYout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 565
|
||||
Warning (13410): Pin "nINHout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 564
|
||||
Warning (13410): Pin "RWout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 567
|
||||
Warning (13410): Pin "nDMAout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 562
|
||||
Warning (13410): Pin "RAdir" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 561
|
||||
Warning (13410): Pin "nNMIout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 563
|
||||
Warning (13410): Pin "nIRQout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 566
|
||||
Warning (13410): Pin "nRDYout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 565
|
||||
Warning (13410): Pin "nINHout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 564
|
||||
Warning (13410): Pin "RWout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 567
|
||||
Warning (13410): Pin "nDMAout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 562
|
||||
Warning (13410): Pin "RAdir" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 561
|
||||
Info (17049): 3 registers lost all their fanouts during netlist optimizations.
|
||||
Info (21057): Implemented 333 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 28 input pins
|
||||
Info (21059): Implemented 35 output pins
|
||||
Info (21060): Implemented 17 bidirectional pins
|
||||
Info (21061): Implemented 253 logic cells
|
||||
Info (144001): Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
|
||||
Info: Peak virtual memory: 13114 megabytes
|
||||
Info: Processing ended: Tue Feb 28 11:21:16 2023
|
||||
Info: Elapsed time: 00:00:23
|
||||
Info: Total CPU time (on all processors): 00:00:48
|
||||
Info (144001): Generated suppressed messages file /Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings
|
||||
Info: Peak virtual memory: 13145 megabytes
|
||||
Info: Processing ended: Fri Feb 16 20:46:11 2024
|
||||
Info: Elapsed time: 00:00:19
|
||||
Info: Total CPU time (on all processors): 00:00:41
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Analysis & Synthesis Suppressed Messages ;
|
||||
+------------------------------------------+
|
||||
The suppressed messages can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg.
|
||||
The suppressed messages can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
||||
|
||||
|
||||
|
||||
@ -1,2 +1,2 @@
|
||||
Warning (10273): Verilog HDL warning at gr8ram.v(110): extended using "x" or "z" File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 110
|
||||
Warning (10273): Verilog HDL warning at gr8ram.v(286): extended using "x" or "z" File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 286
|
||||
Warning (10273): Verilog HDL warning at GR8RAM.v(110): extended using "x" or "z" File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 110
|
||||
Warning (10273): Verilog HDL warning at GR8RAM.v(286): extended using "x" or "z" File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 286
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Analysis & Synthesis Status : Successful - Tue Feb 28 11:21:16 2023
|
||||
Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||
Analysis & Synthesis Status : Successful - Fri Feb 16 20:46:11 2024
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : GR8RAM
|
||||
Top-level Entity Name : GR8RAM
|
||||
Family : MAX II
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
|
||||
-- Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and any partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
@ -58,7 +58,7 @@
|
||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
|
||||
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
Timing Analyzer report for GR8RAM
|
||||
Tue Feb 28 11:21:29 2023
|
||||
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||
Fri Feb 16 20:46:19 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -40,7 +40,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 2022 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+-----------------------+--------------------------------------------------------+
|
||||
; Quartus Prime Version ; Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
|
||||
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Device Family ; MAX II ;
|
||||
; Device Name ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Slow Model ;
|
||||
; Rise/Fall Delays ; Unavailable ;
|
||||
+-----------------------+--------------------------------------------------------+
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+-----------------------+-----------------------------------------------------+
|
||||
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Device Family ; MAX II ;
|
||||
; Device Name ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Slow Model ;
|
||||
; Rise/Fall Delays ; Unavailable ;
|
||||
+-----------------------+-----------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
@ -80,10 +80,11 @@ https://fpgasoftware.intel.com/eula.
|
||||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.00 ;
|
||||
; Maximum used ; 1 ;
|
||||
; Maximum used ; 2 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 0.2% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
@ -92,7 +93,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------+--------+--------------------------+
|
||||
; SDC File Path ; Status ; Read at ;
|
||||
+---------------+--------+--------------------------+
|
||||
; GR8RAM.sdc ; OK ; Tue Feb 28 11:21:29 2023 ;
|
||||
; GR8RAM.sdc ; OK ; Fri Feb 16 20:46:19 2024 ;
|
||||
+---------------+--------+--------------------------+
|
||||
|
||||
|
||||
@ -745,8 +746,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
+--------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||
Info: Processing started: Tue Feb 28 11:21:27 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Fri Feb 16 20:46:18 2024
|
||||
Info: Command: quartus_sta GR8RAM -c GR8RAM
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
@ -783,9 +784,9 @@ Info (332001): The selected device family is not supported by the report_metasta
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 13081 megabytes
|
||||
Info: Processing ended: Tue Feb 28 11:21:29 2023
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Peak virtual memory: 13094 megabytes
|
||||
Info: Processing ended: Fri Feb 16 20:46:19 2024
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user