mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-06-27 00:29:30 +00:00
Slim down a lot
This commit is contained in:
Zane Kaminski
parent
3b99146a5b
commit
9a1aa44d03
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@ -69,7 +69,7 @@ set_global_assignment -name MUX_RESTRUCTURE ON
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set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS"
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set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS"
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set_global_assignment -name SYNTHESIS_SEED 123
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set_global_assignment -name SYNTHESIS_SEED 123
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set_global_assignment -name SEED 235
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set_global_assignment -name SEED 235
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set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA"
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set_global_assignment -name AUTO_PACKED_REGISTERS_MAX "MINIMIZE AREA"
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set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF
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set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF
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set_global_assignment -name VERILOG_FILE GR8RAM.v
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set_global_assignment -name VERILOG_FILE GR8RAM.v
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set_location_assignment PIN_1 -to RA[4]
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set_location_assignment PIN_1 -to RA[4]
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142
cpld/GR8RAM.v
142
cpld/GR8RAM.v
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@ -10,32 +10,21 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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reg PHI0r1, PHI0r2;
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reg PHI0r1, PHI0r2;
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always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
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always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
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/* Reset filter */
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/* Reset synchronization */
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input nRES;
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input nRES; reg nRESr = 0;
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reg [3:0] nRESf = 0;
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reg nRESr = 0;
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always @(posedge C25M) begin
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always @(posedge C25M) begin
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nRESf[3:0] <= { nRESf[2:0], nRES };
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if (PS==15) nRESr <= nRES;
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nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0];
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end
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end
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/* Firmware select */
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/* Firmware select */
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input [1:0] SetFW;
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input [1:0] SetFW;
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reg [1:0] SetFWr;
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wire [1:0] SetROM = ~SetFW[1:0];
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reg SetFWLoaded = 0;
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wire SetEN16MB = 0;//SetROM[1:0]==2'b11;
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always @(posedge C25M) begin
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if (~SetFWLoaded) begin
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SetFWLoaded <= 1;
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SetFWr[1:0] <= SetFW[1:0];
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end
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end
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wire [1:0] SetROM = ~SetFWr[1:0];
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wire SetEN16MB = SetROM[1:0]==2'b11;
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wire SetEN24bit = SetROM[1];
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wire SetEN24bit = SetROM[1];
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/* State counter from PHI0 rising edge */
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/* State counter from PHI0 rising edge */
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reg [3:0] PS = 0;
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reg [3:0] PS = 0;
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wire PSStart = PS==0 && PHI0r1 && ~PHI0r2;
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wire PSStart = PS==0 && PHI0r1 && !PHI0r2;
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always @(posedge C25M) begin
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always @(posedge C25M) begin
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if (PSStart) PS <= 1;
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if (PSStart) PS <= 1;
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else if (PS==0) PS <= 0;
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else if (PS==0) PS <= 0;
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@ -64,53 +53,39 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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input nIOSEL, nDEVSEL, nIOSTRB;
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input nIOSEL, nDEVSEL, nIOSTRB;
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/* Apple address bus */
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/* Apple address bus */
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input [15:0] RA; input nWE;
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input [15:0] RA; reg CXXXr;
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reg [11:0] RAr; reg nWEr;
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input nWE;
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reg CXXXr;
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always @(posedge PHI0) CXXXr <= RA[15:12]==4'hC;
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always @(posedge PHI0) begin
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CXXXr <= RA[15:12]==4'hC;
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RAr[11:0] <= RA[11:0];
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nWEr <= nWE;
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end
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/* Apple select signals */
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/* Apple select signals */
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wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11]));
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wire RAMExists = (~SetEN24bit || SetEN16MB || ~Addr[23]);
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wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
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wire BankSEL = REGEN && !nDEVSEL && RA[3:0]==4'hF;
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wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
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wire RAMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h3;
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wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
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wire AddrHSEL = REGEN && !nDEVSEL && RA[3:0]==4'h2;
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wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]);
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wire AddrMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h1;
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wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
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wire AddrLSEL = REGEN && !nDEVSEL && RA[3:0]==4'h0;
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wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
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wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
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wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL;
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wire RAMRegSEL = ~nDEVSEL && RAMRegSpecSEL;
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wire RAMSEL = ~nDEVSEL && RAMSpecSEL;
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wire RAMWR = RAMSEL && ~nWEr;
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wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL;
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wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL;
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wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL;
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/* IOROMEN and REGEN control */
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/* IOROMEN control */
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reg IOROMEN = 0;
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reg IOROMEN = 0;
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reg REGEN = 0;
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wire IOROMRES = !nIOSTRB && RA[10:0]==11'h7FF;
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reg nIOSTRBr;
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always @(posedge C25M, posedge IOROMRES) begin
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wire IOROMRES = RAr[10:0]==11'h7FF && ~nIOSTRB && ~nIOSTRBr;
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if (IOROMRES) IOROMEN <= 0;
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always @(posedge C25M, negedge nRESr) begin
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else if (!nRESr) IOROMEN <= 0;
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if (~nRESr) REGEN <= 0;
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else if (!nIOSEL) IOROMEN <= 1;
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else if (PS==8 && ~nIOSEL) REGEN <= 1;
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end
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end
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always @(posedge C25M) begin
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nIOSTRBr <= nIOSTRB;
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/* REGEN control */
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if (~nRESr) IOROMEN <= 0;
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reg REGEN = 0;
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else if (PS==8 && IOROMRES) IOROMEN <= 0;
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always @(posedge C25M, negedge nRESr) begin
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else if (PS==8 && ~nIOSEL) IOROMEN <= 1;
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if (!nRESr) REGEN <= 0;
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else if (!nIOSEL) REGEN <= 1;
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end
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end
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/* Apple data bus */
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/* Apple data bus */
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inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
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inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
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reg [7:0] RDD;
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reg [7:0] RDD;
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output RDdir = ~(PHI0r2 && nWE && PHI0 &&
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output RDdir = !(PHI0r2 && nWE && PHI0 &&
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(~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));
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((!nDEVSEL && RAMExists) || !nIOSEL || (!nIOSTRB && IOROMEN)));
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/* Slinky address registers */
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/* Slinky address registers */
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reg [23:0] Addr = 0;
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reg [23:0] Addr = 0;
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@ -118,16 +93,16 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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reg AddrIncM = 0;
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reg AddrIncM = 0;
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reg AddrIncH = 0;
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reg AddrIncH = 0;
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always @(posedge C25M, negedge nRESr) begin
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always @(posedge C25M, negedge nRESr) begin
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if (~nRESr) begin
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if (!nRESr) begin
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Addr[23:0] <= 24'h000000;
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Addr[23:0] <= 24'h000000;
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AddrIncL <= 0;
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AddrIncL <= 0;
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AddrIncM <= 0;
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AddrIncM <= 0;
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AddrIncH <= 0;
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AddrIncH <= 0;
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end else begin
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end else begin
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if (PS==8 && RAMRegSEL) AddrIncL <= 1;
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if (PS==8 && RAMSEL) AddrIncL <= 1;
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else AddrIncL <= 0;
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else AddrIncL <= 0;
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if (PS==8 && AddrLSEL && ~nWEr) begin
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if (PS==8 && AddrLSEL && !nWE) begin
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Addr[7:0] <= RD[7:0];
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Addr[7:0] <= RD[7:0];
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AddrIncM <= Addr[7] && ~RD[7];
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AddrIncM <= Addr[7] && ~RD[7];
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end else if (AddrIncL) begin
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end else if (AddrIncL) begin
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@ -135,7 +110,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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AddrIncM <= Addr[7:0]==8'hFF;
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AddrIncM <= Addr[7:0]==8'hFF;
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end else AddrIncM <= 0;
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end else AddrIncM <= 0;
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if (PS==8 && AddrMSEL && ~nWEr) begin
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if (PS==8 && AddrMSEL && !nWE) begin
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Addr[15:8] <= RD[7:0];
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Addr[15:8] <= RD[7:0];
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AddrIncH <= Addr[15] && ~RD[7];
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AddrIncH <= Addr[15] && ~RD[7];
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end else if (AddrIncM) begin
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end else if (AddrIncM) begin
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@ -143,7 +118,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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AddrIncH <= Addr[15:8]==8'hFF;
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AddrIncH <= Addr[15:8]==8'hFF;
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end else AddrIncH <= 0;
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end else AddrIncH <= 0;
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if (PS==8 && AddrHSEL && ~nWEr) begin
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if (PS==8 && AddrHSEL && !nWE) begin
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Addr[23:16] <= RD[7:0];
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Addr[23:16] <= RD[7:0];
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end else if (AddrIncH) begin
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end else if (AddrIncH) begin
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Addr[23:16] <= Addr[23:16]+1;
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Addr[23:16] <= Addr[23:16]+1;
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@ -155,7 +130,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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reg Bank = 0;
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reg Bank = 0;
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always @(posedge C25M, negedge nRESr) begin
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always @(posedge C25M, negedge nRESr) begin
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if (~nRESr) Bank <= 0;
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if (~nRESr) Bank <= 0;
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else if (PS==8 && BankSEL && ~nWEr) begin
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else if (PS==8 && BankSEL && !nWE) begin
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Bank <= RD[0];
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Bank <= RD[0];
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end
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end
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end
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end
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@ -327,10 +302,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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/* Apple data bus from SDRAM */
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/* Apple data bus from SDRAM */
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always @(negedge C25M) begin
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always @(negedge C25M) begin
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if (PS==5) begin
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if (PS==5) begin
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if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
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if (!nDEVSEL) case (RA[3:0])
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else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
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4'h0: RDD[7:0] <= Addr[7:0];
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else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
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4'h1: RDD[7:0] <= Addr[15:8];
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else RDD[7:0] <= SD[7:0];
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4'h2: RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
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4'h3: RDD[7:0] <= SD[7:0];
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default: RDD[7:0] <= SD[7:0];
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endcase else RDD[7:0] <= SD[7:0];
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end
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end
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end
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end
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@ -344,28 +322,28 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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always @(posedge C25M) begin
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always @(posedge C25M) begin
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case (PS[3:0])
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case (PS[3:0])
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0: begin // NOP CKE / NOP CKD
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0: begin // NOP CKE / NOP CKD
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RCKE <= PSStart && (IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
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RCKE <= PSStart && (IS==6 || (IS==7 && CXXXr));
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nRCS <= 1;
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nRCS <= 1;
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nRAS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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nSWE <= 1;
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SDOE <= 0;
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SDOE <= 0;
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end 1: begin // ACT CKE / NOP CKD (ACT)
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end 1: begin // ACT CKE / NOP CKD (ACT)
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RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
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RCKE <= RCKE;
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nRCS <= ~(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
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nRCS <= !RCKE;
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nRAS <= 0;
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nRAS <= 0;
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nCAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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nSWE <= 1;
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SDOE <= 0;
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SDOE <= 0;
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end 2: begin // RD CKE / NOP CKD (RD)
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end 2: begin // RD CKE / NOP CKD (RD)
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RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
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RCKE <= RCKE;
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nRCS <= ~(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
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nRCS <= !RCKE;
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nRAS <= 1;
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nRAS <= 1;
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nCAS <= 0;
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nCAS <= 0;
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nSWE <= 1;
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nSWE <= 1;
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SDOE <= 0;
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SDOE <= 0;
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end 3: begin // NOP CKE / CKD
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end 3: begin // NOP CKE / CKD
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RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
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RCKE <= RCKE;
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nRCS <= 1;
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nRCS <= 1;
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nRAS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nCAS <= 1;
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@ -393,19 +371,19 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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nSWE <= 1;
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nSWE <= 1;
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SDOE <= 0;
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SDOE <= 0;
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end 7: begin // NOP CKE / CKD
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end 7: begin // NOP CKE / CKD
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RCKE <= IS==6 || (RAMWR && IS==7);
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RCKE <= IS==6 || (RAMSEL && !nWE && IS==7);
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nRCS <= 1;
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nRCS <= 1;
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nRAS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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nSWE <= 1;
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SDOE <= 0;
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SDOE <= 0;
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end 8: begin // WR AP CKE / NOP CKD (WR AP)
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end 8: begin // WR AP CKE / NOP CKD (WR AP)
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RCKE <= IS==6 || (RAMWR && IS==7);
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RCKE <= RCKE;
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nRCS <= ~(IS==6 || (RAMWR && IS==7));
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nRCS <= !RCKE;
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nRAS <= 1;
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nRAS <= 1;
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nCAS <= 0;
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nCAS <= 0;
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nSWE <= 0;
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nSWE <= 0;
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SDOE <= IS==6 || (RAMWR && IS==7);
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SDOE <= RCKE;
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end 9: begin // NOP CKE / NOP CKD
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end 9: begin // NOP CKE / NOP CKD
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RCKE <= 1;
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RCKE <= 1;
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nRCS <= 1;
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nRCS <= 1;
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@ -421,8 +399,8 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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nSWE <= 0;
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nSWE <= 0;
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SDOE <= 0;
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SDOE <= 0;
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end 11: begin // LDM CKE / AREF CKE / NOP CKD
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end 11: begin // LDM CKE / AREF CKE / NOP CKD
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RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
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RCKE <= RCKE;
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nRCS <= ~(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
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nRCS <= !RCKE;
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nRAS <= 0;
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nRAS <= 0;
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nCAS <= 0;
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nCAS <= 0;
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nSWE <= ~(IS==1);
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nSWE <= ~(IS==1);
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@ -456,25 +434,25 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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if (IS==6) begin
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if (IS==6) begin
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SBA[1:0] <= { 2'b10 };
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SBA[1:0] <= { 2'b10 };
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SA[12:0] <= { 10'b0011000100, LS[12:10] };
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SA[12:0] <= { 10'b0011000100, LS[12:10] };
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end else if (RAMSpecSEL) begin
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end else if (nIOSEL && nIOSTRB) begin
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SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
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SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
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SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
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SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
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SA[9:0] <= Addr[19:10];
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SA[9:0] <= Addr[19:10];
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end else begin
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end else begin
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SBA[1:0] <= 2'b10;
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SBA[1:0] <= 2'b10;
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SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] };
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SA[12:0] <= { 10'b0011000100, Bank, RA[11:10] };
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end
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end
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end 2: begin // RD
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end 2: begin // RD
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if (RAMSpecSEL) begin
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if (nIOSEL && nIOSTRB) begin
|
||||||
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
|
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
|
||||||
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
||||||
DQML <= Addr[0];
|
DQML <= Addr[0];
|
||||||
DQMH <= ~Addr[0];
|
DQMH <= ~Addr[0];
|
||||||
end else begin
|
end else begin
|
||||||
SBA[1:0] <= 2'b10;
|
SBA[1:0] <= 2'b10;
|
||||||
SA[12:0] <= { 4'b0011, RAr[9:1]};
|
SA[12:0] <= { 4'b0011, RA[9:1]};
|
||||||
DQML <= RAr[0];
|
DQML <= RA[0];
|
||||||
DQMH <= ~RAr[0];
|
DQMH <= ~RA[0];
|
||||||
end
|
end
|
||||||
end 3: begin // NOP CKE
|
end 3: begin // NOP CKE
|
||||||
DQML <= 1'b1;
|
DQML <= 1'b1;
|
||||||
|
|
|
||||||
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|
|
@ -1,7 +1,7 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994396726 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681444899848 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994396726 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:06:36 2023 " "Processing started: Tue Mar 28 05:06:36 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994396726 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1679994396726 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444899862 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 00:01:39 2023 " "Processing started: Fri Apr 14 00:01:39 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444899862 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1681444899862 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1679994396726 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1681444899862 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1679994396991 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1681444900157 ""}
|
||||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1679994397038 ""}
|
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1681444900188 ""}
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1679994397038 ""}
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1681444900188 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13057 " "Peak virtual memory: 13057 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994397272 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:37 2023 " "Processing ended: Tue Mar 28 05:06:37 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994397272 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994397272 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994397272 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1679994397272 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13056 " "Peak virtual memory: 13056 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444900423 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:01:40 2023 " "Processing ended: Fri Apr 14 00:01:40 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444900423 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444900423 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444900423 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1681444900423 ""}
|
||||||
|
|
|
||||||
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|
|
@ -1,40 +1,38 @@
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1679994392961 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1681444896092 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1679994392961 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1681444896092 ""}
|
||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1679994392961 ""}
|
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1681444896092 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679994393007 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681444896139 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679994393007 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681444896139 ""}
|
||||||
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1679994393038 ""}
|
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1681444896232 ""}
|
||||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1679994393054 ""}
|
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1681444896248 ""}
|
||||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1679994393132 ""}
|
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444896498 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444896498 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444896498 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444896498 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444896498 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1681444896498 ""}
|
||||||
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1679994393225 ""}
|
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1681444896624 ""}
|
||||||
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1679994393241 ""}
|
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1681444896639 ""}
|
||||||
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1679994393241 ""}
|
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444896639 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444896639 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444896639 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444896639 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1681444896639 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679994393257 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681444896639 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679994393257 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681444896639 ""}
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1679994393257 ""}
|
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681444896654 ""}
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1679994393272 ""}
|
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681444896670 ""}
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1679994393272 ""}
|
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 69 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681444896670 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 14 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681444896670 ""}
|
||||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "temporary_test_loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 417 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1679994393272 ""}
|
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681444896670 ""}
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 88 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RestoreDone~0 " "Destination \"RestoreDone~0\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 150 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1679994393272 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1681444896670 ""}
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1679994393272 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1681444896702 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1679994393272 ""}
|
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1681444896748 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1679994393319 ""}
|
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1681444896763 ""}
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1679994393366 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1681444896763 ""}
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1679994393366 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1681444896763 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1679994393366 ""}
|
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444896810 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1679994393366 ""}
|
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1681444896810 ""}
|
||||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994393413 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1681444896965 ""}
|
||||||
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1679994393429 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444897139 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1679994393554 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1681444897139 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994393804 ""}
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1681444897811 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1679994393804 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444897811 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1679994394585 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1681444897857 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994394585 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "30 " "Router estimated average interconnect usage is 30% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "30 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1681444898076 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1681444898076 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1679994394632 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444898310 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "31 " "Router estimated average interconnect usage is 31% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "31 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1679994394866 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1679994394866 ""}
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1681444898325 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994395147 ""}
|
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444898340 ""}
|
||||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.31 " "Total time spent on timing analysis during the Fitter is 0.31 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1679994395163 ""}
|
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1681444898387 ""}
|
||||||
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994395179 ""}
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1681444898434 ""}
|
||||||
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1679994395225 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13732 " "Peak virtual memory: 13732 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444898489 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:01:38 2023 " "Processing ended: Fri Apr 14 00:01:38 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444898489 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444898489 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444898489 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1681444898489 ""}
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1679994395272 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13733 " "Peak virtual memory: 13733 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994395319 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:35 2023 " "Processing ended: Tue Mar 28 05:06:35 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994395319 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994395319 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994395319 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1679994395319 ""}
|
|
||||||
|
|
|
||||||
|
|
@ -31,10 +31,10 @@ C25M => WRD[5].CLK
|
||||||
C25M => WRD[6].CLK
|
C25M => WRD[6].CLK
|
||||||
C25M => WRD[7].CLK
|
C25M => WRD[7].CLK
|
||||||
C25M => MOSIout.CLK
|
C25M => MOSIout.CLK
|
||||||
|
C25M => FCKOE.CLK
|
||||||
C25M => MOSIOE.CLK
|
C25M => MOSIOE.CLK
|
||||||
C25M => nFCS~reg0.CLK
|
C25M => FCS.CLK
|
||||||
C25M => FCKout.CLK
|
C25M => FCKout.CLK
|
||||||
C25M => RestoreDone.CLK
|
|
||||||
C25M => Bank.CLK
|
C25M => Bank.CLK
|
||||||
C25M => AddrIncH.CLK
|
C25M => AddrIncH.CLK
|
||||||
C25M => AddrIncM.CLK
|
C25M => AddrIncM.CLK
|
||||||
|
|
@ -63,9 +63,8 @@ C25M => Addr[20].CLK
|
||||||
C25M => Addr[21].CLK
|
C25M => Addr[21].CLK
|
||||||
C25M => Addr[22].CLK
|
C25M => Addr[22].CLK
|
||||||
C25M => Addr[23].CLK
|
C25M => Addr[23].CLK
|
||||||
C25M => IOROMEN.CLK
|
|
||||||
C25M => nIOSTRBr.CLK
|
|
||||||
C25M => REGEN.CLK
|
C25M => REGEN.CLK
|
||||||
|
C25M => IOROMEN.CLK
|
||||||
C25M => nRESout~reg0.CLK
|
C25M => nRESout~reg0.CLK
|
||||||
C25M => LS[0].CLK
|
C25M => LS[0].CLK
|
||||||
C25M => LS[1].CLK
|
C25M => LS[1].CLK
|
||||||
|
|
@ -86,10 +85,6 @@ C25M => PS[1].CLK
|
||||||
C25M => PS[2].CLK
|
C25M => PS[2].CLK
|
||||||
C25M => PS[3].CLK
|
C25M => PS[3].CLK
|
||||||
C25M => nRESr.CLK
|
C25M => nRESr.CLK
|
||||||
C25M => nRESf[0].CLK
|
|
||||||
C25M => nRESf[1].CLK
|
|
||||||
C25M => nRESf[2].CLK
|
|
||||||
C25M => nRESf[3].CLK
|
|
||||||
C25M => PHI0r2.CLK
|
C25M => PHI0r2.CLK
|
||||||
C25M => PHI0r1.CLK
|
C25M => PHI0r1.CLK
|
||||||
C25M => IS~7.DATAIN
|
C25M => IS~7.DATAIN
|
||||||
|
|
@ -102,26 +97,21 @@ C25M => RDD[5].CLK
|
||||||
C25M => RDD[6].CLK
|
C25M => RDD[6].CLK
|
||||||
C25M => RDD[7].CLK
|
C25M => RDD[7].CLK
|
||||||
PHI0 => comb.IN1
|
PHI0 => comb.IN1
|
||||||
PHI0 => nWEr.CLK
|
|
||||||
PHI0 => RAr[0].CLK
|
|
||||||
PHI0 => RAr[1].CLK
|
|
||||||
PHI0 => RAr[2].CLK
|
|
||||||
PHI0 => RAr[3].CLK
|
|
||||||
PHI0 => RAr[4].CLK
|
|
||||||
PHI0 => RAr[5].CLK
|
|
||||||
PHI0 => RAr[6].CLK
|
|
||||||
PHI0 => RAr[7].CLK
|
|
||||||
PHI0 => RAr[8].CLK
|
|
||||||
PHI0 => RAr[9].CLK
|
|
||||||
PHI0 => RAr[10].CLK
|
|
||||||
PHI0 => RAr[11].CLK
|
|
||||||
PHI0 => CXXXr.CLK
|
PHI0 => CXXXr.CLK
|
||||||
PHI0 => PHI0r1.DATAIN
|
PHI0 => PHI0r1.DATAIN
|
||||||
nRES => MOSIout.OUTPUTSELECT
|
nRES => nRESr.DATAIN
|
||||||
nRES => nRESf[0].DATAIN
|
|
||||||
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
SetFW[0] => ~NO_FANOUT~
|
SetFW[0] => Mux1.IN7
|
||||||
SetFW[1] => ~NO_FANOUT~
|
SetFW[1] => RAMExists.IN1
|
||||||
|
SetFW[1] => RDD.OUTPUTSELECT
|
||||||
|
SetFW[1] => RDD.OUTPUTSELECT
|
||||||
|
SetFW[1] => RDD.OUTPUTSELECT
|
||||||
|
SetFW[1] => RDD.OUTPUTSELECT
|
||||||
|
SetFW[1] => SA.OUTPUTSELECT
|
||||||
|
SetFW[1] => SA.OUTPUTSELECT
|
||||||
|
SetFW[1] => SA.OUTPUTSELECT
|
||||||
|
SetFW[1] => SBA.OUTPUTSELECT
|
||||||
|
SetFW[1] => MOSIout.DATAB
|
||||||
INTin => INTout.DATAIN
|
INTin => INTout.DATAIN
|
||||||
INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
|
INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
DMAin => DMAout.DATAIN
|
DMAin => DMAout.DATAIN
|
||||||
|
|
@ -132,35 +122,92 @@ nRDYout <= <VCC>
|
||||||
nINHout <= <VCC>
|
nINHout <= <VCC>
|
||||||
RWout <= <VCC>
|
RWout <= <VCC>
|
||||||
nDMAout <= <VCC>
|
nDMAout <= <VCC>
|
||||||
RA[0] => RAr[0].DATAIN
|
RA[0] => Mux11.IN17
|
||||||
RA[0] => Equal17.IN10
|
RA[0] => Mux12.IN17
|
||||||
RA[1] => RAr[1].DATAIN
|
RA[0] => Mux13.IN17
|
||||||
RA[1] => Equal17.IN9
|
RA[0] => Mux14.IN17
|
||||||
RA[2] => RAr[2].DATAIN
|
RA[0] => Mux15.IN16
|
||||||
RA[2] => Equal17.IN8
|
RA[0] => Mux16.IN16
|
||||||
RA[3] => RAr[3].DATAIN
|
RA[0] => Mux17.IN16
|
||||||
RA[3] => Equal17.IN7
|
RA[0] => Mux18.IN16
|
||||||
RA[4] => RAr[4].DATAIN
|
RA[0] => DQML.DATAA
|
||||||
RA[4] => Equal17.IN6
|
RA[0] => Equal8.IN3
|
||||||
RA[5] => RAr[5].DATAIN
|
RA[0] => Equal9.IN3
|
||||||
RA[5] => Equal17.IN5
|
RA[0] => Equal10.IN2
|
||||||
RA[6] => RAr[6].DATAIN
|
RA[0] => Equal11.IN3
|
||||||
RA[6] => Equal17.IN4
|
RA[0] => Equal12.IN3
|
||||||
RA[7] => RAr[7].DATAIN
|
RA[0] => Equal13.IN10
|
||||||
RA[7] => Equal17.IN3
|
RA[0] => DQMH.DATAA
|
||||||
RA[8] => RAr[8].DATAIN
|
RA[1] => Mux11.IN16
|
||||||
RA[8] => Equal17.IN2
|
RA[1] => Mux12.IN16
|
||||||
RA[9] => RAr[9].DATAIN
|
RA[1] => Mux13.IN16
|
||||||
RA[9] => Equal17.IN1
|
RA[1] => Mux14.IN16
|
||||||
RA[10] => RAr[10].DATAIN
|
RA[1] => Mux15.IN15
|
||||||
RA[10] => Equal17.IN0
|
RA[1] => Mux16.IN15
|
||||||
RA[11] => RAr[11].DATAIN
|
RA[1] => Mux17.IN15
|
||||||
|
RA[1] => Mux18.IN15
|
||||||
|
RA[1] => SA.DATAA
|
||||||
|
RA[1] => Equal8.IN2
|
||||||
|
RA[1] => Equal9.IN2
|
||||||
|
RA[1] => Equal10.IN3
|
||||||
|
RA[1] => Equal11.IN2
|
||||||
|
RA[1] => Equal12.IN2
|
||||||
|
RA[1] => Equal13.IN9
|
||||||
|
RA[2] => Mux11.IN15
|
||||||
|
RA[2] => Mux12.IN15
|
||||||
|
RA[2] => Mux13.IN15
|
||||||
|
RA[2] => Mux14.IN15
|
||||||
|
RA[2] => Mux15.IN14
|
||||||
|
RA[2] => Mux16.IN14
|
||||||
|
RA[2] => Mux17.IN14
|
||||||
|
RA[2] => Mux18.IN14
|
||||||
|
RA[2] => SA.DATAA
|
||||||
|
RA[2] => Equal8.IN1
|
||||||
|
RA[2] => Equal9.IN1
|
||||||
|
RA[2] => Equal10.IN1
|
||||||
|
RA[2] => Equal11.IN1
|
||||||
|
RA[2] => Equal12.IN1
|
||||||
|
RA[2] => Equal13.IN8
|
||||||
|
RA[3] => Mux11.IN14
|
||||||
|
RA[3] => Mux12.IN14
|
||||||
|
RA[3] => Mux13.IN14
|
||||||
|
RA[3] => Mux14.IN14
|
||||||
|
RA[3] => Mux15.IN13
|
||||||
|
RA[3] => Mux16.IN13
|
||||||
|
RA[3] => Mux17.IN13
|
||||||
|
RA[3] => Mux18.IN13
|
||||||
|
RA[3] => SA.DATAA
|
||||||
|
RA[3] => Equal8.IN0
|
||||||
|
RA[3] => Equal9.IN0
|
||||||
|
RA[3] => Equal10.IN0
|
||||||
|
RA[3] => Equal11.IN0
|
||||||
|
RA[3] => Equal12.IN0
|
||||||
|
RA[3] => Equal13.IN7
|
||||||
|
RA[4] => SA.DATAA
|
||||||
|
RA[4] => Equal13.IN6
|
||||||
|
RA[5] => SA.DATAA
|
||||||
|
RA[5] => Equal13.IN5
|
||||||
|
RA[6] => SA.DATAA
|
||||||
|
RA[6] => Equal13.IN4
|
||||||
|
RA[7] => SA.DATAA
|
||||||
|
RA[7] => Equal13.IN3
|
||||||
|
RA[8] => SA.DATAA
|
||||||
|
RA[8] => Equal13.IN2
|
||||||
|
RA[9] => SA.DATAA
|
||||||
|
RA[9] => Equal13.IN1
|
||||||
|
RA[10] => SA.DATAA
|
||||||
|
RA[10] => Equal13.IN0
|
||||||
|
RA[11] => SA.DATAA
|
||||||
RA[12] => Equal7.IN1
|
RA[12] => Equal7.IN1
|
||||||
RA[13] => Equal7.IN0
|
RA[13] => Equal7.IN0
|
||||||
RA[14] => Equal7.IN3
|
RA[14] => Equal7.IN3
|
||||||
RA[15] => Equal7.IN2
|
RA[15] => Equal7.IN2
|
||||||
nWE => comb.IN1
|
nWE => comb.IN1
|
||||||
nWE => nWEr.DATAIN
|
nWE => RCKE.IN1
|
||||||
|
nWE => always9.IN1
|
||||||
|
nWE => always8.IN1
|
||||||
|
nWE => always8.IN1
|
||||||
|
nWE => always8.IN1
|
||||||
RD[0] <> RD[0]
|
RD[0] <> RD[0]
|
||||||
RD[1] <> RD[1]
|
RD[1] <> RD[1]
|
||||||
RD[2] <> RD[2]
|
RD[2] <> RD[2]
|
||||||
|
|
@ -171,17 +218,24 @@ RD[6] <> RD[6]
|
||||||
RD[7] <> RD[7]
|
RD[7] <> RD[7]
|
||||||
RAdir <= <VCC>
|
RAdir <= <VCC>
|
||||||
RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
|
RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
nIOSEL => SA.OUTPUTSELECT
|
nIOSEL => always15.IN0
|
||||||
nIOSEL => comb.IN0
|
nIOSEL => IOROMEN.OUTPUTSELECT
|
||||||
nIOSEL => always6.IN1
|
nIOSEL => comb.IN1
|
||||||
|
nIOSEL => REGEN.ENA
|
||||||
|
nDEVSEL => RDD.OUTPUTSELECT
|
||||||
|
nDEVSEL => RDD.OUTPUTSELECT
|
||||||
|
nDEVSEL => RDD.OUTPUTSELECT
|
||||||
|
nDEVSEL => RDD.OUTPUTSELECT
|
||||||
|
nDEVSEL => RDD.OUTPUTSELECT
|
||||||
|
nDEVSEL => RDD.OUTPUTSELECT
|
||||||
|
nDEVSEL => RDD.OUTPUTSELECT
|
||||||
|
nDEVSEL => RDD.OUTPUTSELECT
|
||||||
nDEVSEL => comb.IN1
|
nDEVSEL => comb.IN1
|
||||||
nDEVSEL => RAMSEL.IN1
|
|
||||||
nDEVSEL => FCKout.IN1
|
|
||||||
nDEVSEL => comb.IN1
|
nDEVSEL => comb.IN1
|
||||||
nDEVSEL => RAMRegSEL.IN1
|
nDEVSEL => comb.IN1
|
||||||
nIOSTRB => nIOSTRBr.DATAIN
|
nIOSTRB => always15.IN1
|
||||||
nIOSTRB => comb.IN1
|
|
||||||
nIOSTRB => comb.IN1
|
nIOSTRB => comb.IN1
|
||||||
|
nIOSTRB => IOROMRES.IN1
|
||||||
SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
|
@ -212,10 +266,9 @@ SD[4] <> SD[4]
|
||||||
SD[5] <> SD[5]
|
SD[5] <> SD[5]
|
||||||
SD[6] <> SD[6]
|
SD[6] <> SD[6]
|
||||||
SD[7] <> SD[7]
|
SD[7] <> SD[7]
|
||||||
nFCS <= nFCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
FCK <= FCKout.DB_MAX_OUTPUT_PORT_TYPE
|
FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
MISO => WRD.DATAB
|
MISO => WRD.DATAB
|
||||||
MISO => RDD.DATAB
|
|
||||||
MOSI <> MOSI
|
MOSI <> MOSI
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,21 +1,20 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994373538 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681444876827 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994373554 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:06:13 2023 " "Processing started: Tue Mar 28 05:06:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994373554 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994373554 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444876827 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 00:01:16 2023 " "Processing started: Fri Apr 14 00:01:16 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444876827 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444876827 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994373554 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444876827 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679994373897 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1681444877218 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679994373897 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1681444877218 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(104) " "Verilog HDL warning at GR8RAM.v(104): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 104 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994390038 ""}
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(85) " "Verilog HDL warning at GR8RAM.v(85): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681444893408 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(281) " "Verilog HDL warning at GR8RAM.v(281): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 281 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994390038 ""}
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(261) " "Verilog HDL warning at GR8RAM.v(261): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 261 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681444893408 ""}
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679994390038 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994390038 ""}
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1681444893408 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444893408 ""}
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679994390069 ""}
|
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1681444893440 ""}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(34) " "Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(31) " "Verilog HDL assignment warning at GR8RAM.v(31): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 31 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444893455 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(39) " "Verilog HDL assignment warning at GR8RAM.v(39): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(36) " "Verilog HDL assignment warning at GR8RAM.v(36): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 36 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444893455 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(128) " "Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 128 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(109) " "Verilog HDL assignment warning at GR8RAM.v(109): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444893455 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(136) " "Verilog HDL assignment warning at GR8RAM.v(136): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 136 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(117) " "Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444893455 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(143) " "Verilog HDL assignment warning at GR8RAM.v(143): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 143 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(124) " "Verilog HDL assignment warning at GR8RAM.v(124): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444893455 "|GR8RAM"}
|
||||||
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 -1 1679994390538 ""}
|
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 -1 1681444893877 ""}
|
||||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 559 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 560 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 558 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 442 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|SBA[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1679994390757 ""}
|
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 541 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 544 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 543 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 542 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 545 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 540 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1681444894049 ""}
|
||||||
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1679994391085 ""}
|
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1681444894252 ""}
|
||||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1679994391100 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1679994391100 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1679994391100 ""}
|
{ "Info" "ICUT_CUT_TM_SUMMARY" "305 " "Implemented 305 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1681444894268 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1681444894268 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1681444894268 ""} { "Info" "ICUT_CUT_TM_LCELLS" "225 " "Implemented 225 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1681444894268 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1681444894268 ""}
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "336 " "Implemented 336 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679994391100 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679994391100 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1679994391100 ""} { "Info" "ICUT_CUT_TM_LCELLS" "256 " "Implemented 256 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679994391100 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679994391100 ""}
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444894331 ""}
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994391147 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13092 " "Peak virtual memory: 13092 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444894347 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:01:34 2023 " "Processing ended: Fri Apr 14 00:01:34 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444894347 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444894347 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444894347 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444894347 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13094 " "Peak virtual memory: 13094 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994391179 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:31 2023 " "Processing ended: Tue Mar 28 05:06:31 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994391179 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994391179 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994391179 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994391179 ""}
|
|
||||||
|
|
|
||||||
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|
@ -1,22 +1,22 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994398756 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681444902112 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994398756 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:06:38 2023 " "Processing started: Tue Mar 28 05:06:38 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994398756 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1679994398756 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444902128 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 00:01:41 2023 " "Processing started: Fri Apr 14 00:01:41 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444902128 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1681444902128 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1679994398756 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1681444902128 ""}
|
||||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1679994398866 ""}
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1681444902237 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1679994399077 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1681444902472 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1679994399077 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1681444902472 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399112 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444902534 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399112 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444902534 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1679994399175 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1681444902597 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1679994399581 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1681444903003 ""}
|
||||||
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1679994399659 ""}
|
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1681444903068 ""}
|
||||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1679994399659 ""}
|
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1681444903083 ""}
|
||||||
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1679994399690 ""}
|
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1681444903115 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.472 " "Worst-case setup slack is 12.472" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.472 0.000 C25M " " 12.472 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399706 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 14.252 " "Worst-case setup slack is 14.252" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 14.252 0.000 C25M " " 14.252 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444903130 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.383 " "Worst-case hold slack is 1.383" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.383 0.000 C25M " " 1.383 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399706 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.394 " "Worst-case hold slack is 1.394" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.394 0.000 C25M " " 1.394 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444903130 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.331 " "Worst-case recovery slack is 33.331" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.331 0.000 C25M " " 33.331 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399722 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.179 " "Worst-case recovery slack is 33.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.179 0.000 C25M " " 33.179 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444903130 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.115 " "Worst-case removal slack is 6.115" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.115 0.000 C25M " " 6.115 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399722 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.267 " "Worst-case removal slack is 6.267" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.267 0.000 C25M " " 6.267 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444903146 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399722 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444903146 ""}
|
||||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1679994399769 ""}
|
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1681444903193 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679994399784 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681444903208 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679994399784 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681444903224 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13052 " "Peak virtual memory: 13052 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994399847 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:39 2023 " "Processing ended: Tue Mar 28 05:06:39 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994399847 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994399847 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994399847 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1679994399847 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13051 " "Peak virtual memory: 13051 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444903292 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:01:43 2023 " "Processing ended: Fri Apr 14 00:01:43 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444903292 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444903292 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444903292 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1681444903292 ""}
|
||||||
|
|
|
||||||
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|
|
@ -1,11 +1,95 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994334673 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681444781029 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994334673 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:05:34 2023 " "Processing started: Tue Mar 28 05:05:34 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994334673 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994334673 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444781029 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 13 23:59:40 2023 " "Processing started: Thu Apr 13 23:59:40 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444781029 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444781029 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994334673 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444781029 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679994335048 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1681444781402 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679994335048 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1681444781402 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(103) " "Verilog HDL warning at GR8RAM.v(103): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994351125 ""}
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(85) " "Verilog HDL warning at GR8RAM.v(85): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681444798192 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(280) " "Verilog HDL warning at GR8RAM.v(280): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 280 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994351125 ""}
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(261) " "Verilog HDL warning at GR8RAM.v(261): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 261 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681444798192 ""}
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679994351125 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994351125 ""}
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1681444798192 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444798192 ""}
|
||||||
{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW GR8RAM.v(1) " "Verilog HDL error at GR8RAM.v(1): object \"SetFW\" is not declared. Verify the object name is correct. If the name is correct, declare the object." { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1679994351125 ""}
|
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1681444798239 ""}
|
||||||
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "13076 " "Peak virtual memory: 13076 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994351157 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Mar 28 05:05:51 2023 " "Processing ended: Tue Mar 28 05:05:51 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994351157 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994351157 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994351157 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994351157 ""}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(31) " "Verilog HDL assignment warning at GR8RAM.v(31): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 31 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444798254 "|GR8RAM"}
|
||||||
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1 " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994351875 ""}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(36) " "Verilog HDL assignment warning at GR8RAM.v(36): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 36 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444798254 "|GR8RAM"}
|
||||||
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(109) " "Verilog HDL assignment warning at GR8RAM.v(109): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444798254 "|GR8RAM"}
|
||||||
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(117) " "Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444798270 "|GR8RAM"}
|
||||||
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(124) " "Verilog HDL assignment warning at GR8RAM.v(124): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444798270 "|GR8RAM"}
|
||||||
|
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 -1 1681444798739 ""}
|
||||||
|
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 541 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 544 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 543 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 542 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 545 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 540 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1681444798911 ""}
|
||||||
|
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1681444799194 ""}
|
||||||
|
{ "Info" "ICUT_CUT_TM_SUMMARY" "305 " "Implemented 305 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1681444799208 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1681444799208 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1681444799208 ""} { "Info" "ICUT_CUT_TM_LCELLS" "225 " "Implemented 225 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1681444799208 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1681444799208 ""}
|
||||||
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444799270 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13091 " "Peak virtual memory: 13091 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444799301 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 13 23:59:59 2023 " "Processing ended: Thu Apr 13 23:59:59 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444799301 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Elapsed time: 00:00:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444799301 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444799301 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444799301 ""}
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1681444800872 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444800888 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 00:00:00 2023 " "Processing started: Fri Apr 14 00:00:00 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444800888 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1681444800888 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1681444800888 ""}
|
||||||
|
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1681444800982 ""}
|
||||||
|
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1681444800982 ""}
|
||||||
|
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1681444800982 ""}
|
||||||
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1681444801107 ""}
|
||||||
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1681444801107 ""}
|
||||||
|
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1681444801107 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681444801153 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681444801169 ""}
|
||||||
|
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1681444801263 ""}
|
||||||
|
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1681444801278 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444801528 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444801528 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444801528 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444801528 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444801528 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1681444801528 ""}
|
||||||
|
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1681444801716 ""}
|
||||||
|
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1681444801747 ""}
|
||||||
|
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444801747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444801747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444801747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444801747 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1681444801747 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681444801747 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681444801747 ""}
|
||||||
|
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681444801747 ""}
|
||||||
|
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681444801779 ""}
|
||||||
|
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 69 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681444801779 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 14 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681444801779 ""}
|
||||||
|
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681444801779 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1681444801779 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1681444801810 ""}
|
||||||
|
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1681444801857 ""}
|
||||||
|
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1681444801857 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1681444801857 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1681444801857 ""}
|
||||||
|
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444801919 ""}
|
||||||
|
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1681444801919 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1681444802060 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444802294 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1681444802310 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1681444803044 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444803044 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1681444803092 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "32 " "Router estimated average interconnect usage is 32% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "32 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1681444803327 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1681444803327 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444803607 ""}
|
||||||
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.32 " "Total time spent on timing analysis during the Fitter is 0.32 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1681444803622 ""}
|
||||||
|
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444803638 ""}
|
||||||
|
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1681444803685 ""}
|
||||||
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1681444803732 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13735 " "Peak virtual memory: 13735 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444803779 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:00:03 2023 " "Processing ended: Fri Apr 14 00:00:03 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444803779 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444803779 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444803779 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1681444803779 ""}
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1681444805211 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444805211 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 00:00:05 2023 " "Processing started: Fri Apr 14 00:00:05 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444805211 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1681444805211 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1681444805211 ""}
|
||||||
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1681444805477 ""}
|
||||||
|
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1681444805508 ""}
|
||||||
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1681444805524 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13055 " "Peak virtual memory: 13055 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444805748 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:00:05 2023 " "Processing ended: Fri Apr 14 00:00:05 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444805748 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444805748 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444805748 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1681444805748 ""}
|
||||||
|
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1681444806469 ""}
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1681444807407 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444807407 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 00:00:07 2023 " "Processing started: Fri Apr 14 00:00:07 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444807407 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1681444807407 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1681444807407 ""}
|
||||||
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1681444807517 ""}
|
||||||
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1681444807689 ""}
|
||||||
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1681444807689 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444807735 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444807735 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1681444807802 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1681444808204 ""}
|
||||||
|
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1681444808267 ""}
|
||||||
|
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1681444808282 ""}
|
||||||
|
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1681444808314 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 14.271 " "Worst-case setup slack is 14.271" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808314 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808314 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 14.271 0.000 C25M " " 14.271 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808314 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444808314 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.385 " "Worst-case hold slack is 1.385" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.385 0.000 C25M " " 1.385 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444808329 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 32.601 " "Worst-case recovery slack is 32.601" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 32.601 0.000 C25M " " 32.601 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444808329 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.845 " "Worst-case removal slack is 6.845" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.845 0.000 C25M " " 6.845 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444808329 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444808329 ""}
|
||||||
|
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1681444808376 ""}
|
||||||
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681444808407 ""}
|
||||||
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681444808407 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13053 " "Peak virtual memory: 13053 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444808471 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:00:08 2023 " "Processing ended: Fri Apr 14 00:00:08 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444808471 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444808471 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444808471 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1681444808471 ""}
|
||||||
|
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 19 s " "Quartus Prime Full Compilation was successful. 0 errors, 19 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1681444809260 ""}
|
||||||
|
|
|
||||||
Binary file not shown.
|
|
@ -1,5 +1,5 @@
|
||||||
Assembler report for GR8RAM
|
Assembler report for GR8RAM
|
||||||
Tue Mar 28 05:06:37 2023
|
Fri Apr 14 00:01:40 2023
|
||||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
|
||||||
+---------------------------------------------------------------+
|
+---------------------------------------------------------------+
|
||||||
; Assembler Summary ;
|
; Assembler Summary ;
|
||||||
+-----------------------+---------------------------------------+
|
+-----------------------+---------------------------------------+
|
||||||
; Assembler Status ; Successful - Tue Mar 28 05:06:37 2023 ;
|
; Assembler Status ; Successful - Fri Apr 14 00:01:40 2023 ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX II ;
|
; Family ; MAX II ;
|
||||||
|
|
@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula.
|
||||||
+----------------+-------------------------------------------------------+
|
+----------------+-------------------------------------------------------+
|
||||||
; Option ; Setting ;
|
; Option ; Setting ;
|
||||||
+----------------+-------------------------------------------------------+
|
+----------------+-------------------------------------------------------+
|
||||||
; JTAG usercode ; 0x001615F8 ;
|
; JTAG usercode ; 0x00166C15 ;
|
||||||
; Checksum ; 0x001618F8 ;
|
; Checksum ; 0x00167085 ;
|
||||||
+----------------+-------------------------------------------------------+
|
+----------------+-------------------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula.
|
||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus Prime Assembler
|
Info: Running Quartus Prime Assembler
|
||||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Info: Processing started: Tue Mar 28 05:06:36 2023
|
Info: Processing started: Fri Apr 14 00:01:39 2023
|
||||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
Info (115031): Writing out detailed assembly data for power analysis
|
Info (115031): Writing out detailed assembly data for power analysis
|
||||||
Info (115030): Assembler is generating device programming files
|
Info (115030): Assembler is generating device programming files
|
||||||
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
|
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
|
||||||
Info: Peak virtual memory: 13057 megabytes
|
Info: Peak virtual memory: 13056 megabytes
|
||||||
Info: Processing ended: Tue Mar 28 05:06:37 2023
|
Info: Processing ended: Fri Apr 14 00:01:40 2023
|
||||||
Info: Elapsed time: 00:00:01
|
Info: Elapsed time: 00:00:01
|
||||||
Info: Total CPU time (on all processors): 00:00:01
|
Info: Total CPU time (on all processors): 00:00:01
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1 +1 @@
|
||||||
Tue Mar 28 05:06:40 2023
|
Fri Apr 14 00:01:44 2023
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
Fitter report for GR8RAM
|
Fitter report for GR8RAM
|
||||||
Tue Mar 28 05:06:35 2023
|
Fri Apr 14 00:01:38 2023
|
||||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -57,14 +57,14 @@ https://fpgasoftware.intel.com/eula.
|
||||||
+---------------------------------------------------------------------+
|
+---------------------------------------------------------------------+
|
||||||
; Fitter Summary ;
|
; Fitter Summary ;
|
||||||
+-----------------------+---------------------------------------------+
|
+-----------------------+---------------------------------------------+
|
||||||
; Fitter Status ; Successful - Tue Mar 28 05:06:35 2023 ;
|
; Fitter Status ; Successful - Fri Apr 14 00:01:38 2023 ;
|
||||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX II ;
|
; Family ; MAX II ;
|
||||||
; Device ; EPM240T100C5 ;
|
; Device ; EPM240T100C5 ;
|
||||||
; Timing Models ; Final ;
|
; Timing Models ; Final ;
|
||||||
; Total logic elements ; 236 / 240 ( 98 % ) ;
|
; Total logic elements ; 220 / 240 ( 92 % ) ;
|
||||||
; Total pins ; 80 / 80 ( 100 % ) ;
|
; Total pins ; 80 / 80 ( 100 % ) ;
|
||||||
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
||||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||||
|
|
@ -129,13 +129,13 @@ https://fpgasoftware.intel.com/eula.
|
||||||
; Number detected on machine ; 4 ;
|
; Number detected on machine ; 4 ;
|
||||||
; Maximum allowed ; 4 ;
|
; Maximum allowed ; 4 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Average used ; 1.04 ;
|
; Average used ; 1.03 ;
|
||||||
; Maximum used ; 4 ;
|
; Maximum used ; 4 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Usage by Processor ; % Time Used ;
|
; Usage by Processor ; % Time Used ;
|
||||||
; Processor 1 ; 100.0% ;
|
; Processor 1 ; 100.0% ;
|
||||||
; Processor 2 ; 1.6% ;
|
; Processor 2 ; 1.2% ;
|
||||||
; Processors 3-4 ; 1.2% ;
|
; Processors 3-4 ; 1.0% ;
|
||||||
+----------------------------+-------------+
|
+----------------------------+-------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -150,28 +150,28 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
+---------------------------------------------+-----------------------+
|
+---------------------------------------------+-----------------------+
|
||||||
; Resource ; Usage ;
|
; Resource ; Usage ;
|
||||||
+---------------------------------------------+-----------------------+
|
+---------------------------------------------+-----------------------+
|
||||||
; Total logic elements ; 236 / 240 ( 98 % ) ;
|
; Total logic elements ; 220 / 240 ( 92 % ) ;
|
||||||
; -- Combinational with no register ; 119 ;
|
; -- Combinational with no register ; 120 ;
|
||||||
; -- Register only ; 1 ;
|
; -- Register only ; 1 ;
|
||||||
; -- Combinational with a register ; 116 ;
|
; -- Combinational with a register ; 99 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Logic element usage by number of LUT inputs ; ;
|
; Logic element usage by number of LUT inputs ; ;
|
||||||
; -- 4 input functions ; 137 ;
|
; -- 4 input functions ; 120 ;
|
||||||
; -- 3 input functions ; 35 ;
|
; -- 3 input functions ; 32 ;
|
||||||
; -- 2 input functions ; 63 ;
|
; -- 2 input functions ; 66 ;
|
||||||
; -- 1 input functions ; 0 ;
|
; -- 1 input functions ; 1 ;
|
||||||
; -- 0 input functions ; 0 ;
|
; -- 0 input functions ; 0 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Logic elements by mode ; ;
|
; Logic elements by mode ; ;
|
||||||
; -- normal mode ; 203 ;
|
; -- normal mode ; 187 ;
|
||||||
; -- arithmetic mode ; 33 ;
|
; -- arithmetic mode ; 33 ;
|
||||||
; -- qfbk mode ; 15 ;
|
; -- qfbk mode ; 3 ;
|
||||||
; -- register cascade mode ; 0 ;
|
; -- register cascade mode ; 0 ;
|
||||||
; -- synchronous clear/load mode ; 64 ;
|
; -- synchronous clear/load mode ; 49 ;
|
||||||
; -- asynchronous clear/load mode ; 29 ;
|
; -- asynchronous clear/load mode ; 30 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Total registers ; 117 / 240 ( 49 % ) ;
|
; Total registers ; 100 / 240 ( 42 % ) ;
|
||||||
; Total LABs ; 24 / 24 ( 100 % ) ;
|
; Total LABs ; 23 / 24 ( 96 % ) ;
|
||||||
; Logic elements in carry chains ; 37 ;
|
; Logic elements in carry chains ; 37 ;
|
||||||
; Virtual pins ; 0 ;
|
; Virtual pins ; 0 ;
|
||||||
; I/O pins ; 80 / 80 ( 100 % ) ;
|
; I/O pins ; 80 / 80 ( 100 % ) ;
|
||||||
|
|
@ -182,15 +182,15 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
; -- Total Fixed Point DSP Blocks ; 0 ;
|
; -- Total Fixed Point DSP Blocks ; 0 ;
|
||||||
; -- Total Floating Point DSP Blocks ; 0 ;
|
; -- Total Floating Point DSP Blocks ; 0 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Global signals ; 3 ;
|
; Global signals ; 2 ;
|
||||||
; -- Global clocks ; 3 / 4 ( 75 % ) ;
|
; -- Global clocks ; 2 / 4 ( 50 % ) ;
|
||||||
; JTAGs ; 0 / 1 ( 0 % ) ;
|
; JTAGs ; 0 / 1 ( 0 % ) ;
|
||||||
; Average interconnect usage (total/H/V) ; 38.7% / 42.5% / 34.6% ;
|
; Average interconnect usage (total/H/V) ; 37.0% / 38.2% / 35.8% ;
|
||||||
; Peak interconnect usage (total/H/V) ; 38.7% / 42.5% / 34.6% ;
|
; Peak interconnect usage (total/H/V) ; 37.0% / 38.2% / 35.8% ;
|
||||||
; Maximum fan-out ; 103 ;
|
; Maximum fan-out ; 99 ;
|
||||||
; Highest non-global fan-out ; 53 ;
|
; Highest non-global fan-out ; 43 ;
|
||||||
; Total fan-out ; 1101 ;
|
; Total fan-out ; 1019 ;
|
||||||
; Average fan-out ; 3.48 ;
|
; Average fan-out ; 3.40 ;
|
||||||
+---------------------------------------------+-----------------------+
|
+---------------------------------------------+-----------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -199,34 +199,34 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
|
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
|
||||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ;
|
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ;
|
||||||
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
|
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
|
||||||
; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 103 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 99 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 2 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ; no ;
|
; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 15 ; 0 ; yes ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
|
; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
|
||||||
; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
|
||||||
; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 0 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ;
|
; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ;
|
||||||
; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 0 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ;
|
; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 8 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ;
|
||||||
; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
|
; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
|
||||||
; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
|
; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
|
||||||
; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
|
; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
|
||||||
; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
|
; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
|
||||||
; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
|
; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
|
||||||
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
|
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -238,7 +238,7 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; yes ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; yes ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
|
||||||
; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
|
|
@ -252,7 +252,7 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
|
; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
|
|
@ -261,14 +261,14 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
|
; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
|
; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||||
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||||
|
|
||||||
|
|
@ -279,22 +279,22 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
|
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
|
||||||
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||||
; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; MOSIOE ; - ;
|
; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; MOSIOE ; - ;
|
||||||
; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
||||||
; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; comb~2 ; - ;
|
; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
||||||
; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
||||||
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; comb~2 ; - ;
|
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
||||||
; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
||||||
; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; comb~2 ; - ;
|
; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
||||||
; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
||||||
; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
|
||||||
; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
|
||||||
; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
||||||
; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
|
||||||
; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
||||||
; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
||||||
; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
||||||
; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
||||||
; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
|
; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
|
||||||
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -438,7 +438,7 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
||||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
||||||
; |GR8RAM ; 236 (236) ; 117 ; 0 ; 80 ; 0 ; 119 (119) ; 1 (1) ; 116 (116) ; 37 (37) ; 20 (20) ; |GR8RAM ; GR8RAM ; work ;
|
; |GR8RAM ; 220 (220) ; 100 ; 0 ; 80 ; 0 ; 120 (120) ; 1 (1) ; 99 (99) ; 37 (37) ; 4 (4) ; |GR8RAM ; GR8RAM ; work ;
|
||||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
||||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||||
|
|
||||||
|
|
@ -449,8 +449,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||||
; Name ; Pin Type ; Pad to Core 0 ;
|
; Name ; Pin Type ; Pad to Core 0 ;
|
||||||
+----------+----------+---------------+
|
+----------+----------+---------------+
|
||||||
; nRESout ; Output ; -- ;
|
; nRESout ; Output ; -- ;
|
||||||
; SetFW[0] ; Input ; (0) ;
|
|
||||||
; SetFW[1] ; Input ; (0) ;
|
|
||||||
; INTout ; Output ; -- ;
|
; INTout ; Output ; -- ;
|
||||||
; DMAout ; Output ; -- ;
|
; DMAout ; Output ; -- ;
|
||||||
; nNMIout ; Output ; -- ;
|
; nNMIout ; Output ; -- ;
|
||||||
|
|
@ -506,10 +504,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||||
; DMAin ; Input ; (1) ;
|
; DMAin ; Input ; (1) ;
|
||||||
; PHI0 ; Input ; (0) ;
|
; PHI0 ; Input ; (0) ;
|
||||||
; nWE ; Input ; (1) ;
|
; nWE ; Input ; (1) ;
|
||||||
; RA[0] ; Input ; (1) ;
|
; SetFW[1] ; Input ; (1) ;
|
||||||
|
; nDEVSEL ; Input ; (1) ;
|
||||||
|
; nIOSEL ; Input ; (1) ;
|
||||||
|
; nIOSTRB ; Input ; (1) ;
|
||||||
|
; C25M ; Input ; (0) ;
|
||||||
; RA[1] ; Input ; (1) ;
|
; RA[1] ; Input ; (1) ;
|
||||||
; RA[2] ; Input ; (1) ;
|
; RA[2] ; Input ; (1) ;
|
||||||
; RA[3] ; Input ; (1) ;
|
; RA[3] ; Input ; (1) ;
|
||||||
|
; RA[0] ; Input ; (1) ;
|
||||||
; RA[4] ; Input ; (1) ;
|
; RA[4] ; Input ; (1) ;
|
||||||
; RA[5] ; Input ; (1) ;
|
; RA[5] ; Input ; (1) ;
|
||||||
; RA[6] ; Input ; (1) ;
|
; RA[6] ; Input ; (1) ;
|
||||||
|
|
@ -517,39 +520,38 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||||
; RA[8] ; Input ; (1) ;
|
; RA[8] ; Input ; (1) ;
|
||||||
; RA[9] ; Input ; (1) ;
|
; RA[9] ; Input ; (1) ;
|
||||||
; RA[10] ; Input ; (1) ;
|
; RA[10] ; Input ; (1) ;
|
||||||
; nIOSTRB ; Input ; (1) ;
|
|
||||||
; nIOSEL ; Input ; (1) ;
|
|
||||||
; nDEVSEL ; Input ; (1) ;
|
|
||||||
; C25M ; Input ; (0) ;
|
|
||||||
; RA[11] ; Input ; (1) ;
|
; RA[11] ; Input ; (1) ;
|
||||||
|
; nRES ; Input ; (1) ;
|
||||||
; RA[14] ; Input ; (1) ;
|
; RA[14] ; Input ; (1) ;
|
||||||
; RA[15] ; Input ; (1) ;
|
; RA[15] ; Input ; (1) ;
|
||||||
; RA[12] ; Input ; (1) ;
|
; RA[12] ; Input ; (1) ;
|
||||||
; RA[13] ; Input ; (1) ;
|
; RA[13] ; Input ; (1) ;
|
||||||
; nRES ; Input ; (1) ;
|
|
||||||
; MISO ; Input ; (1) ;
|
; MISO ; Input ; (1) ;
|
||||||
|
; SetFW[0] ; Input ; (1) ;
|
||||||
+----------+----------+---------------+
|
+----------+----------+---------------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Control Signals ;
|
; Control Signals ;
|
||||||
+-----------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
|
+------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
|
||||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||||
+-----------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
|
+------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
|
||||||
; C25M ; PIN_64 ; 103 ; Clock ; yes ; Global Clock ; GCLK3 ;
|
; C25M ; PIN_64 ; 99 ; Clock ; yes ; Global Clock ; GCLK3 ;
|
||||||
; Equal1~0 ; LC_X7_Y3_N5 ; 19 ; Clock enable ; no ; -- ; -- ;
|
; Equal0~0 ; LC_X3_Y2_N7 ; 20 ; Clock enable ; no ; -- ; -- ;
|
||||||
; Equal22~1 ; LC_X6_Y4_N6 ; 8 ; Clock enable ; no ; -- ; -- ;
|
; Equal17~0 ; LC_X6_Y2_N9 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||||
; MOSIOE ; LC_X4_Y1_N9 ; 1 ; Output enable ; no ; -- ; -- ;
|
; FCKOE ; LC_X2_Y2_N6 ; 2 ; Output enable ; no ; -- ; -- ;
|
||||||
; PHI0 ; PIN_41 ; 15 ; Clock ; yes ; Global Clock ; GCLK2 ;
|
; IOROMRES~3 ; LC_X3_Y4_N5 ; 1 ; Async. clear ; no ; -- ; -- ;
|
||||||
; PS[0] ; LC_X6_Y4_N5 ; 52 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ;
|
; MOSIOE ; LC_X2_Y2_N3 ; 1 ; Output enable ; no ; -- ; -- ;
|
||||||
; PS[2] ; LC_X7_Y3_N1 ; 29 ; Sync. clear, Sync. load ; no ; -- ; -- ;
|
; PHI0 ; PIN_41 ; 3 ; Clock ; no ; -- ; -- ;
|
||||||
; SDOE ; LC_X7_Y1_N5 ; 8 ; Output enable ; no ; -- ; -- ;
|
; PS[0] ; LC_X5_Y2_N9 ; 42 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ;
|
||||||
; always8~2 ; LC_X6_Y2_N5 ; 8 ; Sync. load ; no ; -- ; -- ;
|
; PS[2] ; LC_X5_Y2_N7 ; 28 ; Sync. clear, Sync. load ; no ; -- ; -- ;
|
||||||
; always8~3 ; LC_X6_Y2_N2 ; 9 ; Sync. load ; no ; -- ; -- ;
|
; SDOE ; LC_X7_Y1_N5 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||||
; always8~4 ; LC_X5_Y2_N4 ; 9 ; Sync. load ; no ; -- ; -- ;
|
; always8~1 ; LC_X6_Y4_N9 ; 8 ; Sync. load ; no ; -- ; -- ;
|
||||||
; comb~2 ; LC_X5_Y2_N1 ; 9 ; Output enable ; no ; -- ; -- ;
|
; always8~2 ; LC_X6_Y4_N5 ; 9 ; Sync. load ; no ; -- ; -- ;
|
||||||
; nRESr ; LC_X4_Y2_N9 ; 31 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK1 ;
|
; always8~3 ; LC_X6_Y3_N9 ; 9 ; Sync. load ; no ; -- ; -- ;
|
||||||
+-----------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
|
; comb~2 ; LC_X5_Y3_N4 ; 9 ; Output enable ; no ; -- ; -- ;
|
||||||
|
; nRESr ; LC_X6_Y1_N3 ; 30 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK2 ;
|
||||||
|
+------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------+
|
||||||
|
|
@ -557,9 +559,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||||
+-------+-------------+---------+----------------------+------------------+
|
+-------+-------------+---------+----------------------+------------------+
|
||||||
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
||||||
+-------+-------------+---------+----------------------+------------------+
|
+-------+-------------+---------+----------------------+------------------+
|
||||||
; C25M ; PIN_64 ; 103 ; Global Clock ; GCLK3 ;
|
; C25M ; PIN_64 ; 99 ; Global Clock ; GCLK3 ;
|
||||||
; PHI0 ; PIN_41 ; 15 ; Global Clock ; GCLK2 ;
|
; nRESr ; LC_X6_Y1_N3 ; 30 ; Global Clock ; GCLK2 ;
|
||||||
; nRESr ; LC_X4_Y2_N9 ; 31 ; Global Clock ; GCLK1 ;
|
|
||||||
+-------+-------------+---------+----------------------+------------------+
|
+-------+-------------+---------+----------------------+------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -568,20 +569,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||||
+-----------------------+--------------------+
|
+-----------------------+--------------------+
|
||||||
; Routing Resource Type ; Usage ;
|
; Routing Resource Type ; Usage ;
|
||||||
+-----------------------+--------------------+
|
+-----------------------+--------------------+
|
||||||
; C4s ; 224 / 784 ( 29 % ) ;
|
; C4s ; 223 / 784 ( 28 % ) ;
|
||||||
; Direct links ; 55 / 888 ( 6 % ) ;
|
; Direct links ; 51 / 888 ( 6 % ) ;
|
||||||
; Global clocks ; 3 / 4 ( 75 % ) ;
|
; Global clocks ; 2 / 4 ( 50 % ) ;
|
||||||
; LAB clocks ; 14 / 32 ( 44 % ) ;
|
; LAB clocks ; 8 / 32 ( 25 % ) ;
|
||||||
; LUT chains ; 32 / 216 ( 15 % ) ;
|
; LUT chains ; 27 / 216 ( 13 % ) ;
|
||||||
; Local interconnects ; 418 / 888 ( 47 % ) ;
|
; Local interconnects ; 392 / 888 ( 44 % ) ;
|
||||||
; R4s ; 228 / 704 ( 32 % ) ;
|
; R4s ; 197 / 704 ( 28 % ) ;
|
||||||
+-----------------------+--------------------+
|
+-----------------------+--------------------+
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------+
|
||||||
; LAB Logic Elements ;
|
; LAB Logic Elements ;
|
||||||
+--------------------------------------------+------------------------------+
|
+--------------------------------------------+------------------------------+
|
||||||
; Number of Logic Elements (Average = 9.83) ; Number of LABs (Total = 24) ;
|
; Number of Logic Elements (Average = 9.57) ; Number of LABs (Total = 23) ;
|
||||||
+--------------------------------------------+------------------------------+
|
+--------------------------------------------+------------------------------+
|
||||||
; 1 ; 0 ;
|
; 1 ; 0 ;
|
||||||
; 2 ; 0 ;
|
; 2 ; 0 ;
|
||||||
|
|
@ -589,67 +590,63 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||||
; 4 ; 0 ;
|
; 4 ; 0 ;
|
||||||
; 5 ; 0 ;
|
; 5 ; 0 ;
|
||||||
; 6 ; 0 ;
|
; 6 ; 0 ;
|
||||||
; 7 ; 0 ;
|
; 7 ; 1 ;
|
||||||
; 8 ; 1 ;
|
; 8 ; 3 ;
|
||||||
; 9 ; 2 ;
|
; 9 ; 1 ;
|
||||||
; 10 ; 21 ;
|
; 10 ; 18 ;
|
||||||
+--------------------------------------------+------------------------------+
|
+--------------------------------------------+------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------+
|
+-------------------------------------------------------------------+
|
||||||
; LAB-wide Signals ;
|
; LAB-wide Signals ;
|
||||||
+------------------------------------+------------------------------+
|
+------------------------------------+------------------------------+
|
||||||
; LAB-wide Signals (Average = 1.88) ; Number of LABs (Total = 24) ;
|
; LAB-wide Signals (Average = 1.74) ; Number of LABs (Total = 23) ;
|
||||||
+------------------------------------+------------------------------+
|
+------------------------------------+------------------------------+
|
||||||
; 1 Async. clear ; 5 ;
|
; 1 Async. clear ; 5 ;
|
||||||
; 1 Clock ; 20 ;
|
; 1 Clock ; 21 ;
|
||||||
; 1 Clock enable ; 5 ;
|
; 1 Clock enable ; 4 ;
|
||||||
; 1 Sync. clear ; 7 ;
|
; 1 Sync. clear ; 5 ;
|
||||||
; 1 Sync. load ; 4 ;
|
; 1 Sync. load ; 4 ;
|
||||||
; 2 Clocks ; 4 ;
|
; 2 Clocks ; 1 ;
|
||||||
+------------------------------------+------------------------------+
|
+------------------------------------+------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+-----------------------------------------------------------------------------+
|
+----------------------------------------------------------------------------+
|
||||||
; LAB Signals Sourced ;
|
; LAB Signals Sourced ;
|
||||||
+----------------------------------------------+------------------------------+
|
+---------------------------------------------+------------------------------+
|
||||||
; Number of Signals Sourced (Average = 10.63) ; Number of LABs (Total = 24) ;
|
; Number of Signals Sourced (Average = 9.78) ; Number of LABs (Total = 23) ;
|
||||||
+----------------------------------------------+------------------------------+
|
+---------------------------------------------+------------------------------+
|
||||||
; 0 ; 0 ;
|
; 0 ; 0 ;
|
||||||
; 1 ; 0 ;
|
; 1 ; 0 ;
|
||||||
; 2 ; 0 ;
|
; 2 ; 0 ;
|
||||||
; 3 ; 0 ;
|
; 3 ; 0 ;
|
||||||
; 4 ; 0 ;
|
; 4 ; 0 ;
|
||||||
; 5 ; 0 ;
|
; 5 ; 0 ;
|
||||||
; 6 ; 0 ;
|
; 6 ; 0 ;
|
||||||
; 7 ; 0 ;
|
; 7 ; 1 ;
|
||||||
; 8 ; 1 ;
|
; 8 ; 2 ;
|
||||||
; 9 ; 2 ;
|
; 9 ; 2 ;
|
||||||
; 10 ; 14 ;
|
; 10 ; 15 ;
|
||||||
; 11 ; 2 ;
|
; 11 ; 2 ;
|
||||||
; 12 ; 2 ;
|
; 12 ; 1 ;
|
||||||
; 13 ; 1 ;
|
+---------------------------------------------+------------------------------+
|
||||||
; 14 ; 1 ;
|
|
||||||
; 15 ; 0 ;
|
|
||||||
; 16 ; 1 ;
|
|
||||||
+----------------------------------------------+------------------------------+
|
|
||||||
|
|
||||||
|
|
||||||
+--------------------------------------------------------------------------------+
|
+--------------------------------------------------------------------------------+
|
||||||
; LAB Signals Sourced Out ;
|
; LAB Signals Sourced Out ;
|
||||||
+-------------------------------------------------+------------------------------+
|
+-------------------------------------------------+------------------------------+
|
||||||
; Number of Signals Sourced Out (Average = 7.21) ; Number of LABs (Total = 24) ;
|
; Number of Signals Sourced Out (Average = 7.00) ; Number of LABs (Total = 23) ;
|
||||||
+-------------------------------------------------+------------------------------+
|
+-------------------------------------------------+------------------------------+
|
||||||
; 0 ; 0 ;
|
; 0 ; 0 ;
|
||||||
; 1 ; 0 ;
|
; 1 ; 0 ;
|
||||||
; 2 ; 0 ;
|
; 2 ; 1 ;
|
||||||
; 3 ; 2 ;
|
; 3 ; 2 ;
|
||||||
; 4 ; 1 ;
|
; 4 ; 2 ;
|
||||||
; 5 ; 3 ;
|
; 5 ; 2 ;
|
||||||
; 6 ; 2 ;
|
; 6 ; 1 ;
|
||||||
; 7 ; 3 ;
|
; 7 ; 3 ;
|
||||||
; 8 ; 5 ;
|
; 8 ; 3 ;
|
||||||
; 9 ; 5 ;
|
; 9 ; 6 ;
|
||||||
; 10 ; 3 ;
|
; 10 ; 3 ;
|
||||||
+-------------------------------------------------+------------------------------+
|
+-------------------------------------------------+------------------------------+
|
||||||
|
|
||||||
|
|
@ -657,7 +654,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||||
+-----------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------+
|
||||||
; LAB Distinct Inputs ;
|
; LAB Distinct Inputs ;
|
||||||
+----------------------------------------------+------------------------------+
|
+----------------------------------------------+------------------------------+
|
||||||
; Number of Distinct Inputs (Average = 15.50) ; Number of LABs (Total = 24) ;
|
; Number of Distinct Inputs (Average = 14.87) ; Number of LABs (Total = 23) ;
|
||||||
+----------------------------------------------+------------------------------+
|
+----------------------------------------------+------------------------------+
|
||||||
; 0 ; 0 ;
|
; 0 ; 0 ;
|
||||||
; 1 ; 0 ;
|
; 1 ; 0 ;
|
||||||
|
|
@ -665,24 +662,27 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||||
; 3 ; 0 ;
|
; 3 ; 0 ;
|
||||||
; 4 ; 1 ;
|
; 4 ; 1 ;
|
||||||
; 5 ; 0 ;
|
; 5 ; 0 ;
|
||||||
; 6 ; 0 ;
|
; 6 ; 1 ;
|
||||||
; 7 ; 1 ;
|
; 7 ; 1 ;
|
||||||
; 8 ; 0 ;
|
; 8 ; 0 ;
|
||||||
; 9 ; 0 ;
|
; 9 ; 0 ;
|
||||||
; 10 ; 1 ;
|
; 10 ; 2 ;
|
||||||
; 11 ; 1 ;
|
; 11 ; 0 ;
|
||||||
; 12 ; 0 ;
|
; 12 ; 2 ;
|
||||||
; 13 ; 4 ;
|
; 13 ; 3 ;
|
||||||
; 14 ; 4 ;
|
; 14 ; 1 ;
|
||||||
; 15 ; 0 ;
|
; 15 ; 2 ;
|
||||||
; 16 ; 2 ;
|
; 16 ; 1 ;
|
||||||
; 17 ; 2 ;
|
; 17 ; 2 ;
|
||||||
; 18 ; 0 ;
|
; 18 ; 1 ;
|
||||||
; 19 ; 2 ;
|
; 19 ; 1 ;
|
||||||
; 20 ; 2 ;
|
; 20 ; 2 ;
|
||||||
; 21 ; 1 ;
|
; 21 ; 0 ;
|
||||||
; 22 ; 2 ;
|
; 22 ; 1 ;
|
||||||
; 23 ; 1 ;
|
; 23 ; 1 ;
|
||||||
|
; 24 ; 0 ;
|
||||||
|
; 25 ; 0 ;
|
||||||
|
; 26 ; 1 ;
|
||||||
+----------------------------------------------+------------------------------+
|
+----------------------------------------------+------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -725,13 +725,8 @@ Info (332111): Found 2 clocks
|
||||||
Info (332111): 978.000 PHI0
|
Info (332111): 978.000 PHI0
|
||||||
Info (186079): Completed User Assigned Global Signals Promotion Operation
|
Info (186079): Completed User Assigned Global Signals Promotion Operation
|
||||||
Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
|
Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
|
||||||
Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
|
Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 14
|
||||||
Info (186217): Destination "comb~0" may be non-global or may not use global clock
|
Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 69
|
||||||
Info (186217): Destination "PHI0r1" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 10
|
|
||||||
Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
|
|
||||||
Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 16
|
|
||||||
Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 88
|
|
||||||
Info (186217): Destination "RestoreDone~0" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 150
|
|
||||||
Info (186079): Completed Auto Global Promotion Operation
|
Info (186079): Completed Auto Global Promotion Operation
|
||||||
Info (176234): Starting register packing
|
Info (176234): Starting register packing
|
||||||
Info (186468): Started processing fast register assignments
|
Info (186468): Started processing fast register assignments
|
||||||
|
|
@ -745,16 +740,16 @@ Info (170191): Fitter placement operations beginning
|
||||||
Info (170137): Fitter placement was successful
|
Info (170137): Fitter placement was successful
|
||||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
|
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
|
||||||
Info (170193): Fitter routing operations beginning
|
Info (170193): Fitter routing operations beginning
|
||||||
Info (170195): Router estimated average interconnect usage is 31% of the available device resources
|
Info (170195): Router estimated average interconnect usage is 30% of the available device resources
|
||||||
Info (170196): Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
Info (170196): Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.31 seconds.
|
Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds.
|
||||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||||
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
|
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
|
||||||
Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
|
Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
|
||||||
Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings
|
Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings
|
||||||
Info: Peak virtual memory: 13733 megabytes
|
Info: Peak virtual memory: 13732 megabytes
|
||||||
Info: Processing ended: Tue Mar 28 05:06:35 2023
|
Info: Processing ended: Fri Apr 14 00:01:38 2023
|
||||||
Info: Elapsed time: 00:00:03
|
Info: Elapsed time: 00:00:03
|
||||||
Info: Total CPU time (on all processors): 00:00:04
|
Info: Total CPU time (on all processors): 00:00:04
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,11 @@
|
||||||
Fitter Status : Successful - Tue Mar 28 05:06:35 2023
|
Fitter Status : Successful - Fri Apr 14 00:01:38 2023
|
||||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Revision Name : GR8RAM
|
Revision Name : GR8RAM
|
||||||
Top-level Entity Name : GR8RAM
|
Top-level Entity Name : GR8RAM
|
||||||
Family : MAX II
|
Family : MAX II
|
||||||
Device : EPM240T100C5
|
Device : EPM240T100C5
|
||||||
Timing Models : Final
|
Timing Models : Final
|
||||||
Total logic elements : 236 / 240 ( 98 % )
|
Total logic elements : 220 / 240 ( 92 % )
|
||||||
Total pins : 80 / 80 ( 100 % )
|
Total pins : 80 / 80 ( 100 % )
|
||||||
Total virtual pins : 0
|
Total virtual pins : 0
|
||||||
UFM blocks : 0 / 1 ( 0 % )
|
UFM blocks : 0 / 1 ( 0 % )
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
Flow report for GR8RAM
|
Flow report for GR8RAM
|
||||||
Tue Mar 28 05:06:39 2023
|
Fri Apr 14 00:01:43 2023
|
||||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -41,14 +41,14 @@ https://fpgasoftware.intel.com/eula.
|
||||||
+---------------------------------------------------------------------+
|
+---------------------------------------------------------------------+
|
||||||
; Flow Summary ;
|
; Flow Summary ;
|
||||||
+-----------------------+---------------------------------------------+
|
+-----------------------+---------------------------------------------+
|
||||||
; Flow Status ; Successful - Tue Mar 28 05:06:37 2023 ;
|
; Flow Status ; Successful - Fri Apr 14 00:01:40 2023 ;
|
||||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX II ;
|
; Family ; MAX II ;
|
||||||
; Device ; EPM240T100C5 ;
|
; Device ; EPM240T100C5 ;
|
||||||
; Timing Models ; Final ;
|
; Timing Models ; Final ;
|
||||||
; Total logic elements ; 236 / 240 ( 98 % ) ;
|
; Total logic elements ; 220 / 240 ( 92 % ) ;
|
||||||
; Total pins ; 80 / 80 ( 100 % ) ;
|
; Total pins ; 80 / 80 ( 100 % ) ;
|
||||||
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
||||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||||
|
|
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
; Option ; Setting ;
|
; Option ; Setting ;
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
; Start date & time ; 03/28/2023 05:06:13 ;
|
; Start date & time ; 04/14/2023 00:01:17 ;
|
||||||
; Main task ; Compilation ;
|
; Main task ; Compilation ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
|
|
@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
|
||||||
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
|
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
|
||||||
; AUTO_PACKED_REGISTERS_MAX ; Minimize Area ; Auto ; -- ; -- ;
|
; AUTO_PACKED_REGISTERS_MAX ; Minimize Area ; Auto ; -- ; -- ;
|
||||||
; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
|
; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
|
||||||
; COMPILER_SIGNATURE_ID ; 121381084694.167999437303928 ; -- ; -- ; -- ;
|
; COMPILER_SIGNATURE_ID ; 121381084694.168144487708968 ; -- ; -- ; -- ;
|
||||||
; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
|
; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
|
||||||
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
|
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
|
||||||
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ;
|
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ;
|
||||||
|
|
@ -103,11 +103,11 @@ https://fpgasoftware.intel.com/eula.
|
||||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
; Analysis & Synthesis ; 00:00:18 ; 1.0 ; 13094 MB ; 00:00:39 ;
|
; Analysis & Synthesis ; 00:00:18 ; 1.0 ; 13092 MB ; 00:00:39 ;
|
||||||
; Fitter ; 00:00:03 ; 1.0 ; 13733 MB ; 00:00:04 ;
|
; Fitter ; 00:00:03 ; 1.0 ; 13732 MB ; 00:00:04 ;
|
||||||
; Assembler ; 00:00:01 ; 1.0 ; 13053 MB ; 00:00:01 ;
|
; Assembler ; 00:00:01 ; 1.0 ; 13052 MB ; 00:00:01 ;
|
||||||
; Timing Analyzer ; 00:00:01 ; 1.0 ; 13052 MB ; 00:00:01 ;
|
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13051 MB ; 00:00:01 ;
|
||||||
; Total ; 00:00:23 ; -- ; -- ; 00:00:45 ;
|
; Total ; 00:00:24 ; -- ; -- ; 00:00:45 ;
|
||||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
Analysis & Synthesis report for GR8RAM
|
Analysis & Synthesis report for GR8RAM
|
||||||
Tue Mar 28 05:06:31 2023
|
Fri Apr 14 00:01:34 2023
|
||||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -46,12 +46,12 @@ https://fpgasoftware.intel.com/eula.
|
||||||
+---------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Summary ;
|
; Analysis & Synthesis Summary ;
|
||||||
+-----------------------------+---------------------------------------------+
|
+-----------------------------+---------------------------------------------+
|
||||||
; Analysis & Synthesis Status ; Successful - Tue Mar 28 05:06:31 2023 ;
|
; Analysis & Synthesis Status ; Successful - Fri Apr 14 00:01:34 2023 ;
|
||||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX II ;
|
; Family ; MAX II ;
|
||||||
; Total logic elements ; 256 ;
|
; Total logic elements ; 225 ;
|
||||||
; Total pins ; 80 ;
|
; Total pins ; 80 ;
|
||||||
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
||||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||||
|
|
@ -159,33 +159,33 @@ https://fpgasoftware.intel.com/eula.
|
||||||
+---------------------------------------------+-------+
|
+---------------------------------------------+-------+
|
||||||
; Resource ; Usage ;
|
; Resource ; Usage ;
|
||||||
+---------------------------------------------+-------+
|
+---------------------------------------------+-------+
|
||||||
; Total logic elements ; 256 ;
|
; Total logic elements ; 225 ;
|
||||||
; -- Combinational with no register ; 139 ;
|
; -- Combinational with no register ; 125 ;
|
||||||
; -- Register only ; 21 ;
|
; -- Register only ; 6 ;
|
||||||
; -- Combinational with a register ; 96 ;
|
; -- Combinational with a register ; 94 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Logic element usage by number of LUT inputs ; ;
|
; Logic element usage by number of LUT inputs ; ;
|
||||||
; -- 4 input functions ; 137 ;
|
; -- 4 input functions ; 120 ;
|
||||||
; -- 3 input functions ; 35 ;
|
; -- 3 input functions ; 32 ;
|
||||||
; -- 2 input functions ; 63 ;
|
; -- 2 input functions ; 66 ;
|
||||||
; -- 1 input functions ; 0 ;
|
; -- 1 input functions ; 1 ;
|
||||||
; -- 0 input functions ; 0 ;
|
; -- 0 input functions ; 0 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Logic elements by mode ; ;
|
; Logic elements by mode ; ;
|
||||||
; -- normal mode ; 223 ;
|
; -- normal mode ; 192 ;
|
||||||
; -- arithmetic mode ; 33 ;
|
; -- arithmetic mode ; 33 ;
|
||||||
; -- qfbk mode ; 0 ;
|
; -- qfbk mode ; 0 ;
|
||||||
; -- register cascade mode ; 0 ;
|
; -- register cascade mode ; 0 ;
|
||||||
; -- synchronous clear/load mode ; 44 ;
|
; -- synchronous clear/load mode ; 45 ;
|
||||||
; -- asynchronous clear/load mode ; 29 ;
|
; -- asynchronous clear/load mode ; 30 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Total registers ; 117 ;
|
; Total registers ; 100 ;
|
||||||
; Total logic cells in carry chains ; 37 ;
|
; Total logic cells in carry chains ; 37 ;
|
||||||
; I/O pins ; 80 ;
|
; I/O pins ; 80 ;
|
||||||
; Maximum fan-out node ; C25M ;
|
; Maximum fan-out node ; C25M ;
|
||||||
; Maximum fan-out ; 103 ;
|
; Maximum fan-out ; 99 ;
|
||||||
; Total fan-out ; 1104 ;
|
; Total fan-out ; 1009 ;
|
||||||
; Average fan-out ; 3.29 ;
|
; Average fan-out ; 3.31 ;
|
||||||
+---------------------------------------------+-------+
|
+---------------------------------------------+-------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -194,7 +194,7 @@ https://fpgasoftware.intel.com/eula.
|
||||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
||||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
||||||
; |GR8RAM ; 256 (256) ; 117 ; 0 ; 80 ; 0 ; 139 (139) ; 21 (21) ; 96 (96) ; 37 (37) ; 0 (0) ; |GR8RAM ; GR8RAM ; work ;
|
; |GR8RAM ; 225 (225) ; 100 ; 0 ; 80 ; 0 ; 125 (125) ; 6 (6) ; 94 (94) ; 37 (37) ; 0 (0) ; |GR8RAM ; GR8RAM ; work ;
|
||||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
||||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||||
|
|
||||||
|
|
@ -214,15 +214,14 @@ Encoding Type: Minimal Bits
|
||||||
+--------+----------------+----------------+----------------+
|
+--------+----------------+----------------+----------------+
|
||||||
|
|
||||||
|
|
||||||
+--------------------------------------------------------------------------------+
|
+------------------------------------------------------------+
|
||||||
; Registers Removed During Synthesis ;
|
; Registers Removed During Synthesis ;
|
||||||
+---------------------------------------+----------------------------------------+
|
+---------------------------------------+--------------------+
|
||||||
; Register name ; Reason for Removal ;
|
; Register name ; Reason for Removal ;
|
||||||
+---------------------------------------+----------------------------------------+
|
+---------------------------------------+--------------------+
|
||||||
; SBA[0]~reg0 ; Stuck at GND due to stuck port data_in ;
|
; IS~10 ; Lost fanout ;
|
||||||
; IS~10 ; Lost fanout ;
|
; Total Number of Removed Registers = 1 ; ;
|
||||||
; Total Number of Removed Registers = 2 ; ;
|
+---------------------------------------+--------------------+
|
||||||
+---------------------------------------+----------------------------------------+
|
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------+
|
+------------------------------------------------------+
|
||||||
|
|
@ -230,12 +229,12 @@ Encoding Type: Minimal Bits
|
||||||
+----------------------------------------------+-------+
|
+----------------------------------------------+-------+
|
||||||
; Statistic ; Value ;
|
; Statistic ; Value ;
|
||||||
+----------------------------------------------+-------+
|
+----------------------------------------------+-------+
|
||||||
; Total registers ; 117 ;
|
; Total registers ; 100 ;
|
||||||
; Number of registers using Synchronous Clear ; 11 ;
|
; Number of registers using Synchronous Clear ; 12 ;
|
||||||
; Number of registers using Synchronous Load ; 33 ;
|
; Number of registers using Synchronous Load ; 33 ;
|
||||||
; Number of registers using Asynchronous Clear ; 29 ;
|
; Number of registers using Asynchronous Clear ; 30 ;
|
||||||
; Number of registers using Asynchronous Load ; 0 ;
|
; Number of registers using Asynchronous Load ; 0 ;
|
||||||
; Number of registers using Clock Enable ; 22 ;
|
; Number of registers using Clock Enable ; 24 ;
|
||||||
; Number of registers using Preset ; 0 ;
|
; Number of registers using Preset ; 0 ;
|
||||||
+----------------------------------------------+-------+
|
+----------------------------------------------+-------+
|
||||||
|
|
||||||
|
|
@ -251,9 +250,8 @@ Encoding Type: Minimal Bits
|
||||||
; nSWE~reg0 ; 1 ;
|
; nSWE~reg0 ; 1 ;
|
||||||
; DQML~reg0 ; 1 ;
|
; DQML~reg0 ; 1 ;
|
||||||
; DQMH~reg0 ; 1 ;
|
; DQMH~reg0 ; 1 ;
|
||||||
; RCKE~reg0 ; 1 ;
|
; RCKE~reg0 ; 4 ;
|
||||||
; nFCS~reg0 ; 1 ;
|
; Total number of inverted registers = 7 ; ;
|
||||||
; Total number of inverted registers = 8 ; ;
|
|
||||||
+----------------------------------------+---------+
|
+----------------------------------------+---------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -262,13 +260,14 @@ Encoding Type: Minimal Bits
|
||||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||||
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ;
|
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[1] ;
|
||||||
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |GR8RAM|SA[9]~reg0 ;
|
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ;
|
||||||
; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[8]~reg0 ;
|
; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[6]~reg0 ;
|
||||||
; 20:1 ; 2 bits ; 26 LEs ; 12 LEs ; 14 LEs ; Yes ; |GR8RAM|SA[1]~reg0 ;
|
; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[2]~reg0 ;
|
||||||
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[0] ;
|
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[5] ;
|
||||||
; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |GR8RAM|RDD[0] ;
|
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |GR8RAM|RDD[2] ;
|
||||||
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
|
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQML~reg0 ;
|
||||||
|
; 18:1 ; 4 bits ; 48 LEs ; 8 LEs ; 40 LEs ; Yes ; |GR8RAM|RDD[6] ;
|
||||||
; 7:1 ; 5 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |GR8RAM|IS ;
|
; 7:1 ; 5 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |GR8RAM|IS ;
|
||||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||||
|
|
||||||
|
|
@ -279,41 +278,37 @@ Encoding Type: Minimal Bits
|
||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus Prime Analysis & Synthesis
|
Info: Running Quartus Prime Analysis & Synthesis
|
||||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Info: Processing started: Tue Mar 28 05:06:13 2023
|
Info: Processing started: Fri Apr 14 00:01:16 2023
|
||||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||||
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
||||||
Info (12023): Found entity 1: GR8RAM File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 1
|
Info (12023): Found entity 1: GR8RAM File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 1
|
||||||
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (4) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 34
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(31): truncated value with size 32 to match size of target (4) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 31
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(39): truncated value with size 32 to match size of target (14) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 39
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(36): truncated value with size 32 to match size of target (14) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 36
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 128
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(109): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 109
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(136): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 136
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 117
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(143): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 143
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(124): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 124
|
||||||
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
|
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
|
||||||
Warning (13024): Output pins are stuck at VCC or GND
|
Warning (13024): Output pins are stuck at VCC or GND
|
||||||
Warning (13410): Pin "nNMIout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 559
|
Warning (13410): Pin "nNMIout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 541
|
||||||
Warning (13410): Pin "nIRQout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 562
|
Warning (13410): Pin "nIRQout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 544
|
||||||
Warning (13410): Pin "nRDYout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 561
|
Warning (13410): Pin "nRDYout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 543
|
||||||
Warning (13410): Pin "nINHout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 560
|
Warning (13410): Pin "nINHout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 542
|
||||||
Warning (13410): Pin "RWout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 563
|
Warning (13410): Pin "RWout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 545
|
||||||
Warning (13410): Pin "nDMAout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 558
|
Warning (13410): Pin "nDMAout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 540
|
||||||
Warning (13410): Pin "RAdir" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 557
|
Warning (13410): Pin "RAdir" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 539
|
||||||
Warning (13410): Pin "SBA[0]" is stuck at GND File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 442
|
|
||||||
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
|
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
|
||||||
Warning (21074): Design contains 2 input pin(s) that do not drive logic
|
Info (21057): Implemented 305 device resources after synthesis - the final resource count might be different
|
||||||
Warning (15610): No output dependent on input pin "SetFW[0]" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 23
|
|
||||||
Warning (15610): No output dependent on input pin "SetFW[1]" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 23
|
|
||||||
Info (21057): Implemented 336 device resources after synthesis - the final resource count might be different
|
|
||||||
Info (21058): Implemented 28 input pins
|
Info (21058): Implemented 28 input pins
|
||||||
Info (21059): Implemented 35 output pins
|
Info (21059): Implemented 35 output pins
|
||||||
Info (21060): Implemented 17 bidirectional pins
|
Info (21060): Implemented 17 bidirectional pins
|
||||||
Info (21061): Implemented 256 logic cells
|
Info (21061): Implemented 225 logic cells
|
||||||
Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
||||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings
|
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings
|
||||||
Info: Peak virtual memory: 13094 megabytes
|
Info: Peak virtual memory: 13092 megabytes
|
||||||
Info: Processing ended: Tue Mar 28 05:06:31 2023
|
Info: Processing ended: Fri Apr 14 00:01:34 2023
|
||||||
Info: Elapsed time: 00:00:18
|
Info: Elapsed time: 00:00:18
|
||||||
Info: Total CPU time (on all processors): 00:00:39
|
Info: Total CPU time (on all processors): 00:00:39
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,2 +1,2 @@
|
||||||
Warning (10273): Verilog HDL warning at GR8RAM.v(104): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 104
|
Warning (10273): Verilog HDL warning at GR8RAM.v(85): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 85
|
||||||
Warning (10273): Verilog HDL warning at GR8RAM.v(281): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 281
|
Warning (10273): Verilog HDL warning at GR8RAM.v(261): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 261
|
||||||
|
|
|
||||||
|
|
@ -1,9 +1,9 @@
|
||||||
Analysis & Synthesis Status : Successful - Tue Mar 28 05:06:31 2023
|
Analysis & Synthesis Status : Successful - Fri Apr 14 00:01:34 2023
|
||||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Revision Name : GR8RAM
|
Revision Name : GR8RAM
|
||||||
Top-level Entity Name : GR8RAM
|
Top-level Entity Name : GR8RAM
|
||||||
Family : MAX II
|
Family : MAX II
|
||||||
Total logic elements : 256
|
Total logic elements : 225
|
||||||
Total pins : 80
|
Total pins : 80
|
||||||
Total virtual pins : 0
|
Total virtual pins : 0
|
||||||
UFM blocks : 0 / 1 ( 0 % )
|
UFM blocks : 0 / 1 ( 0 % )
|
||||||
|
|
|
||||||
Binary file not shown.
|
|
@ -1,5 +1,5 @@
|
||||||
Timing Analyzer report for GR8RAM
|
Timing Analyzer report for GR8RAM
|
||||||
Tue Mar 28 05:06:39 2023
|
Fri Apr 14 00:01:43 2023
|
||||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -84,7 +84,7 @@ https://fpgasoftware.intel.com/eula.
|
||||||
; ; ;
|
; ; ;
|
||||||
; Usage by Processor ; % Time Used ;
|
; Usage by Processor ; % Time Used ;
|
||||||
; Processor 1 ; 100.0% ;
|
; Processor 1 ; 100.0% ;
|
||||||
; Processor 2 ; 0.2% ;
|
; Processor 2 ; 0.0% ;
|
||||||
+----------------------------+-------------+
|
+----------------------------+-------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -93,7 +93,7 @@ https://fpgasoftware.intel.com/eula.
|
||||||
+---------------+--------+--------------------------+
|
+---------------+--------+--------------------------+
|
||||||
; SDC File Path ; Status ; Read at ;
|
; SDC File Path ; Status ; Read at ;
|
||||||
+---------------+--------+--------------------------+
|
+---------------+--------+--------------------------+
|
||||||
; GR8RAM.sdc ; OK ; Tue Mar 28 05:06:39 2023 ;
|
; GR8RAM.sdc ; OK ; Fri Apr 14 00:01:43 2023 ;
|
||||||
+---------------+--------+--------------------------+
|
+---------------+--------+--------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -112,7 +112,7 @@ https://fpgasoftware.intel.com/eula.
|
||||||
+-----------+-----------------+------------+------+
|
+-----------+-----------------+------------+------+
|
||||||
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||||||
+-----------+-----------------+------------+------+
|
+-----------+-----------------+------------+------+
|
||||||
; 66.42 MHz ; 66.42 MHz ; C25M ; ;
|
; 86.99 MHz ; 86.99 MHz ; C25M ; ;
|
||||||
+-----------+-----------------+------------+------+
|
+-----------+-----------------+------------+------+
|
||||||
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||||||
|
|
||||||
|
|
@ -122,7 +122,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||||
+-------+--------+---------------+
|
+-------+--------+---------------+
|
||||||
; Clock ; Slack ; End Point TNS ;
|
; Clock ; Slack ; End Point TNS ;
|
||||||
+-------+--------+---------------+
|
+-------+--------+---------------+
|
||||||
; C25M ; 12.472 ; 0.000 ;
|
; C25M ; 14.252 ; 0.000 ;
|
||||||
+-------+--------+---------------+
|
+-------+--------+---------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -131,7 +131,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||||
+-------+-------+---------------+
|
+-------+-------+---------------+
|
||||||
; Clock ; Slack ; End Point TNS ;
|
; Clock ; Slack ; End Point TNS ;
|
||||||
+-------+-------+---------------+
|
+-------+-------+---------------+
|
||||||
; C25M ; 1.383 ; 0.000 ;
|
; C25M ; 1.394 ; 0.000 ;
|
||||||
+-------+-------+---------------+
|
+-------+-------+---------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -140,7 +140,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||||
+-------+--------+---------------+
|
+-------+--------+---------------+
|
||||||
; Clock ; Slack ; End Point TNS ;
|
; Clock ; Slack ; End Point TNS ;
|
||||||
+-------+--------+---------------+
|
+-------+--------+---------------+
|
||||||
; C25M ; 33.331 ; 0.000 ;
|
; C25M ; 33.179 ; 0.000 ;
|
||||||
+-------+--------+---------------+
|
+-------+--------+---------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -149,7 +149,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||||
+-------+-------+---------------+
|
+-------+-------+---------------+
|
||||||
; Clock ; Slack ; End Point TNS ;
|
; Clock ; Slack ; End Point TNS ;
|
||||||
+-------+-------+---------------+
|
+-------+-------+---------------+
|
||||||
; C25M ; 6.115 ; 0.000 ;
|
; C25M ; 6.267 ; 0.000 ;
|
||||||
+-------+-------+---------------+
|
+-------+-------+---------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -168,106 +168,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||||
+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
||||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||||
+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
||||||
; 12.472 ; REGEN ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.195 ;
|
; 14.252 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.415 ;
|
||||||
; 12.473 ; REGEN ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.194 ;
|
; 14.252 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.415 ;
|
||||||
; 12.485 ; REGEN ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.182 ;
|
; 14.252 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.415 ;
|
||||||
; 12.571 ; REGEN ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.096 ;
|
; 14.272 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.395 ;
|
||||||
; 12.858 ; REGEN ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.809 ;
|
; 14.272 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.395 ;
|
||||||
; 12.946 ; REGEN ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.721 ;
|
; 14.272 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.395 ;
|
||||||
; 12.947 ; REGEN ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.720 ;
|
; 14.313 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.354 ;
|
||||||
; 13.462 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.205 ;
|
; 14.640 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.027 ;
|
||||||
; 13.543 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.124 ;
|
; 14.640 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.027 ;
|
||||||
; 13.543 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.124 ;
|
; 14.640 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.027 ;
|
||||||
; 13.543 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.124 ;
|
; 14.716 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.951 ;
|
||||||
; 13.649 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.018 ;
|
; 14.716 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.951 ;
|
||||||
; 13.668 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.999 ;
|
; 14.716 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.951 ;
|
||||||
; 13.730 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.937 ;
|
; 14.716 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.951 ;
|
||||||
; 13.730 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.937 ;
|
; 14.716 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.951 ;
|
||||||
; 13.730 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.937 ;
|
; 14.718 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.949 ;
|
||||||
; 13.825 ; REGEN ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.842 ;
|
; 14.736 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.931 ;
|
||||||
; 13.979 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.688 ;
|
; 14.736 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.931 ;
|
||||||
; 14.060 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.607 ;
|
; 14.736 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.931 ;
|
||||||
; 14.060 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.607 ;
|
; 14.736 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.931 ;
|
||||||
; 14.060 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.607 ;
|
; 14.736 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.931 ;
|
||||||
; 14.184 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.483 ;
|
; 14.746 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.921 ;
|
||||||
; 14.184 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.483 ;
|
; 14.746 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.921 ;
|
||||||
; 14.184 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.483 ;
|
; 14.746 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.921 ;
|
||||||
; 14.210 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.457 ;
|
; 14.758 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.909 ;
|
||||||
; 14.328 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.339 ;
|
; 14.841 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.826 ;
|
||||||
; 14.366 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.301 ;
|
; 14.881 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.786 ;
|
||||||
; 14.371 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.296 ;
|
; 14.993 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.674 ;
|
||||||
; 14.371 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.296 ;
|
; 15.104 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.563 ;
|
||||||
; 14.371 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.296 ;
|
; 15.104 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.563 ;
|
||||||
; 14.390 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.277 ;
|
; 15.104 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.563 ;
|
||||||
; 14.409 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.258 ;
|
; 15.104 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.563 ;
|
||||||
; 14.409 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.258 ;
|
; 15.104 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.563 ;
|
||||||
; 14.409 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.258 ;
|
; 15.210 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.457 ;
|
||||||
; 14.445 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.222 ;
|
; 15.210 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.457 ;
|
||||||
; 14.496 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.171 ;
|
; 15.210 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.457 ;
|
||||||
; 14.622 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.045 ;
|
; 15.210 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.457 ;
|
||||||
; 14.701 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.966 ;
|
; 15.210 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.457 ;
|
||||||
; 14.701 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.966 ;
|
; 15.303 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.364 ;
|
||||||
; 14.701 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.966 ;
|
; 15.404 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.263 ;
|
||||||
; 14.707 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.960 ;
|
; 15.629 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.038 ;
|
||||||
; 14.709 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.958 ;
|
; 15.669 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.998 ;
|
||||||
; 14.809 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.858 ;
|
; 15.686 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.981 ;
|
||||||
; 15.050 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.617 ;
|
; 15.695 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.972 ;
|
||||||
; 15.050 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.617 ;
|
; 15.762 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.905 ;
|
||||||
; 15.050 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.617 ;
|
; 15.840 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.827 ;
|
||||||
; 15.061 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.606 ;
|
; 15.967 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.700 ;
|
||||||
; 15.128 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.539 ;
|
; 16.041 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.626 ;
|
||||||
; 15.139 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.528 ;
|
; 16.139 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.528 ;
|
||||||
; 15.199 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.468 ;
|
; 16.203 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.464 ;
|
||||||
; 15.284 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.383 ;
|
; 16.253 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.414 ;
|
||||||
; 15.322 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.345 ;
|
; 16.354 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.313 ;
|
||||||
; 15.488 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.179 ;
|
; 16.389 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.278 ;
|
||||||
; 15.722 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.945 ;
|
; 16.467 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.200 ;
|
||||||
; 16.006 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.661 ;
|
; 16.527 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.140 ;
|
||||||
; 16.012 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.655 ;
|
; 16.563 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.104 ;
|
||||||
; 16.089 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.578 ;
|
; 28.556 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.111 ;
|
||||||
; 16.110 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.557 ;
|
; 28.715 ; LS[9] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.952 ;
|
||||||
; 16.112 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.555 ;
|
; 28.895 ; LS[11] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.772 ;
|
||||||
; 16.133 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.534 ;
|
; 28.900 ; LS[10] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.767 ;
|
||||||
; 16.142 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.525 ;
|
; 29.059 ; LS[9] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.608 ;
|
||||||
; 16.144 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.523 ;
|
; 29.239 ; LS[11] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.428 ;
|
||||||
; 16.144 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.523 ;
|
; 29.252 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.415 ;
|
||||||
; 16.300 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.367 ;
|
; 29.535 ; PS[3] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.132 ;
|
||||||
; 27.034 ; IS.state_bit_0 ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.633 ;
|
; 29.596 ; LS[8] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.071 ;
|
||||||
; 27.416 ; IS.state_bit_0 ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.251 ;
|
; 29.602 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.065 ;
|
||||||
; 27.568 ; Addr[23] ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.099 ;
|
; 29.687 ; PS[1] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.980 ;
|
||||||
; 27.654 ; REGEN ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.013 ;
|
; 29.698 ; IS.state_bit_1 ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.969 ;
|
||||||
; 27.717 ; Addr[23] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.950 ;
|
; 29.729 ; LS[7] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.938 ;
|
||||||
; 27.803 ; REGEN ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.864 ;
|
; 29.734 ; LS[3] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.933 ;
|
||||||
; 27.841 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.826 ;
|
; 29.770 ; PS[1] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.897 ;
|
||||||
; 28.219 ; Addr[23] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.448 ;
|
; 29.811 ; PS[3] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.856 ;
|
||||||
; 28.223 ; IS.state_bit_1 ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.444 ;
|
; 29.837 ; PS[1] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ;
|
||||||
; 28.238 ; LS[1] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.429 ;
|
; 29.837 ; PS[1] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ;
|
||||||
; 28.251 ; Addr[23] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.416 ;
|
; 29.837 ; PS[1] ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ;
|
||||||
; 28.266 ; Addr[23] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.401 ;
|
; 29.837 ; PS[1] ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ;
|
||||||
; 28.305 ; REGEN ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.362 ;
|
; 29.837 ; PS[1] ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ;
|
||||||
; 28.337 ; REGEN ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.330 ;
|
; 29.837 ; PS[1] ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ;
|
||||||
; 28.352 ; REGEN ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.315 ;
|
; 29.837 ; PS[1] ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ;
|
||||||
; 28.419 ; IS.state_bit_0 ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.248 ;
|
; 29.837 ; PS[1] ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ;
|
||||||
; 28.423 ; IS.state_bit_0 ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.244 ;
|
; 29.841 ; PS[0] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.826 ;
|
||||||
; 28.431 ; LS[7] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.236 ;
|
; 29.878 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.789 ;
|
||||||
; 28.447 ; LS[10] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.220 ;
|
; 29.892 ; PS[0] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.775 ;
|
||||||
; 28.462 ; LS[3] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.205 ;
|
; 29.926 ; LS[6] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.741 ;
|
||||||
; 28.464 ; LS[1] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.203 ;
|
; 29.942 ; LS[10] ; IS.state_bit_2 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.725 ;
|
||||||
; 28.566 ; Addr[23] ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.101 ;
|
; 30.003 ; IS.state_bit_0 ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.664 ;
|
||||||
; 28.594 ; LS[9] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.073 ;
|
; 30.027 ; PS[3] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.640 ;
|
||||||
; 28.605 ; Addr[23] ; nRCS~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.062 ;
|
; 30.030 ; PS[3] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.637 ;
|
||||||
; 28.611 ; Addr[23] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.056 ;
|
; 30.058 ; LS[12] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.609 ;
|
||||||
; 28.652 ; REGEN ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.015 ;
|
; 30.073 ; LS[7] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.594 ;
|
||||||
; 28.657 ; LS[7] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.010 ;
|
; 30.078 ; LS[3] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.589 ;
|
||||||
; 28.673 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.994 ;
|
; 30.094 ; IS.state_bit_1 ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.573 ;
|
||||||
; 28.688 ; LS[3] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.979 ;
|
; 30.097 ; IS.state_bit_1 ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.570 ;
|
||||||
; 28.691 ; REGEN ; nRCS~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.976 ;
|
; 30.099 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.568 ;
|
||||||
; 28.696 ; Addr[23] ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.971 ;
|
; 30.100 ; LS[1] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.567 ;
|
||||||
; 28.697 ; REGEN ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.970 ;
|
; 30.101 ; LS[9] ; IS.state_bit_2 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.566 ;
|
||||||
; 28.720 ; Addr[23] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.947 ;
|
; 30.102 ; PS[0] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.565 ;
|
||||||
; 28.782 ; REGEN ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.885 ;
|
; 30.168 ; PS[0] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.499 ;
|
||||||
; 28.784 ; LS[11] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.883 ;
|
; 30.226 ; PS[3] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.441 ;
|
||||||
; 28.806 ; REGEN ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.861 ;
|
; 30.249 ; PS[1] ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.418 ;
|
||||||
+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -276,106 +276,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||||
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
||||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||||
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
||||||
; 1.383 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.604 ;
|
; 1.394 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.615 ;
|
||||||
; 1.384 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.605 ;
|
; 1.403 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.624 ;
|
||||||
; 1.396 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.617 ;
|
; 1.410 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.631 ;
|
||||||
; 1.412 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ;
|
; 1.411 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.632 ;
|
||||||
; 1.422 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.643 ;
|
; 1.420 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ;
|
||||||
; 1.652 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.873 ;
|
; 1.640 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.861 ;
|
||||||
; 1.654 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.875 ;
|
; 1.695 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 1.916 ;
|
||||||
; 1.667 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.888 ;
|
; 1.815 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.036 ;
|
||||||
; 1.667 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 1.888 ;
|
; 1.835 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.056 ;
|
||||||
; 1.779 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.000 ;
|
; 1.927 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.148 ;
|
||||||
; 1.780 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.001 ;
|
; 1.937 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.158 ;
|
||||||
; 1.785 ; PS[1] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.006 ;
|
; 1.941 ; PHI0r1 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.162 ;
|
||||||
; 1.787 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.008 ;
|
; 1.972 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.193 ;
|
||||||
; 1.825 ; nRESf[0] ; nRESf[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.046 ;
|
; 2.076 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.297 ;
|
||||||
; 1.880 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.101 ;
|
; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ;
|
||||||
; 1.920 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.141 ;
|
; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
|
||||||
; 1.937 ; RestoreDone ; RestoreDone ; C25M ; C25M ; 0.000 ; 0.000 ; 2.158 ;
|
; 2.117 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
|
||||||
; 1.942 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.163 ;
|
|
||||||
; 1.961 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.182 ;
|
|
||||||
; 1.978 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.199 ;
|
|
||||||
; 1.996 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.217 ;
|
|
||||||
; 2.049 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.270 ;
|
|
||||||
; 2.108 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.329 ;
|
|
||||||
; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
|
; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
|
||||||
; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
|
; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
|
||||||
; 2.117 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
|
; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
|
||||||
|
; 2.120 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.341 ;
|
||||||
|
; 2.122 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.343 ;
|
||||||
; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ;
|
; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ;
|
||||||
|
; 2.125 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ;
|
||||||
; 2.126 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
|
; 2.126 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
|
||||||
; 2.126 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
|
; 2.126 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
|
||||||
; 2.126 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
|
; 2.126 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
|
||||||
; 2.128 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.349 ;
|
; 2.126 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
|
||||||
; 2.129 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.350 ;
|
; 2.127 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ;
|
||||||
; 2.133 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ;
|
; 2.136 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.357 ;
|
||||||
; 2.133 ; IS.state_bit_2 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ;
|
|
||||||
; 2.134 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.355 ;
|
|
||||||
; 2.136 ; IS.state_bit_2 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.357 ;
|
|
||||||
; 2.143 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.364 ;
|
|
||||||
; 2.144 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
|
|
||||||
; 2.144 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
|
; 2.144 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
|
||||||
; 2.144 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
|
; 2.144 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
|
||||||
; 2.148 ; RestoreDone ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.369 ;
|
; 2.144 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
|
||||||
; 2.199 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.420 ;
|
; 2.147 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.368 ;
|
||||||
; 2.203 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.424 ;
|
; 2.153 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.374 ;
|
||||||
; 2.210 ; PS[2] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.431 ;
|
; 2.170 ; REGEN ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 2.391 ;
|
||||||
; 2.212 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ;
|
; 2.222 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ;
|
||||||
; 2.212 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ;
|
|
||||||
; 2.212 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ;
|
|
||||||
; 2.213 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.434 ;
|
|
||||||
; 2.214 ; IS.state_bit_0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.435 ;
|
|
||||||
; 2.221 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ;
|
|
||||||
; 2.221 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ;
|
|
||||||
; 2.221 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ;
|
|
||||||
; 2.222 ; PS[2] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ;
|
|
||||||
; 2.222 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ;
|
|
||||||
; 2.222 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ;
|
|
||||||
; 2.230 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ;
|
|
||||||
; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ;
|
; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ;
|
||||||
; 2.231 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
|
; 2.231 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
|
||||||
; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
|
|
||||||
; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
|
; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
|
||||||
; 2.234 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.455 ;
|
; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
|
||||||
; 2.237 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.458 ;
|
; 2.234 ; RCKE~reg0 ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.455 ;
|
||||||
; 2.239 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ;
|
; 2.241 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
|
||||||
; 2.240 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ;
|
; 2.241 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
|
||||||
; 2.241 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
|
; 2.246 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.467 ;
|
||||||
; 2.241 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
|
; 2.248 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ;
|
||||||
; 2.251 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ;
|
; 2.249 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
|
||||||
; 2.253 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ;
|
; 2.249 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
|
||||||
; 2.262 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ;
|
; 2.250 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ;
|
||||||
; 2.276 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.497 ;
|
; 2.250 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ;
|
||||||
; 2.283 ; PS[3] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.504 ;
|
; 2.250 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ;
|
||||||
; 2.290 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.511 ;
|
; 2.250 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ;
|
||||||
; 2.291 ; IS.state_bit_1 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.512 ;
|
; 2.251 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ;
|
||||||
; 2.313 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.534 ;
|
; 2.251 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ;
|
||||||
; 2.364 ; PS[1] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.585 ;
|
; 2.253 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ;
|
||||||
; 2.370 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.591 ;
|
; 2.254 ; PHI0r2 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.475 ;
|
||||||
; 2.448 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.669 ;
|
; 2.254 ; Addr[19] ; SA[9]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.475 ;
|
||||||
; 2.508 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.729 ;
|
; 2.261 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
|
||||||
; 2.542 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.763 ;
|
; 2.261 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
|
||||||
; 2.547 ; LS[4] ; SA[3]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.768 ;
|
; 2.261 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
|
||||||
; 2.554 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.775 ;
|
; 2.262 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ;
|
||||||
; 2.557 ; nRESf[0] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.778 ;
|
; 2.428 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.649 ;
|
||||||
; 2.582 ; PS[3] ; nRCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.803 ;
|
; 2.500 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.721 ;
|
||||||
; 2.595 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.816 ;
|
; 2.548 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.769 ;
|
||||||
; 2.638 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.859 ;
|
; 2.558 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.779 ;
|
||||||
; 2.652 ; IS.state_bit_0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.873 ;
|
; 2.569 ; IS.state_bit_0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.790 ;
|
||||||
; 2.655 ; IS.state_bit_0 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.876 ;
|
; 2.574 ; IS.state_bit_0 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 2.795 ;
|
||||||
; 2.656 ; PHI0r2 ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.877 ;
|
; 2.584 ; IS.state_bit_0 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.805 ;
|
||||||
; 2.676 ; PS[2] ; nRCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.897 ;
|
; 2.622 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.843 ;
|
||||||
; 2.719 ; LS[7] ; SA[6]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.940 ;
|
; 2.702 ; IS.state_bit_1 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.923 ;
|
||||||
; 2.720 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.941 ;
|
; 2.717 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.938 ;
|
||||||
; 2.838 ; IS.state_bit_1 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.059 ;
|
; 2.718 ; IS.state_bit_1 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 2.939 ;
|
||||||
; 2.848 ; IS.state_bit_1 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.069 ;
|
; 2.719 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.940 ;
|
||||||
; 2.928 ; Addr[14] ; SA[4]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.149 ;
|
; 2.721 ; IS.state_bit_1 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.942 ;
|
||||||
|
; 2.782 ; IS.state_bit_0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.003 ;
|
||||||
|
; 2.849 ; IS.state_bit_2 ; IS.state_bit_2 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.070 ;
|
||||||
|
; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ;
|
||||||
|
; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
|
||||||
|
; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
|
||||||
; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
|
; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
|
||||||
; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
|
; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
|
||||||
|
; 2.954 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.175 ;
|
||||||
|
; 2.955 ; IS.state_bit_2 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.176 ;
|
||||||
|
; 2.956 ; PS[1] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ;
|
||||||
; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ;
|
; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ;
|
||||||
; 2.958 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
|
; 2.957 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ;
|
||||||
; 2.958 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
|
; 2.957 ; IS.state_bit_2 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ;
|
||||||
; 2.965 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.186 ;
|
; 2.958 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
|
||||||
|
; 2.958 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
|
||||||
|
; 2.959 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ;
|
||||||
|
; 2.976 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ;
|
||||||
|
; 2.976 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ;
|
||||||
|
; 2.976 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ;
|
||||||
|
; 2.985 ; PS[1] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.206 ;
|
||||||
|
; 3.037 ; Addr[0] ; DQMH~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.258 ;
|
||||||
|
; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ;
|
||||||
|
; 3.060 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
|
||||||
|
; 3.060 ; Addr[18] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
|
||||||
|
; 3.060 ; Addr[9] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
|
||||||
|
; 3.060 ; Addr[17] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
|
||||||
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -384,35 +384,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||||
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||||
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||||
; 33.331 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; REGEN ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; REGEN ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
; 33.331 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ;
|
; 33.179 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ;
|
||||||
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -421,57 +421,57 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||||
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||||
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||||
; 6.115 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
; 6.115 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ;
|
; 6.267 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ;
|
||||||
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------+
|
||||||
; Setup Transfers ;
|
; Setup Transfers ;
|
||||||
+------------+----------+------------+------------+------------+----------+
|
+------------+----------+------------+------------+----------+----------+
|
||||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||||
+------------+----------+------------+------------+------------+----------+
|
+------------+----------+------------+------------+----------+----------+
|
||||||
; C25M ; C25M ; 1405 ; 0 ; 95 ; 0 ;
|
; C25M ; C25M ; 1285 ; 0 ; 56 ; 0 ;
|
||||||
; PHI0 ; C25M ; false path ; false path ; false path ; 0 ;
|
; PHI0 ; C25M ; false path ; false path ; 0 ; 0 ;
|
||||||
+------------+----------+------------+------------+------------+----------+
|
+------------+----------+------------+------------+----------+----------+
|
||||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------+
|
||||||
; Hold Transfers ;
|
; Hold Transfers ;
|
||||||
+------------+----------+------------+------------+------------+----------+
|
+------------+----------+------------+------------+----------+----------+
|
||||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||||
+------------+----------+------------+------------+------------+----------+
|
+------------+----------+------------+------------+----------+----------+
|
||||||
; C25M ; C25M ; 1405 ; 0 ; 95 ; 0 ;
|
; C25M ; C25M ; 1285 ; 0 ; 56 ; 0 ;
|
||||||
; PHI0 ; C25M ; false path ; false path ; false path ; 0 ;
|
; PHI0 ; C25M ; false path ; false path ; 0 ; 0 ;
|
||||||
+------------+----------+------------+------------+------------+----------+
|
+------------+----------+------------+------------+----------+----------+
|
||||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -514,10 +514,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||||
+---------------------------------+-------+------+
|
+---------------------------------+-------+------+
|
||||||
; Illegal Clocks ; 0 ; 0 ;
|
; Illegal Clocks ; 0 ; 0 ;
|
||||||
; Unconstrained Clocks ; 0 ; 0 ;
|
; Unconstrained Clocks ; 0 ; 0 ;
|
||||||
; Unconstrained Input Ports ; 42 ; 42 ;
|
; Unconstrained Input Ports ; 44 ; 44 ;
|
||||||
; Unconstrained Input Port Paths ; 251 ; 251 ;
|
; Unconstrained Input Port Paths ; 390 ; 390 ;
|
||||||
; Unconstrained Output Ports ; 44 ; 44 ;
|
; Unconstrained Output Ports ; 45 ; 45 ;
|
||||||
; Unconstrained Output Port Paths ; 214 ; 214 ;
|
; Unconstrained Output Port Paths ; 136 ; 136 ;
|
||||||
+---------------------------------+-------+------+
|
+---------------------------------+-------+------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -573,6 +573,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||||
; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; SetFW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; SetFW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
|
@ -615,6 +617,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||||
; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
|
@ -675,6 +678,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||||
; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; SetFW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; SetFW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
|
@ -717,6 +722,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||||
; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
|
@ -741,7 +747,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus Prime Timing Analyzer
|
Info: Running Quartus Prime Timing Analyzer
|
||||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Info: Processing started: Tue Mar 28 05:06:38 2023
|
Info: Processing started: Fri Apr 14 00:01:41 2023
|
||||||
Info: Command: quartus_sta GR8RAM -c GR8RAM
|
Info: Command: quartus_sta GR8RAM -c GR8RAM
|
||||||
Info: qsta_default_script.tcl version: #1
|
Info: qsta_default_script.tcl version: #1
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
|
|
@ -753,22 +759,22 @@ Info (334004): Delay annotation completed successfully
|
||||||
Info (332104): Reading SDC File: 'GR8RAM.sdc'
|
Info (332104): Reading SDC File: 'GR8RAM.sdc'
|
||||||
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
||||||
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
|
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
|
||||||
Info (332146): Worst-case setup slack is 12.472
|
Info (332146): Worst-case setup slack is 14.252
|
||||||
Info (332119): Slack End Point TNS Clock
|
Info (332119): Slack End Point TNS Clock
|
||||||
Info (332119): ========= =================== =====================
|
Info (332119): ========= =================== =====================
|
||||||
Info (332119): 12.472 0.000 C25M
|
Info (332119): 14.252 0.000 C25M
|
||||||
Info (332146): Worst-case hold slack is 1.383
|
Info (332146): Worst-case hold slack is 1.394
|
||||||
Info (332119): Slack End Point TNS Clock
|
Info (332119): Slack End Point TNS Clock
|
||||||
Info (332119): ========= =================== =====================
|
Info (332119): ========= =================== =====================
|
||||||
Info (332119): 1.383 0.000 C25M
|
Info (332119): 1.394 0.000 C25M
|
||||||
Info (332146): Worst-case recovery slack is 33.331
|
Info (332146): Worst-case recovery slack is 33.179
|
||||||
Info (332119): Slack End Point TNS Clock
|
Info (332119): Slack End Point TNS Clock
|
||||||
Info (332119): ========= =================== =====================
|
Info (332119): ========= =================== =====================
|
||||||
Info (332119): 33.331 0.000 C25M
|
Info (332119): 33.179 0.000 C25M
|
||||||
Info (332146): Worst-case removal slack is 6.115
|
Info (332146): Worst-case removal slack is 6.267
|
||||||
Info (332119): Slack End Point TNS Clock
|
Info (332119): Slack End Point TNS Clock
|
||||||
Info (332119): ========= =================== =====================
|
Info (332119): ========= =================== =====================
|
||||||
Info (332119): 6.115 0.000 C25M
|
Info (332119): 6.267 0.000 C25M
|
||||||
Info (332146): Worst-case minimum pulse width slack is 19.734
|
Info (332146): Worst-case minimum pulse width slack is 19.734
|
||||||
Info (332119): Slack End Point TNS Clock
|
Info (332119): Slack End Point TNS Clock
|
||||||
Info (332119): ========= =================== =====================
|
Info (332119): ========= =================== =====================
|
||||||
|
|
@ -778,9 +784,9 @@ Info (332001): The selected device family is not supported by the report_metasta
|
||||||
Info (332102): Design is not fully constrained for setup requirements
|
Info (332102): Design is not fully constrained for setup requirements
|
||||||
Info (332102): Design is not fully constrained for hold requirements
|
Info (332102): Design is not fully constrained for hold requirements
|
||||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
|
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
|
||||||
Info: Peak virtual memory: 13052 megabytes
|
Info: Peak virtual memory: 13051 megabytes
|
||||||
Info: Processing ended: Tue Mar 28 05:06:39 2023
|
Info: Processing ended: Fri Apr 14 00:01:43 2023
|
||||||
Info: Elapsed time: 00:00:01
|
Info: Elapsed time: 00:00:02
|
||||||
Info: Total CPU time (on all processors): 00:00:01
|
Info: Total CPU time (on all processors): 00:00:01
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -3,19 +3,19 @@ Timing Analyzer Summary
|
||||||
------------------------------------------------------------
|
------------------------------------------------------------
|
||||||
|
|
||||||
Type : Setup 'C25M'
|
Type : Setup 'C25M'
|
||||||
Slack : 12.472
|
Slack : 14.252
|
||||||
TNS : 0.000
|
TNS : 0.000
|
||||||
|
|
||||||
Type : Hold 'C25M'
|
Type : Hold 'C25M'
|
||||||
Slack : 1.383
|
Slack : 1.394
|
||||||
TNS : 0.000
|
TNS : 0.000
|
||||||
|
|
||||||
Type : Recovery 'C25M'
|
Type : Recovery 'C25M'
|
||||||
Slack : 33.331
|
Slack : 33.179
|
||||||
TNS : 0.000
|
TNS : 0.000
|
||||||
|
|
||||||
Type : Removal 'C25M'
|
Type : Removal 'C25M'
|
||||||
Slack : 6.115
|
Slack : 6.267
|
||||||
TNS : 0.000
|
TNS : 0.000
|
||||||
|
|
||||||
Type : Minimum Pulse Width 'C25M'
|
Type : Minimum Pulse Width 'C25M'
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue
Block a user