Apple-2-HW/GR8RAM
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Clarifications and bugfixes, will try again

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This commit is contained in:
Zane Kaminski 2019-09-02 01:42:07 -04:00
parent 5b230c0966
commit a73cbf10ef
79 changed files with 657 additions and 701 deletions
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12
Docs.sch
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@ -44,8 +44,6 @@ Wire Wire Line
6100 1400 6150 1300 6100 1400 6150 1300
Wire Wire Line Wire Wire Line
6100 1150 6150 1250 6100 1150 6150 1250
Text Notes 6300 1100 0 40 ~ 0
S7
Wire Wire Line Wire Wire Line
10300 1100 10300 1000 10300 1100 10300 1000
Wire Wire Line Wire Wire Line
@ -212,16 +210,12 @@ Wire Wire Line
4300 1100 4300 1000 4300 1100 4300 1000
Wire Wire Line Wire Wire Line
4300 1000 4600 1000 4300 1000 4600 1000
Wire Wire Line
4600 1000 4600 1100
Wire Wire Line Wire Wire Line
4600 1100 4900 1100 4600 1100 4900 1100
Wire Wire Line Wire Wire Line
4900 1100 4900 1000 4900 1100 4900 1000
Wire Wire Line Wire Wire Line
4900 1000 5200 1000 4900 1000 5200 1000
Wire Wire Line
5200 1000 5200 1100
Wire Wire Line Wire Wire Line
10300 1000 10400 1000 10300 1000 10400 1000
Wire Wire Line Wire Wire Line
@ -803,4 +797,10 @@ Wire Wire Line
10400 1650 10450 1650 10400 1650 10450 1650
Wire Wire Line Wire Wire Line
10350 1550 10400 1650 10350 1550 10400 1650
Wire Wire Line
5200 1000 5200 1100
Wire Wire Line
4600 1000 4600 1100
Text Notes 6300 1100 0 40 ~ 0
S7
$EndSCHEMATC $EndSCHEMATC

8
GR8RAM.sch
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@ -2186,6 +2186,10 @@ Wire Bus Line
Connection ~ 7100 4800 Connection ~ 7100 4800
Wire Bus Line Wire Bus Line
7100 4800 4500 4800 7100 4800 4500 4800
Text Label 2700 3350 2 50 ~ 0
C7Mout
Text Label 2700 3250 2 50 ~ 0
PHI1out
Wire Bus Line Wire Bus Line
2400 1150 2400 2150 2400 1150 2400 2150
Wire Bus Line Wire Bus Line
@ -2216,8 +2220,4 @@ Wire Bus Line
8900 1900 8900 5850 8900 1900 8900 5850
Wire Bus Line Wire Bus Line
7300 1900 7300 5850 7300 1900 7300 5850
Text Label 2700 3350 2 50 ~ 0
C7Mout
Text Label 2700 3250 2 50 ~ 0
PHI1out
$EndSCHEMATC $EndSCHEMATC

39
cpld/GR8RAM.qsf
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@ -261,22 +261,21 @@ set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal17
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to IOBank0 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to IOBank0
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to IOROMEN set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to IOROMEN
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to MODE set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to MODE
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI0in set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI0seen
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI0seen set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b0_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b0_MC set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b1_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b1_MC set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b2_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b2_MC set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b3_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b3_MC set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b4_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b4_MC set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b5_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b5_MC set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b6_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b6_MC set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b7_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b7_MC set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b8_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b8_MC set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b9_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b9_MC set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1in
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1in set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1out
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1out set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1reg
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1reg
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Q3 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Q3
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RAMSEL_MC set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RAMSEL_MC
@ -318,10 +317,10 @@ set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[0]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[1] set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[1]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[2] set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[2]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[3] set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[3]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to S set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to S[0] set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S[0]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to S[1] set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S[1]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to S[2] set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S[2]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to SetWR set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to SetWR
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to always0 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to always0
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to always2 set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to always2

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cpld/GR8RAM.v
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@ -29,11 +29,10 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
input [15:0] A; // 6502 address bus input [15:0] A; // 6502 address bus
input nWE; // 6502 R/W input nWE; // 6502 R/W
output [10:0] RA; // DRAM/ROM address output [10:0] RA; // DRAM/ROM address
assign RA[10:8] = ASel ? Addr[10:8] : Addr[21:19]; assign RA[10:8] = ASel ? Addr[21:19] : Addr[10:8];
assign RA[7:0] = assign RA[7:0] = (~nIOSTRB & ~IOBank0) ? Bank+1 :
(~nIOSTRB & nIOSEL & ~IOBank0) ? Bank+1 : (~ASel & nIOSEL & nIOSTRB) ? Addr[18:11] :
(ASel & nIOSEL & nIOSTRB) ? Addr[7:0] : (ASel & nIOSEL & nIOSTRB) ? Addr[7:0] : 8'h00;
(~ASel & nIOSEL & nIOSTRB) ? Addr[18:11] : 8'h00;
/* Data Bus Routing */ /* Data Bus Routing */
// DRAM/ROM data bus // DRAM/ROM data bus
@ -49,18 +48,17 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
inout [7:0] D = DOE ? Dout : 8'bZ; inout [7:0] D = DOE ? Dout : 8'bZ;
/* Inhibit output */ /* Inhibit output */
/*wire AROMSEL; wire AROMSEL;
LCELL AROMSEL_MC (.in((A[15:12]==4'hD | A[15:12]==4'hE | A[15:12]==4'hF) & nWE & ~MODE), .out(AROMSEL)); LCELL AROMSEL_MC (.in(/*(A[15:12]==4'hD | A[15:12]==4'hE | A[15:12]==4'hF) & nWE & ~MODE*/0), .out(AROMSEL));
output nINH = AROMSEL ? 1'b0 : 1'bZ;*/ output nINH = AROMSEL ? 1'b0 : 1'bZ;
output nINH = 1'bZ;
/* DRAM and ROM Control Signals */ /* DRAM and ROM Control Signals */
output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSDBEN); // ROM chip select output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSDBEN); // ROM chip select
output nROE = ~nWE; // need this for flash ROM output nROE = ~nWE; // need this for flash ROM
output nRWE = nWE | (nDEVSEL & nIOSEL & nIOSTRB); // for ROM & DRAM output nRWE = nWE | (nDEVSEL & nIOSEL & nIOSTRB); // for ROM & DRAM
output nRAS = ~(RASr | RASf); output nRAS = ~(RASr | RASf);
output nCAS0 = ~(CASr | (CASf & ~nDEVSEL & ~Addr[22])); // DRAM CAS bank 0 output nCAS0 = ~(CASr | (CASf & RAMSEL & ~Addr[22])); // DRAM CAS bank 0
output nCAS1 = ~(CASr | (CASf & ~nDEVSEL & Addr[22])); // DRAM CAS bank 1 output nCAS1 = ~(CASr | (CASf & RAMSEL & Addr[22])); // DRAM CAS bank 1
/* 6502-accessible Registers */ /* 6502-accessible Registers */
reg [7:0] Bank = 8'h00; // Bank register for ROM access reg [7:0] Bank = 8'h00; // Bank register for ROM access
@ -154,15 +152,15 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
// Similarly, only select the ROM chip starting at the end of S4. // Similarly, only select the ROM chip starting at the end of S4.
// This provides address setup time for write operations and // This provides address setup time for write operations and
// minimizes power consumption. // minimizes power consumption.
CSDBEN <= S[2]; /*S==4 | S==5 | S==6 | S==7 */ CSDBEN <= S==4 | S==5 | S==6 | S==7;
// Increment address register after RAM access, // Increment address register after RAM access.
// otherwise set register during S6 if accessed.
if (S==2 & RAMSELreg) begin if (S==2 & RAMSELreg) begin
Addr <= Addr+1; // RAMSELreg refers to prev. Addr <= Addr+1;
RAMSELreg <= 1'b0; RAMSELreg <= 1'b0;
end end
// Set register during S6 if accessed.
if (S==6) begin if (S==6) begin
if (BankWR) Bank[7:0] <= D[7:0]; // Bank if (BankWR) Bank[7:0] <= D[7:0]; // Bank
if (SetWR) IOBank0 <= D[7:0] == 8'hE5; if (SetWR) IOBank0 <= D[7:0] == 8'hE5;
@ -181,8 +179,8 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
// so hold RAS through S5 // so hold RAS through S5
RASr <= (S==4 & RAMSEL); RASr <= (S==4 & RAMSEL);
// Multiplex DRAM address in at end of S4 through S5 end. // Multiplex DRAM address in at end of S4 through S6.
ASel = RAMSEL & S[2] & ~S[1]; /*(S==4 | S==5)*/ ASel = RAMSEL & (S==4 | S==5);
// Refresh at end of S1 (i.e. through S2) // Refresh at end of S1 (i.e. through S2)
// CAS whenever RAM seleced // CAS whenever RAM seleced
@ -195,7 +193,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
// Refresh in S2 // Refresh in S2
// Row activate in S4 when accessing RAM // Row activate in S4 when accessing RAM
// Hold RAS in S5 when not doing late CAS for write. // Hold RAS in S5 when not doing late CAS for write.
RASf <= (S==2 & Ref==0) | ((S==4 | (S==5 & ~nWE) & RAMSEL)); RASf <= (S==2 & Ref==0) | (RAMSEL & (S==4 | (S==5 /*& ~nWE*/)));
// CASf gated by nDEVSEL; no need to predicate on RAMSEL. // CASf gated by nDEVSEL; no need to predicate on RAMSEL.
// Early CAS in S5 for read operations. // Early CAS in S5 for read operations.

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cpld/db/GR8RAM.asm.qmsg
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@ -1,5 +1,5 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567385056202 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567402893262 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567385056202 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:44:16 2019 " "Processing started: Sun Sep 01 20:44:16 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567385056202 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567385056202 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402893262 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:41:32 2019 " "Processing started: Mon Sep 02 01:41:32 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402893262 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567402893262 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567385056202 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567402893262 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567385056310 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567402895340 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4520 " "Peak virtual memory: 4520 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567385056470 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:44:16 2019 " "Processing ended: Sun Sep 01 20:44:16 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567385056470 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567385056470 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567385056470 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567385056470 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402895809 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:41:35 2019 " "Processing ended: Mon Sep 02 01:41:35 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402895809 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402895809 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402895809 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567402895809 ""}

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cpld/db/GR8RAM.db_info
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@ -1,3 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280 Version_Index = 302049280
Creation_Time = Sat Aug 31 22:55:28 2019 Creation_Time = Mon Sep 02 01:36:55 2019

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{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567385055172 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567402890980 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567385055174 ""} { "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567402890996 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567385055356 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:44:15 2019 " "Processing ended: Sun Sep 01 20:44:15 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567385055356 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567385055356 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567385055356 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567385055356 ""} { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402891543 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:41:31 2019 " "Processing ended: Mon Sep 02 01:41:31 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402891543 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402891543 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402891543 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567402891543 ""}

1
cpld/db/GR8RAM.hier_info
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@ -141,7 +141,6 @@ nDEVSEL => comb.IN0
nDEVSEL => comb.IN0 nDEVSEL => comb.IN0
nIOSEL => RA.IN1 nIOSEL => RA.IN1
nIOSEL => RA.IN0 nIOSEL => RA.IN0
nIOSEL => RA.IN1
nIOSEL => comb.IN0 nIOSEL => comb.IN0
nIOSEL => comb.IN1 nIOSEL => comb.IN1
nIOSTRB => RA.IN0 nIOSTRB => RA.IN0

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cpld/db/GR8RAM.hif
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cpld/db/GR8RAM.ipinfo
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cpld/db/GR8RAM.lpc.rdb
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cpld/db/GR8RAM.map.cdb
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72
cpld/db/GR8RAM.map.qmsg
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@ -1,36 +1,36 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567385053238 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567402877574 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567385053238 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:44:13 2019 " "Processing started: Sun Sep 01 20:44:13 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567385053238 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567385053238 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402877574 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:41:17 2019 " "Processing started: Mon Sep 02 01:41:17 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402877574 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567402877574 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567385053238 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567402877574 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567385053456 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567402881230 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(41) " "Verilog HDL warning at GR8RAM.v(41): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 41 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567385053481 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(40) " "Verilog HDL warning at GR8RAM.v(40): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 40 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567402881340 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(49) " "Verilog HDL warning at GR8RAM.v(49): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 49 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567385053481 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(48) " "Verilog HDL warning at GR8RAM.v(48): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 48 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567402881340 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(177) " "Verilog HDL information at GR8RAM.v(177): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 177 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567385053481 ""} { "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(175) " "Verilog HDL information at GR8RAM.v(175): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 175 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567402881340 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567385053482 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567385053482 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567402881340 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567402881340 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567385053522 ""} { "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567402881824 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(33) " "Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 33 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567385053523 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(33) " "Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402881840 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567385053523 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402881840 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(137) " "Verilog HDL assignment warning at GR8RAM.v(137): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 137 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567385053524 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(135) " "Verilog HDL assignment warning at GR8RAM.v(135): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 135 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402881840 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 GR8RAM.v(162) " "Verilog HDL assignment warning at GR8RAM.v(162): truncated value with size 32 to match size of target (23)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567385053524 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 GR8RAM.v(159) " "Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (23)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402881840 "|GR8RAM"}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385053598 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567385053598 ""} { "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402882199 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567402882199 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385053599 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385053599 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567385053599 ""} { "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402882199 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402882199 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567402882199 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385053623 ""} { "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402882699 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053624 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053624 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053624 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567385053624 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402882699 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402882699 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402882699 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567402882699 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385053641 ""} { "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402883012 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053641 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567385053641 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883012 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883012 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883012 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883012 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567402883012 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053656 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883277 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053665 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883637 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053667 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883652 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053679 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402883934 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053688 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884215 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053689 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884230 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385053692 ""} { "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402884277 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add3 " "Instantiated megafunction \"lpm_add_sub:Add3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 23 " "Parameter \"LPM_WIDTH\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053692 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567385053692 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add3 " "Instantiated megafunction \"lpm_add_sub:Add3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 23 " "Parameter \"LPM_WIDTH\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884277 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884277 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884277 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884277 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567402884277 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|addcore:adder\[2\] lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|addcore:adder\[2\]\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053694 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|addcore:adder\[2\] lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|addcore:adder\[2\]\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884293 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|look_add:look_ahead_unit lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053700 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|look_add:look_ahead_unit lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884387 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|altshift:result_ext_latency_ffs lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053701 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|altshift:result_ext_latency_ffs lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402884387 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "31 " "Ignored 31 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "31 " "Ignored 31 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567385053756 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567385053756 ""} { "Info" "IMLS_MLS_IGNORED_SUMMARY" "31 " "Ignored 31 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "31 " "Ignored 31 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567402884715 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567402884715 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567385053836 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567385053836 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567385053836 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567402884871 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567402884871 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567402884871 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567385054051 ""} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402885324 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567402885324 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "170 " "Implemented 170 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567385054052 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567385054052 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567385054052 ""} { "Info" "ICUT_CUT_TM_MCELLS" "102 " "Implemented 102 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567385054052 ""} { "Info" "ICUT_CUT_TM_SEXPS" "5 " "Implemented 5 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567385054052 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567385054052 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567402885324 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567402885324 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567402885324 ""} { "Info" "ICUT_CUT_TM_MCELLS" "102 " "Implemented 102 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567402885324 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567402885324 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567385054089 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567402885605 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567385054124 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:44:14 2019 " "Processing ended: Sun Sep 01 20:44:14 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567385054124 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567385054124 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567385054124 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567385054124 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402885715 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:41:25 2019 " "Processing ended: Mon Sep 02 01:41:25 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402885715 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402885715 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402885715 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567402885715 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567385057408 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567402899152 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057409 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:44:17 2019 " "Processing started: Sun Sep 01 20:44:17 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567385057409 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567385057409 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402899168 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:41:37 2019 " "Processing started: Mon Sep 02 01:41:37 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402899168 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567402899168 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567385057409 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567402899168 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567385057466 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567402899324 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567385057560 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567402901637 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567385057568 ""} { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567402901699 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567385057571 ""} { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567402901715 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567385057616 ""} { "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567402901871 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567385057629 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567402902059 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567385057630 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567402902059 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057630 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057630 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057630 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902074 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902074 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902074 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567385057632 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567402902090 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567385057644 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567402902309 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.000 " "Worst-case setup slack is -47.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057649 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057649 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.000 -1802.000 C7M " " -47.000 -1802.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057649 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057649 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567385057649 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -47.000 " "Worst-case setup slack is -47.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.000 -1763.000 C7M " " -47.000 -1763.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057658 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567385057658 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567402902356 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567385057664 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567402902371 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567385057669 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567402902402 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057674 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057674 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057674 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -432.000 C7M " " -4.500 -432.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057674 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567385057674 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -432.000 C7M " " -4.500 -432.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402902465 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567402902465 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567385057736 ""} { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567402902637 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567385057757 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567402902715 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567385057758 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567402902715 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567385057823 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:44:17 2019 " "Processing ended: Sun Sep 01 20:44:17 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567385057823 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567385057823 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567385057823 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567385057823 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "263 " "Peak virtual memory: 263 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402902934 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:41:42 2019 " "Processing ended: Mon Sep 02 01:41:42 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402902934 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402902934 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402902934 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567402902934 ""}

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cpld/db/GR8RAM.sta.rdb
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cpld/db/GR8RAM.sta_cmp.15_slow.tdb
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cpld/db/GR8RAM.tis_db_list.ddb
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10
cpld/db/GR8RAM.tmw_info
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@ -1,6 +1,6 @@
start_full_compilation:s:00:00:06 start_full_compilation:s:00:00:27
start_analysis_synthesis:s:00:00:02-start_full_compilation start_analysis_synthesis:s:00:00:10-start_full_compilation
start_analysis_elaboration:s-start_full_compilation start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:01-start_full_compilation start_fitter:s:00:00:06-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation start_assembler:s:00:00:04-start_full_compilation
start_timing_analyzer:s:00:00:01-start_full_compilation start_timing_analyzer:s:00:00:07-start_full_compilation

2
cpld/db/add_sub_8ph.tdf
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@ -1,5 +1,5 @@
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=23 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result --lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=23 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END --VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation -- Copyright (C) 1991-2013 Altera Corporation

2
cpld/db/add_sub_rnh.tdf
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@ -1,5 +1,5 @@
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result --lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END --VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation -- Copyright (C) 1991-2013 Altera Corporation

148
cpld/db/prev_cmp_GR8RAM.qmsg
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@ -1,74 +1,74 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567384350839 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567402633084 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567384350840 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:32:30 2019 " "Processing started: Sun Sep 01 20:32:30 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567384350840 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567384350840 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402633084 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:37:12 2019 " "Processing started: Mon Sep 02 01:37:12 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402633084 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567402633084 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567384350840 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567402633084 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567384351069 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567402636787 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(41) " "Verilog HDL warning at GR8RAM.v(41): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 41 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567384351095 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(40) " "Verilog HDL warning at GR8RAM.v(40): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 40 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567402636975 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(49) " "Verilog HDL warning at GR8RAM.v(49): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 49 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567384351095 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(48) " "Verilog HDL warning at GR8RAM.v(48): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 48 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567402636975 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(177) " "Verilog HDL information at GR8RAM.v(177): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 177 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567384351095 ""} { "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(175) " "Verilog HDL information at GR8RAM.v(175): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 175 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567402636975 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567384351098 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567384351098 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567402636975 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567402636975 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567384351146 ""} { "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567402637240 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(33) " "Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 33 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567384351148 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(33) " "Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402637240 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567384351149 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402637240 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(137) " "Verilog HDL assignment warning at GR8RAM.v(137): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 137 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567384351149 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(135) " "Verilog HDL assignment warning at GR8RAM.v(135): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 135 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402637240 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 GR8RAM.v(162) " "Verilog HDL assignment warning at GR8RAM.v(162): truncated value with size 32 to match size of target (23)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567384351149 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 GR8RAM.v(159) " "Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (23)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567402637240 "|GR8RAM"}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351230 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567384351230 ""} { "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402637600 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567402637600 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351230 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351230 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567384351230 ""} { "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402637600 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402637600 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567402637600 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351258 ""} { "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402638147 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351258 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351258 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351258 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567384351258 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638162 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567402638162 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351275 ""} { "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402638412 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351275 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567384351275 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638412 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638412 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638412 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638412 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567402638412 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351288 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402638740 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351298 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639006 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351300 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639053 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351312 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639272 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351324 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639693 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351325 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 33 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639787 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351330 ""} { "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402639959 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add3 " "Instantiated megafunction \"lpm_add_sub:Add3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 23 " "Parameter \"LPM_WIDTH\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351330 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567384351330 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add3 " "Instantiated megafunction \"lpm_add_sub:Add3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 23 " "Parameter \"LPM_WIDTH\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639959 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639959 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639959 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402639959 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567402639959 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|addcore:adder\[2\] lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|addcore:adder\[2\]\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351332 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|addcore:adder\[2\] lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|addcore:adder\[2\]\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402640178 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|look_add:look_ahead_unit lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351338 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|look_add:look_ahead_unit lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402640318 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|altshift:result_ext_latency_ffs lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351339 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|altshift:result_ext_latency_ffs lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567402640365 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "31 " "Ignored 31 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "31 " "Ignored 31 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567384351400 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567384351400 ""} { "Info" "IMLS_MLS_IGNORED_SUMMARY" "31 " "Ignored 31 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "31 " "Ignored 31 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567402640850 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567402640850 ""}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567384351481 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567384351481 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567384351481 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567402641146 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567402641146 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567402641146 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567384351716 ""} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567402641725 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567402641725 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "170 " "Implemented 170 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567384351716 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567384351716 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567384351716 ""} { "Info" "ICUT_CUT_TM_MCELLS" "102 " "Implemented 102 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567384351716 ""} { "Info" "ICUT_CUT_TM_SEXPS" "5 " "Implemented 5 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567384351716 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567384351716 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567402641740 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567402641740 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567402641740 ""} { "Info" "ICUT_CUT_TM_MCELLS" "102 " "Implemented 102 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567402641740 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567402641740 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567384351755 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567402642303 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567384351797 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:32:31 2019 " "Processing ended: Sun Sep 01 20:32:31 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567384351797 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567384351797 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567384351797 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567384351797 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "308 " "Peak virtual memory: 308 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402642443 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:37:22 2019 " "Processing ended: Mon Sep 02 01:37:22 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402642443 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402642443 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402642443 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567402642443 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567384352736 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567402646912 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567384352736 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:32:32 2019 " "Processing started: Sun Sep 01 20:32:32 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567384352736 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1567384352736 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402646943 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:37:23 2019 " "Processing started: Mon Sep 02 01:37:23 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402646943 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1567402646943 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1567384352736 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1567402646943 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1567384352791 ""} { "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1567402647256 ""}
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1567384352792 ""} { "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1567402647256 ""}
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1567384352792 ""} { "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1567402647256 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567384352842 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567402650052 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567384352844 ""} { "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567402650084 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567384353046 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:32:33 2019 " "Processing ended: Sun Sep 01 20:32:33 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567384353046 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567384353046 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567384353046 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567384353046 ""} { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402651162 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:37:31 2019 " "Processing ended: Mon Sep 02 01:37:31 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402651162 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402651162 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402651162 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567402651162 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1567384353861 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1567402654115 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567384353861 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:32:33 2019 " "Processing started: Sun Sep 01 20:32:33 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567384353861 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567384353861 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402654130 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:37:33 2019 " "Processing started: Mon Sep 02 01:37:33 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402654130 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567402654130 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567384353861 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567402654130 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567384353992 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567402659802 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4520 " "Peak virtual memory: 4520 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567384354129 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:32:34 2019 " "Processing ended: Sun Sep 01 20:32:34 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567384354129 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567384354129 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567384354129 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567384354129 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402660708 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:37:40 2019 " "Processing ended: Mon Sep 02 01:37:40 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402660708 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402660708 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402660708 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567402660708 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1567384354733 ""} { "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1567402662083 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1567384355080 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1567402666020 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355080 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:32:34 2019 " "Processing started: Sun Sep 01 20:32:34 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567384355080 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567384355080 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567402666020 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 02 01:37:42 2019 " "Processing started: Mon Sep 02 01:37:42 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567402666020 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567402666020 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567384355080 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567402666020 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567384355139 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567402666129 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567384355239 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567402668660 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567384355247 ""} { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567402668676 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567384355250 ""} { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567402668676 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567384355277 ""} { "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567402668785 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567384355297 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567402668863 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567384355297 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567402668863 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355298 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355298 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355298 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567402668863 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567402668863 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567402668863 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567384355301 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567402668879 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567384355316 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567402669035 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -21.000 " "Worst-case setup slack is -21.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355319 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355319 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -21.000 -840.000 C7M " " -21.000 -840.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355319 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.500 -20.000 C7M_2 " " -14.500 -20.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355319 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567384355319 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -47.000 " "Worst-case setup slack is -47.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.000 -1802.000 C7M " " -47.000 -1802.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669113 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567402669113 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355326 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355326 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355326 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355326 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567384355326 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669129 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669129 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669129 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669129 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567402669129 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567384355329 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567402669129 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567384355332 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567402669144 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -432.000 C7M " " -4.500 -432.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355335 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567384355335 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669160 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669160 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669160 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -432.000 C7M " " -4.500 -432.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567402669160 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567402669160 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567384355402 ""} { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567402669285 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567384355438 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567402669347 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567384355438 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567402669347 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567384355509 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:32:35 2019 " "Processing ended: Sun Sep 01 20:32:35 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567384355509 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567384355509 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567384355509 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567384355509 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "263 " "Peak virtual memory: 263 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567402669582 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 02 01:37:49 2019 " "Processing ended: Mon Sep 02 01:37:49 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567402669582 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567402669582 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567402669582 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567402669582 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 19 s " "Quartus II Full Compilation was successful. 0 errors, 19 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567384356160 ""} { "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 19 s " "Quartus II Full Compilation was successful. 0 errors, 19 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567402670472 ""}

BIN
cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
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Binary file not shown.

54
cpld/output_files/GR8RAM.asm.rpt
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@ -1,6 +1,6 @@
Assembler report for GR8RAM Assembler report for GR8RAM
Sun Sep 01 20:44:16 2019 Mon Sep 02 01:41:35 2019
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
--------------------- ---------------------
@ -10,7 +10,7 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
2. Assembler Summary 2. Assembler Summary
3. Assembler Settings 3. Assembler Settings
4. Assembler Generated Files 4. Assembler Generated Files
5. Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof 5. Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof
6. Assembler Messages 6. Assembler Messages
@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+ +---------------------------------------------------------------+
; Assembler Summary ; ; Assembler Summary ;
+-----------------------+---------------------------------------+ +-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Sep 01 20:44:16 2019 ; ; Assembler Status ; Successful - Mon Sep 02 01:41:35 2019 ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX7000S ; ; Family ; MAX7000S ;
@ -73,39 +73,39 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+----------+---------------+ +-----------------------------------------------------------------------------+----------+---------------+
+--------------------------------------------------------------------+ +----------------------------------------------+
; Assembler Generated Files ; ; Assembler Generated Files ;
+--------------------------------------------------------------------+ +----------------------------------------------+
; File Name ; ; File Name ;
+--------------------------------------------------------------------+ +----------------------------------------------+
; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ; ; Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
+--------------------------------------------------------------------+ +----------------------------------------------+
+----------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ; ; Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
+----------------+-----------------------------------------------------------------------------+ +----------------+-------------------------------------------------------+
; Option ; Setting ; ; Option ; Setting ;
+----------------+-----------------------------------------------------------------------------+ +----------------+-------------------------------------------------------+
; Device ; EPM7128SLC84-15 ; ; Device ; EPM7128SLC84-15 ;
; JTAG usercode ; 0x00000000 ; ; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x0017B91B ; ; Checksum ; 0x00179BB7 ;
+----------------+-----------------------------------------------------------------------------+ +----------------+-------------------------------------------------------+
+--------------------+ +--------------------+
; Assembler Messages ; ; Assembler Messages ;
+--------------------+ +--------------------+
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler Info: Running Quartus II 32-bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun Sep 01 20:44:16 2019 Info: Processing started: Mon Sep 02 01:41:32 2019
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Info (115030): Assembler is generating device programming files Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4520 megabytes Info: Peak virtual memory: 277 megabytes
Info: Processing ended: Sun Sep 01 20:44:16 2019 Info: Processing ended: Mon Sep 02 01:41:35 2019
Info: Elapsed time: 00:00:00 Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:00 Info: Total CPU time (on all processors): 00:00:03

2
cpld/output_files/GR8RAM.done
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@ -1 +1 @@
Sun Sep 01 20:44:18 2019 Mon Sep 02 01:41:43 2019

336
cpld/output_files/GR8RAM.fit.rpt
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@ -1,6 +1,6 @@
Fitter report for GR8RAM Fitter report for GR8RAM
Sun Sep 01 20:44:15 2019 Mon Sep 02 01:41:31 2019
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
--------------------- ---------------------
@ -9,27 +9,25 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
1. Legal Notice 1. Legal Notice
2. Fitter Summary 2. Fitter Summary
3. Fitter Settings 3. Fitter Settings
4. Parallel Compilation 4. Pin-Out File
5. Pin-Out File 5. Fitter Resource Usage Summary
6. Fitter Resource Usage Summary 6. Input Pins
7. Input Pins 7. Output Pins
8. Output Pins 8. Bidir Pins
9. Bidir Pins 9. All Package Pins
10. All Package Pins 10. I/O Standard
11. I/O Standard 11. Dedicated Inputs I/O
12. Dedicated Inputs I/O 12. Output Pin Default Load For Reported TCO
13. Output Pin Default Load For Reported TCO 13. Fitter Resource Utilization by Entity
14. Fitter Resource Utilization by Entity 14. Control Signals
15. Control Signals 15. Global & Other Fast Signals
16. Global & Other Fast Signals 16. Non-Global High Fan-Out Signals
17. Non-Global High Fan-Out Signals 17. Other Routing Usage Summary
18. Other Routing Usage Summary 18. LAB External Interconnect
19. LAB External Interconnect 19. LAB Macrocells
20. LAB Macrocells 20. Logic Cell Interconnection
21. Shareable Expander 21. Fitter Device Options
22. Logic Cell Interconnection 22. Fitter Messages
23. Fitter Device Options
24. Fitter Messages
@ -55,8 +53,8 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+ +-----------------------------------------------------------------------------+
; Fitter Summary ; ; Fitter Summary ;
+---------------------------+-------------------------------------------------+ +---------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Sun Sep 01 20:44:15 2019 ; ; Fitter Status ; Successful - Mon Sep 02 01:41:31 2019 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX7000S ; ; Family ; MAX7000S ;
@ -87,21 +85,10 @@ applicable agreement for further details.
+----------------------------------------------------------------------------+-----------------------+---------------+ +----------------------------------------------------------------------------+-----------------------+---------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------+ +--------------+
; Pin-Out File ; ; Pin-Out File ;
+--------------+ +--------------+
The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pin. The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+---------------------------------------------------+ +---------------------------------------------------+
@ -111,19 +98,19 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/outp
+------------------------------+--------------------+ +------------------------------+--------------------+
; Logic cells ; 102 / 128 ( 80 % ) ; ; Logic cells ; 102 / 128 ( 80 % ) ;
; Registers ; 50 / 128 ( 39 % ) ; ; Registers ; 50 / 128 ( 39 % ) ;
; Number of pterms used ; 250 ; ; Number of pterms used ; 249 ;
; I/O pins ; 67 / 68 ( 99 % ) ; ; I/O pins ; 67 / 68 ( 99 % ) ;
; -- Clock pins ; 2 / 2 ( 100 % ) ; ; -- Clock pins ; 2 / 2 ( 100 % ) ;
; -- Dedicated input pins ; 2 / 2 ( 100 % ) ; ; -- Dedicated input pins ; 2 / 2 ( 100 % ) ;
; ; ; ; ; ;
; Global signals ; 2 ; ; Global signals ; 2 ;
; Shareable expanders ; 5 / 128 ( 4 % ) ; ; Shareable expanders ; 0 / 128 ( 0 % ) ;
; Parallel expanders ; 0 / 120 ( 0 % ) ; ; Parallel expanders ; 0 / 120 ( 0 % ) ;
; Cells using turbo bit ; 41 / 128 ( 32 % ) ; ; Cells using turbo bit ; 56 / 128 ( 44 % ) ;
; Maximum fan-out ; 50 ; ; Maximum fan-out ; 50 ;
; Highest non-global fan-out ; 48 ; ; Highest non-global fan-out ; 48 ;
; Total fan-out ; 993 ; ; Total fan-out ; 962 ;
; Average fan-out ; 5.71 ; ; Average fan-out ; 5.69 ;
+------------------------------+--------------------+ +------------------------------+--------------------+
@ -154,11 +141,11 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/outp
; PHI0in ; 8 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ; ; PHI0in ; 8 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
; PHI1in ; 2 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ; ; PHI1in ; 2 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ;
; Q3 ; 6 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ; ; Q3 ; 6 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
; nDEVSEL ; 21 ; -- ; 2 ; 18 ; 0 ; no ; no ; TTL ; User ; ; nDEVSEL ; 21 ; -- ; 2 ; 16 ; 0 ; no ; no ; TTL ; User ;
; nIOSEL ; 74 ; -- ; 8 ; 13 ; 0 ; no ; no ; TTL ; User ; ; nIOSEL ; 74 ; -- ; 8 ; 13 ; 0 ; no ; no ; TTL ; User ;
; nIOSTRB ; 24 ; -- ; 3 ; 12 ; 0 ; no ; no ; TTL ; User ; ; nIOSTRB ; 24 ; -- ; 3 ; 12 ; 0 ; no ; no ; TTL ; User ;
; nRES ; 1 ; -- ; -- ; 50 ; 0 ; yes ; no ; TTL ; User ; ; nRES ; 1 ; -- ; -- ; 50 ; 0 ; yes ; no ; TTL ; User ;
; nWE ; 20 ; -- ; 2 ; 11 ; 0 ; no ; no ; TTL ; User ; ; nWE ; 20 ; -- ; 2 ; 10 ; 0 ; no ; no ; TTL ; User ;
+---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+ +---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
@ -359,19 +346,19 @@ Note: User assignments will override these defaults. The user specified values a
; A[1] ; PIN_76 ; 15 ; Clock enable ; no ; -- ; -- ; ; A[1] ; PIN_76 ; 15 ; Clock enable ; no ; -- ; -- ;
; A[2] ; PIN_77 ; 15 ; Clock enable ; no ; -- ; -- ; ; A[2] ; PIN_77 ; 15 ; Clock enable ; no ; -- ; -- ;
; A[3] ; PIN_79 ; 15 ; Clock enable ; no ; -- ; -- ; ; A[3] ; PIN_79 ; 15 ; Clock enable ; no ; -- ; -- ;
; BankWR_MC ; LC111 ; 8 ; Clock enable ; no ; -- ; -- ; ; BankWR_MC ; LC103 ; 8 ; Clock enable ; no ; -- ; -- ;
; C7M ; PIN_83 ; 48 ; Clock ; yes ; On ; -- ; ; C7M ; PIN_83 ; 48 ; Clock ; yes ; On ; -- ;
; C7M_2 ; PIN_84 ; 3 ; Clock ; no ; -- ; -- ; ; C7M_2 ; PIN_84 ; 3 ; Clock ; no ; -- ; -- ;
; PHI1b9_MC ; LC37 ; 6 ; Clock enable ; no ; -- ; -- ; ; PHI1b9_MC ; LC37 ; 6 ; Clock enable ; no ; -- ; -- ;
; RAMSELreg ; LC34 ; 24 ; Clock enable ; no ; -- ; -- ; ; RAMSELreg ; LC36 ; 24 ; Clock enable ; no ; -- ; -- ;
; REGEN ; LC41 ; 7 ; Clock enable ; no ; -- ; -- ; ; REGEN ; LC84 ; 7 ; Clock enable ; no ; -- ; -- ;
; S[0] ; LC113 ; 46 ; Clock enable ; no ; -- ; -- ; ; S[0] ; LC126 ; 46 ; Clock enable ; no ; -- ; -- ;
; S[1] ; LC117 ; 47 ; Clock enable ; no ; -- ; -- ; ; S[1] ; LC114 ; 47 ; Clock enable ; no ; -- ; -- ;
; S[2] ; LC122 ; 48 ; Clock enable ; no ; -- ; -- ; ; S[2] ; LC113 ; 48 ; Clock enable ; no ; -- ; -- ;
; nDEVSEL ; PIN_21 ; 18 ; Clock enable ; no ; -- ; -- ; ; nDEVSEL ; PIN_21 ; 16 ; Clock enable ; no ; -- ; -- ;
; nIOSEL ; PIN_74 ; 13 ; Clock enable ; no ; -- ; -- ; ; nIOSEL ; PIN_74 ; 13 ; Clock enable ; no ; -- ; -- ;
; nRES ; PIN_1 ; 50 ; Async. clear ; yes ; On ; -- ; ; nRES ; PIN_1 ; 50 ; Async. clear ; yes ; On ; -- ;
; nWE ; PIN_20 ; 11 ; Clock enable ; no ; -- ; -- ; ; nWE ; PIN_20 ; 10 ; Clock enable ; no ; -- ; -- ;
+-----------+----------+---------+--------------+--------+----------------------+------------------+ +-----------+----------+---------+--------------+--------+----------------------+------------------+
@ -401,9 +388,9 @@ Note: User assignments will override these defaults. The user specified values a
; Addr[4] ; 21 ; ; Addr[4] ; 21 ;
; Addr[5] ; 20 ; ; Addr[5] ; 20 ;
; Addr[6] ; 19 ; ; Addr[6] ; 19 ;
; nDEVSEL ; 18 ;
; Addr[7] ; 18 ; ; Addr[7] ; 18 ;
; Addr[8] ; 17 ; ; Addr[8] ; 17 ;
; nDEVSEL ; 16 ;
; Addr[9] ; 16 ; ; Addr[9] ; 16 ;
; A[3] ; 15 ; ; A[3] ; 15 ;
; A[2] ; 15 ; ; A[2] ; 15 ;
@ -413,32 +400,31 @@ Note: User assignments will override these defaults. The user specified values a
; Addr[11] ; 14 ; ; Addr[11] ; 14 ;
; nIOSEL ; 13 ; ; nIOSEL ; 13 ;
; Addr[12] ; 13 ; ; Addr[12] ; 13 ;
; Bank[0] ; 13 ;
; nIOSTRB ; 12 ; ; nIOSTRB ; 12 ;
; Addr[13] ; 12 ; ; Addr[13] ; 12 ;
; Bank[1] ; 12 ;
; nWE ; 11 ;
; Addr[14] ; 11 ; ; Addr[14] ; 11 ;
; Bank[2] ; 11 ;
; ASel ; 11 ; ; ASel ; 11 ;
; nWE ; 10 ;
; Addr[15] ; 10 ; ; Addr[15] ; 10 ;
; Bank[3] ; 9 ;
; Addr[16] ; 9 ; ; Addr[16] ; 9 ;
; IOBank0 ; 8 ; ; IOBank0 ; 8 ;
; Addr[17] ; 8 ; ; Addr[17] ; 8 ;
; Bank[0] ; 8 ;
; BankWR_MC ; 8 ; ; BankWR_MC ; 8 ;
; AddrLWR_MC ; 8 ; ; AddrLWR_MC ; 8 ;
; AddrMWR_MC ; 8 ; ; AddrMWR_MC ; 8 ;
; RDOE~1 ; 8 ; ; RDOE~1 ; 8 ;
; DOE~5 ; 8 ; ; DOE~5 ; 8 ;
; Bank[4] ; 7 ;
; Addr[18] ; 7 ; ; Addr[18] ; 7 ;
; Bank[1] ; 7 ;
; RAMSEL_MC ; 7 ;
; REGEN ; 7 ; ; REGEN ; 7 ;
; D[3]~3 ; 6 ; ; D[3]~3 ; 6 ;
; D[2]~2 ; 6 ; ; D[2]~2 ; 6 ;
; D[1]~1 ; 6 ; ; D[1]~1 ; 6 ;
; D[0]~0 ; 6 ; ; D[0]~0 ; 6 ;
; Addr[19] ; 6 ; ; Addr[19] ; 6 ;
; Bank[2] ; 6 ;
; lpm_counter:Ref_rtl_0|dffs[3] ; 6 ; ; lpm_counter:Ref_rtl_0|dffs[3] ; 6 ;
; lpm_counter:Ref_rtl_0|dffs[2] ; 6 ; ; lpm_counter:Ref_rtl_0|dffs[2] ; 6 ;
; lpm_counter:Ref_rtl_0|dffs[0] ; 6 ; ; lpm_counter:Ref_rtl_0|dffs[0] ; 6 ;
@ -447,13 +433,13 @@ Note: User assignments will override these defaults. The user specified values a
; D[6]~6 ; 5 ; ; D[6]~6 ; 5 ;
; D[5]~5 ; 5 ; ; D[5]~5 ; 5 ;
; D[4]~4 ; 5 ; ; D[4]~4 ; 5 ;
; Bank[5] ; 5 ; ; Bank[3] ; 5 ;
; RAMSEL_MC ; 5 ;
; lpm_counter:Ref_rtl_0|dffs[1] ; 5 ; ; lpm_counter:Ref_rtl_0|dffs[1] ; 5 ;
; Bank[4] ; 4 ;
; Addr[20] ; 4 ; ; Addr[20] ; 4 ;
; AddrHWR_MC ; 4 ; ; AddrHWR_MC ; 4 ;
; C7M_2 ; 3 ; ; C7M_2 ; 3 ;
; Bank[6] ; 3 ; ; Bank[5] ; 3 ;
; Addr[22] ; 3 ; ; Addr[22] ; 3 ;
; Addr[21] ; 3 ; ; Addr[21] ; 3 ;
; IOROMEN ; 3 ; ; IOROMEN ; 3 ;
@ -461,6 +447,7 @@ Note: User assignments will override these defaults. The user specified values a
; PHI0seen ; 3 ; ; PHI0seen ; 3 ;
; PHI1reg ; 3 ; ; PHI1reg ; 3 ;
; PHI1in ; 2 ; ; PHI1in ; 2 ;
; Bank[6] ; 2 ;
; CASr ; 2 ; ; CASr ; 2 ;
; CASf ; 2 ; ; CASf ; 2 ;
; RD[7]~7 ; 1 ; ; RD[7]~7 ; 1 ;
@ -479,15 +466,10 @@ Note: User assignments will override these defaults. The user specified values a
; A[5] ; 1 ; ; A[5] ; 1 ;
; A[4] ; 1 ; ; A[4] ; 1 ;
; ~VCC~0 ; 1 ; ; ~VCC~0 ; 1 ;
; RA~111 ; 1 ; ; RA~110 ; 1 ;
; RA~106 ; 1 ; ; RA~103 ; 1 ;
; RA~105 ; 1 ; ; RA~96 ; 1 ;
; RA~100 ; 1 ; ; RA~89 ; 1 ;
; RA~99 ; 1 ;
; RA~94 ; 1 ;
; RA~93 ; 1 ;
; RA~88 ; 1 ;
; RA~87 ; 1 ;
; RA~82 ; 1 ; ; RA~82 ; 1 ;
; RA~81 ; 1 ; ; RA~81 ; 1 ;
; RA~75 ; 1 ; ; RA~75 ; 1 ;
@ -539,15 +521,15 @@ Note: User assignments will override these defaults. The user specified values a
; Other Routing Resource Type ; Usage ; ; Other Routing Resource Type ; Usage ;
+-----------------------------+--------------------+ +-----------------------------+--------------------+
; Output enables ; 2 / 6 ( 33 % ) ; ; Output enables ; 2 / 6 ( 33 % ) ;
; PIA buffers ; 198 / 288 ( 69 % ) ; ; PIA buffers ; 215 / 288 ( 75 % ) ;
; PIAs ; 228 / 288 ( 79 % ) ; ; PIAs ; 238 / 288 ( 83 % ) ;
+-----------------------------+--------------------+ +-----------------------------+--------------------+
+-----------------------------------------------------------------------------+ +-----------------------------------------------------------------------------+
; LAB External Interconnect ; ; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+ +-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 28.50) ; Number of LABs (Total = 8) ; ; LAB External Interconnects (Average = 29.75) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+ +-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ; ; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ; ; 3 - 5 ; 0 ;
@ -555,12 +537,12 @@ Note: User assignments will override these defaults. The user specified values a
; 9 - 11 ; 0 ; ; 9 - 11 ; 0 ;
; 12 - 14 ; 0 ; ; 12 - 14 ; 0 ;
; 15 - 17 ; 0 ; ; 15 - 17 ; 0 ;
; 18 - 20 ; 1 ; ; 18 - 20 ; 0 ;
; 21 - 23 ; 0 ; ; 21 - 23 ; 1 ;
; 24 - 26 ; 0 ; ; 24 - 26 ; 0 ;
; 27 - 29 ; 3 ; ; 27 - 29 ; 2 ;
; 30 - 32 ; 3 ; ; 30 - 32 ; 3 ;
; 33 - 35 ; 1 ; ; 33 - 35 ; 2 ;
+-----------------------------------------------+-----------------------------+ +-----------------------------------------------+-----------------------------+
@ -577,137 +559,125 @@ Note: User assignments will override these defaults. The user specified values a
; 5 ; 0 ; ; 5 ; 0 ;
; 6 ; 0 ; ; 6 ; 0 ;
; 7 ; 0 ; ; 7 ; 0 ;
; 8 ; 2 ; ; 8 ; 0 ;
; 9 ; 0 ; ; 9 ; 1 ;
; 10 ; 0 ; ; 10 ; 1 ;
; 11 ; 1 ; ; 11 ; 0 ;
; 12 ; 0 ; ; 12 ; 1 ;
; 13 ; 1 ; ; 13 ; 2 ;
; 14 ; 1 ; ; 14 ; 1 ;
; 15 ; 0 ; ; 15 ; 1 ;
; 16 ; 3 ; ; 16 ; 1 ;
+-----------------------------------------+-----------------------------+ +-----------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.63) ; Number of LABs (Total = 2) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 1 ;
+-------------------------------------------------+-----------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ; ; Logic Cell Interconnection ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ; ; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[2], S[1], S[0], Addr[7], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], RAMSELreg ; Dout[7]~95, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~111 ;
; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], RAMSELreg ; Dout[3]~71, Addr[11], Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~70 ;
; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[1], S[2], S[0], Addr[0], RAMSELreg ; Dout[0]~53, Addr[0], Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~70 ;
; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], RAMSELreg ; Dout[2]~65, Addr[11], Addr[16], Addr[17], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], RA~66, Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ;
; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], RAMSELreg ; Dout[1]~59, Addr[11], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], RA~63, Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ;
; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], RAMSELreg ; Dout[0]~53, Addr[11], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], RA~60, Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ;
; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], RAMSELreg ; Dout[7]~95, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[15], RA~93 ;
; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[2], S[1], S[0], Addr[6], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], RAMSELreg ; Dout[6]~89, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[6], Addr[14], Addr[15], RA~105 ;
; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[2], S[1], S[0], Addr[2], Addr[0], Addr[1], RAMSELreg ; Dout[2]~65, Addr[11], Addr[7], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~81 ;
; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[2], S[1], S[0], Addr[5], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], RAMSELreg ; Dout[5]~83, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~99 ;
; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[2], S[1], S[0], Addr[1], Addr[0], RAMSELreg ; Dout[1]~59, Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~75 ; ; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[2], S[1], S[0], Addr[1], Addr[0], RAMSELreg ; Dout[1]~59, Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~75 ;
; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], RAMSELreg ; Dout[5]~83, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[13], Addr[14], Addr[15], RA~81 ; ; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[2], S[1], S[0], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[7]~95, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~110 ;
; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], RAMSELreg ; Dout[4]~77, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~75 ; ; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[3]~71, Addr[11], Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~70 ;
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[2], S[1], S[0], Addr[4], Addr[0], Addr[1], Addr[2], Addr[3], RAMSELreg ; Dout[4]~77, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~93 ; ; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[2]~65, Addr[11], Addr[16], Addr[17], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], RA~66, Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ;
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], RAMSELreg ; Dout[6]~89, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[14], Addr[15], RA~87 ; ; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[2], S[1], S[0], Addr[0], RAMSELreg ; Dout[0]~53, Addr[0], Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~70 ;
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[2], S[1], S[0], Addr[3], Addr[0], Addr[1], Addr[2], RAMSELreg ; Dout[3]~71, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~87 ; ; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[1]~59, Addr[11], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], RA~63, Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ;
; B ; LC29 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[1], S[0], Addr[19], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], Addr[16], Addr[17], Addr[18], RAMSELreg ; Dout[3]~71, Addr[19], RA~60, Addr[20], Addr[21], Addr[22] ; ; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[7]~95, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[15], RA~89 ;
; B ; LC31 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[1], S[0], Addr[18], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], Addr[16], Addr[17], RAMSELreg ; Dout[2]~65, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~111 ; ; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[2], S[1], S[0], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[6]~89, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[6], Addr[14], Addr[15], RA~103 ;
; B ; LC19 ; C7M, nRES, D[2], BankWR_MC, S[0], S[2], S[1] ; RA~81, RA~82, RA~87, RA~88, RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ; ; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[0]~53, Addr[11], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], RA~60, Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ;
; B ; LC30 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~46 ; ; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[2], S[1], S[0], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[5]~83, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~96 ;
; B ; LC21 ; C7M, nRES, D[0], AddrHWR_MC, S[2], S[1], S[0], Addr[16], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], RAMSELreg ; Dout[0]~53, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~99 ; ; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[2], S[1], S[0], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[2]~65, Addr[11], Addr[7], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~81 ;
; B ; LC32 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ; ; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[5]~83, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[13], Addr[14], Addr[15], RA~81 ;
; B ; LC27 ; C7M, nRES, D[1], BankWR_MC, S[0], S[2], S[1] ; RA~75, RA~81, RA~82, RA~87, RA~88, RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ; ; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[4]~77, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~75 ;
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[2], S[1], S[0], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[4]~77, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~89 ;
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[6]~89, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[14], Addr[15], RA~82 ;
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[2], S[1], S[0], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[3]~71, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~82 ;
; B ; LC24 ; C7M, nRES, D[3], BankWR_MC, S[2], S[1], S[0] ; RA~82, RA~89, RA~96, RA~103, RA~110 ;
; B ; LC32 ; C7M, nRES, Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[20], S[2], RAMSELreg, S[1], S[0] ; Addr[20], RA~63, Addr[21], Addr[22] ;
; B ; LC20 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[1], S[0], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[3]~71, Addr[19], RA~60, Addr[20], Addr[21], Addr[22] ;
; B ; LC19 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[1], S[0], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[2]~65, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~110 ;
; B ; LC23 ; C7M, nRES, D[2], BankWR_MC, S[2], S[1], S[0] ; RA~81, RA~82, RA~89, RA~96, RA~103, RA~110 ;
; B ; LC29 ; C7M, nRES, D[0], AddrHWR_MC, S[2], S[1], S[0], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[0]~53, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~96 ;
; B ; LC17 ; ; nINH ; ; B ; LC17 ; ; nINH ;
; B ; LC22 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[1], S[0], Addr[17], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], Addr[16], RAMSELreg ; Dout[1]~59, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~105 ; ; B ; LC25 ; C7M, nRES, D[1], BankWR_MC, S[2], S[1], S[0] ; RA~75, RA~81, RA~82, RA~89, RA~96, RA~103, RA~110 ;
; B ; LC20 ; C7M, nRES, D[0], BankWR_MC, S[0], S[2], S[1] ; RA~70, RA~75, RA~81, RA~82, RA~87, RA~88, RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ; ; B ; LC31 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[1], S[0], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], RAMSELreg ; Dout[1]~59, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~103 ;
; B ; LC26 ; C7M, nRES, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[22], S[1], RAMSELreg, S[2], S[0] ; Addr[22], comb~51, comb~55 ; ; B ; LC27 ; C7M, nRES, D[0], BankWR_MC, S[2], S[1], S[0] ; RA~70, RA~75, RA~81, RA~82, RA~89, RA~96, RA~103, RA~110 ;
; B ; LC25 ; C7M, nRES, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[21], S[1], RAMSELreg, S[2], S[0] ; Addr[21], RA~66, Addr[22] ; ; B ; LC26 ; C7M, nRES, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[22], S[2], RAMSELreg, S[1], S[0] ; Addr[22], comb~51, comb~55 ;
; B ; LC28 ; C7M, nRES, D[3], BankWR_MC, S[0], S[2], S[1] ; RA~87, RA~88, RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ; ; B ; LC30 ; C7M, nRES, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[21], S[2], RAMSELreg, S[1], S[0] ; Addr[21], RA~66, Addr[22] ;
; B ; LC23 ; C7M, nRES, Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[20], S[1], RAMSELreg, S[2], S[0] ; Addr[20], RA~63, Addr[21], Addr[22] ; ; C ; LC34 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1] ; comb~48 ;
; C ; LC34 ; C7M, nRES, RAMSEL_MC, S[2], S[0], S[1], RAMSELreg ; RAMSELreg, Addr[0], Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15] ; ; C ; LC36 ; C7M, nRES, S[2], S[1], S[0], RAMSEL_MC, RAMSELreg ; RAMSELreg, Addr[0], Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15] ;
; C ; LC46 ; PHI1in ; PHI1b1_MC ; ; C ; LC46 ; PHI1in ; PHI1b1_MC ;
; C ; LC35 ; C7M_2 ; C7Mout ; ; C ; LC35 ; C7M_2 ; C7Mout ;
; C ; LC37 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, PHI1out, S[0], S[1], S[2] ; ; C ; LC37 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, PHI1out, S[0], S[1], S[2] ;
; C ; LC33 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; C ; LC38 ; RD[4], nDEVSEL, A[1], A[2], A[3], A[0], Addr[12], Addr[4] ; D[4] ; ; C ; LC38 ; RD[4], nDEVSEL, A[1], A[2], A[3], A[0], Addr[12], Addr[4] ; D[4] ;
; C ; LC40 ; RD[5], nDEVSEL, A[1], A[2], A[3], A[0], Addr[13], Addr[5] ; D[5] ; ; C ; LC40 ; RD[5], nDEVSEL, A[1], A[2], A[3], A[0], Addr[13], Addr[5] ; D[5] ;
; C ; LC43 ; RD[6], nDEVSEL, A[1], A[2], A[3], A[0], Addr[14], Addr[6] ; D[6] ; ; C ; LC43 ; RD[6], nDEVSEL, A[1], A[2], A[3], A[0], Addr[14], Addr[6] ; D[6] ;
; C ; LC45 ; RD[7], nDEVSEL, A[1], A[2], A[3], A[0], Addr[15], Addr[7] ; D[7] ; ; C ; LC45 ; RD[7], nDEVSEL, A[1], A[2], A[3], A[0], Addr[15], Addr[7] ; D[7] ;
; C ; LC36 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ; ; C ; LC39 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; C ; LC39 ; C7M, nRES, RAMSEL_MC, S[2], S[1] ; RA~60, RA~63, RA~66, RA~70, RA~75, RA~81, RA~87, RA~93, RA~99, RA~105, RA~111 ; ; C ; LC42 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
; C ; LC42 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1] ; comb~48 ; ; C ; LC41 ; nRES, S[2], S[1], S[0], nWE, C7M_2 ; comb~51, comb~55 ;
; C ; LC41 ; C7M, nRES, nIOSEL, S[0], S[2], S[1] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, IOBank0 ; ; C ; LC48 ; C7M, nRES, RAMSEL_MC, S[2], S[1] ; RA~60, RA~63, RA~66, RA~70, RA~75, RA~81, RA~82, RA~89, RA~96, RA~103, RA~110 ;
; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ; ; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ;
; D ; LC56 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ; ; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ;
; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ; ; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ;
; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ; ; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ;
; D ; LC53 ; Addr[22], CASf, nDEVSEL, CASr ; nCAS0 ; ; D ; LC56 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ;
; D ; LC51 ; Addr[22], CASf, nDEVSEL, CASr ; nCAS1 ;
; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ; ; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ;
; E ; LC80 ; IOBank0, Bank[0], nIOSEL, nIOSTRB, Addr[0], ASel, Addr[11] ; RA[0] ; ; D ; LC52 ; PHI1b6_MC ; PHI1b8_MC ;
; E ; LC72 ; Addr[10], ASel, Addr[21] ; RA[10] ; ; D ; LC51 ; Addr[22], CASf, RAMSEL_MC, CASr ; nCAS1 ;
; E ; LC68 ; PHI1b7_MC ; PHI1b9_MC ; ; D ; LC53 ; Addr[22], CASf, RAMSEL_MC, CASr ; nCAS0 ;
; D ; LC50 ; PHI1b7_MC ; PHI1b9_MC ;
; E ; LC67 ; nWE ; nROE ; ; E ; LC67 ; nWE ; nROE ;
; E ; LC70 ; PHI1b4_MC ; PHI1b6_MC ; ; E ; LC68 ; C7M, nRES, D[5], BankWR_MC, S[2], S[1], S[0] ; RA~96, RA~103, RA~110 ;
; E ; LC65 ; PHI1b5_MC ; PHI1b7_MC ; ; E ; LC79 ; C7M, nRES, D[4], BankWR_MC, S[2], S[1], S[0] ; RA~89, RA~96, RA~103, RA~110 ;
; E ; LC69 ; Addr[9], ASel, Addr[20] ; RA[9] ; ; E ; LC69 ; Addr[20], ASel, Addr[9] ; RA[9] ;
; E ; LC66 ; PHI1b6_MC ; PHI1b8_MC ; ; E ; LC77 ; IOBank0, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ;
; E ; LC77 ; IOBank0, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[5], ASel, Addr[16], RA~94 ; RA[5] ; ; E ; LC73 ; IOBank0, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ;
; E ; LC73 ; IOBank0, Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[3], ASel, Addr[14], RA~82 ; RA[3] ; ; E ; LC75 ; IOBank0, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2] ; RA[2] ;
; E ; LC75 ; IOBank0, Bank[2], Bank[1], nIOSEL, nIOSTRB, Bank[0], Addr[2], ASel, Addr[13] ; RA[2] ; ; E ; LC80 ; IOBank0, Bank[0], nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0] ; RA[0] ;
; E ; LC72 ; Addr[21], ASel, Addr[10] ; RA[10] ;
; F ; LC89 ; PHI1b0_MC ; PHI1b2_MC ;
; F ; LC95 ; PHI1b2_MC ; PHI1b4_MC ;
; F ; LC92 ; C7M, nRES, D[7], BankWR_MC, S[2], S[1], S[0] ; RA~110 ;
; F ; LC85 ; IOBank0, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ;
; F ; LC88 ; IOBank0, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ;
; F ; LC86 ; IOBank0, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ;
; F ; LC83 ; IOBank0, Bank[1], Bank[0], nIOSTRB, Addr[12], ASel, nIOSEL, Addr[1] ; RA[1] ;
; F ; LC93 ; RASr, RASf ; nRAS ; ; F ; LC93 ; RASr, RASf ; nRAS ;
; F ; LC91 ; Addr[8], ASel, Addr[19] ; RA[8] ; ; F ; LC84 ; C7M, nRES, nIOSEL, S[0], S[2], S[1] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, IOBank0 ;
; F ; LC91 ; Addr[19], ASel, Addr[8] ; RA[8] ;
; F ; LC82 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~46 ;
; F ; LC94 ; D[7] ; RD[7] ; ; F ; LC94 ; D[7] ; RD[7] ;
; F ; LC82 ; C7M, nRES, D[5], BankWR_MC, S[0], S[2], S[1] ; RA~99, RA~100, RA~105, RA~106, RA~111 ; ; F ; LC90 ; PHI1b4_MC ; PHI1b6_MC ;
; F ; LC85 ; IOBank0, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[4], ASel, Addr[15], RA~88 ; RA[4] ; ; F ; LC96 ; PHI1b3_MC ; PHI1b5_MC ;
; F ; LC88 ; IOBank0, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[6], ASel, Addr[17], RA~100 ; RA[6] ; ; F ; LC87 ; PHI1b1_MC ; PHI1b3_MC ;
; F ; LC86 ; IOBank0, Bank[7], Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[7], ASel, Addr[18], RA~106 ; RA[7] ; ; G ; LC105 ; D[3] ; RD[3] ;
; F ; LC83 ; IOBank0, Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[1], ASel, Addr[12] ; RA[1] ;
; G ; LC109 ; D[1] ; RD[1] ;
; G ; LC101 ; D[4] ; RD[4] ; ; G ; LC101 ; D[4] ; RD[4] ;
; G ; LC97 ; D[5] ; RD[5] ; ; G ; LC97 ; D[5] ; RD[5] ;
; G ; LC111 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ; ; G ; LC98 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; ASel, RASr, RAMSELreg, CASr, RASf, comb~51, comb~55 ;
; G ; LC102 ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~46 ;
; G ; LC104 ; nDEVSEL, nIOSEL, nIOSTRB, nWE ; nRWE ; ; G ; LC104 ; nDEVSEL, nIOSEL, nIOSTRB, nWE ; nRWE ;
; G ; LC108 ; C7M, nRES, D[6], BankWR_MC, S[0], S[2], S[1] ; RA~105, RA~106, RA~111 ; ; G ; LC112 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19] ;
; G ; LC107 ; D[2] ; RD[2] ; ; G ; LC111 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[11], Addr[8], Addr[9], Addr[10], Addr[12], Addr[13], Addr[14], Addr[15] ;
; G ; LC106 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[7], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6] ;
; G ; LC110 ; C7M, nRES, D[6], BankWR_MC, S[2], S[1], S[0] ; RA~103, RA~110 ;
; G ; LC99 ; D[6] ; RD[6] ; ; G ; LC99 ; D[6] ; RD[6] ;
; G ; LC112 ; C7M, nRES, D[7], BankWR_MC, S[0], S[2], S[1] ; RA~111 ; ; G ; LC102 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[2], S[1], S[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~70, RA~75, RA~81, RA~82, RA~89, RA~96, RA~103, RA~110 ;
; G ; LC103 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[0], S[2], S[1], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~70, RA~75, RA~81, RA~87, RA~93, RA~99, RA~105, RA~111 ; ; G ; LC107 ; D[2] ; RD[2] ;
; G ; LC98 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; ASel, RASr, RAMSELreg, CASr, RASf ; ; G ; LC109 ; D[1] ; RD[1] ;
; G ; LC105 ; D[3] ; RD[3] ; ; G ; LC103 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ;
; G ; LC110 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19] ; ; H ; LC120 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
; G ; LC106 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[11], Addr[8], Addr[9], Addr[10], Addr[12], Addr[13], Addr[14], Addr[15] ;
; G ; LC100 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[7], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6] ;
; H ; LC115 ; D[0] ; RD[0] ; ; H ; LC115 ; D[0] ; RD[0] ;
; H ; LC126 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ; ; H ; LC116 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC128 ; C7M, nRES, S[1], S[0], S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], RAMSEL_MC ; comb~51, comb~55 ; ; H ; LC127 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC119 ; nRES, S[0], S[2], S[1], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], nWE, RAMSEL_MC, C7M_2 ; comb~48 ; ; H ; LC124 ; PHI1b5_MC ; PHI1b7_MC ;
; H ; LC123 ; PHI1b2_MC ; PHI1b4_MC ; ; H ; LC126 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[2], S[1] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ;
; H ; LC124 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ; ; H ; LC114 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ;
; H ; LC121 ; PHI1b1_MC ; PHI1b3_MC ; ; H ; LC122 ; nRES, RAMSEL_MC, S[2], S[1], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], C7M_2 ; comb~48 ;
; H ; LC114 ; C7M, nRES, D[4], BankWR_MC, S[0], S[2], S[1] ; RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ; ; H ; LC119 ; C7M, nRES, S[1], S[0], S[2], RAMSEL_MC, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0] ; comb~51, comb~55 ;
; H ; LC118 ; PHI1b0_MC ; PHI1b2_MC ; ; H ; LC128 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC113 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ; ; H ; LC125 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
; H ; LC120 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ; ; H ; LC117 ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~46 ;
; H ; LC125 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ; ; H ; LC113 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ;
; H ; LC117 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ;
; H ; LC122 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ;
; H ; LC127 ; nRES, S[2], S[1], S[0], nWE, C7M_2 ; comb~51, comb~55 ;
; H ; LC116 ; PHI1b3_MC ; PHI1b5_MC ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@ -731,10 +701,10 @@ Note: User assignments will override these defaults. The user specified values a
+-----------------+ +-----------------+
Warning (20028): Parallel compilation is not licensed and has been disabled Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM" Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM"
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning Info: Quartus II 32-bit Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4708 megabytes Info: Peak virtual memory: 287 megabytes
Info: Processing ended: Sun Sep 01 20:44:15 2019 Info: Processing ended: Mon Sep 02 01:41:31 2019
Info: Elapsed time: 00:00:01 Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:01 Info: Total CPU time (on all processors): 00:00:04

4
cpld/output_files/GR8RAM.fit.summary
View File

@ -1,5 +1,5 @@
Fitter Status : Successful - Sun Sep 01 20:44:15 2019 Fitter Status : Successful - Mon Sep 02 01:41:31 2019
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX7000S Family : MAX7000S

94
cpld/output_files/GR8RAM.flow.rpt
View File

@ -1,6 +1,6 @@
Flow report for GR8RAM Flow report for GR8RAM
Sun Sep 01 20:44:17 2019 Mon Sep 02 01:41:42 2019
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
--------------------- ---------------------
@ -40,8 +40,8 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+ +-----------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+---------------------------+-------------------------------------------------+ +---------------------------+-------------------------------------------------+
; Flow Status ; Successful - Sun Sep 01 20:44:16 2019 ; ; Flow Status ; Successful - Mon Sep 02 01:41:35 2019 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX7000S ; ; Family ; MAX7000S ;
@ -57,39 +57,39 @@ applicable agreement for further details.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 09/01/2019 20:44:13 ; ; Start date & time ; 09/02/2019 01:41:21 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
+-------------------+---------------------+ +-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ; ; Flow Non-Default Global Settings ;
+--------------------------------------------+---------------------------------+---------------+-------------+------------+ +--------------------------------------------+-----------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+--------------------------------------------+---------------------------------+---------------+-------------+------------+ +--------------------------------------------+-----------------------------+---------------+-------------+------------+
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ; ; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ;
; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ; ; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 207120313862967.156738505316020 ; -- ; -- ; -- ; ; COMPILER_SIGNATURE_ID ; 52238299365.156740288102732 ; -- ; -- ; -- ;
; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ; ; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ;
; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ; ; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ;
; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ; ; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ;
; EXTRACT_VHDL_STATE_MACHINES ; Off ; On ; -- ; -- ; ; EXTRACT_VHDL_STATE_MACHINES ; Off ; On ; -- ; -- ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ; ; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ; ; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ;
; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ; ; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ;
; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ; ; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ;
; PRE_MAPPING_RESYNTHESIS ; On ; Off ; -- ; -- ; ; PRE_MAPPING_RESYNTHESIS ; On ; Off ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ; ; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ;
; STATE_MACHINE_PROCESSING ; User-Encoded ; Auto ; -- ; -- ; ; STATE_MACHINE_PROCESSING ; User-Encoded ; Auto ; -- ; -- ;
; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ; ; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ;
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; ; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
+--------------------------------------------+---------------------------------+---------------+-------------+------------+ +--------------------------------------------+-----------------------------+---------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------+
@ -97,24 +97,24 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4587 MB ; 00:00:01 ; ; Analysis & Synthesis ; 00:00:08 ; 1.0 ; 303 MB ; 00:00:08 ;
; Fitter ; 00:00:01 ; 1.0 ; 4708 MB ; 00:00:00 ; ; Fitter ; 00:00:05 ; 1.0 ; 287 MB ; 00:00:04 ;
; Assembler ; 00:00:00 ; 1.0 ; 4520 MB ; 00:00:00 ; ; Assembler ; 00:00:03 ; 1.0 ; 275 MB ; 00:00:03 ;
; TimeQuest Timing Analyzer ; 00:00:00 ; 1.0 ; 4530 MB ; 00:00:00 ; ; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 263 MB ; 00:00:05 ;
; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ; ; Total ; 00:00:21 ; -- ; -- ; 00:00:20 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------+
; Flow OS Summary ; ; Flow OS Summary ;
+---------------------------+------------------+-----------+------------+----------------+ +---------------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+ +---------------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; ; Analysis & Synthesis ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
; Fitter ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; ; Fitter ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
; Assembler ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; ; Assembler ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
; TimeQuest Timing Analyzer ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; ; TimeQuest Timing Analyzer ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
+---------------------------+------------------+-----------+------------+----------------+ +---------------------------+------------------+------------+------------+----------------+
------------ ------------

2
cpld/output_files/GR8RAM.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info> <sld_project_info>
<project> <project>
<hash md5_digest_80b="77f5507f581f4534370c"/> <hash md5_digest_80b="94a5ca8ad1222b1b1963"/>
</project> </project>
<file_info> <file_info>
<file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/> <file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>

70
cpld/output_files/GR8RAM.map.rpt
View File

@ -1,6 +1,6 @@
Analysis & Synthesis report for GR8RAM Analysis & Synthesis report for GR8RAM
Sun Sep 01 20:44:14 2019 Mon Sep 02 01:41:25 2019
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
--------------------- ---------------------
@ -9,15 +9,14 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
1. Legal Notice 1. Legal Notice
2. Analysis & Synthesis Summary 2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings 3. Analysis & Synthesis Settings
4. Parallel Compilation 4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis Resource Utilization by Entity 7. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0
8. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0 8. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0
9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0 9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3
10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3 10. Analysis & Synthesis Messages
11. Analysis & Synthesis Messages 11. Analysis & Synthesis Suppressed Messages
12. Analysis & Synthesis Suppressed Messages
@ -43,8 +42,8 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+ +-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Sep 01 20:44:14 2019 ; ; Analysis & Synthesis Status ; Successful - Mon Sep 02 01:41:25 2019 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX7000S ; ; Family ; MAX7000S ;
@ -117,23 +116,12 @@ applicable agreement for further details.
+----------------------------------------------------------------------------+-----------------+---------------+ +----------------------------------------------------------------------------+-----------------+---------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ; ; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+ +----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+ +----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
; GR8RAM.v ; yes ; User Verilog HDL File ; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ; ; ; GR8RAM.v ; yes ; User Verilog HDL File ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ; ;
; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ; ; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ;
; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ; ; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ; ; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
@ -166,11 +154,10 @@ Parallel compilation was disabled, but you have multiple processors available. E
; Logic cells ; 102 ; ; Logic cells ; 102 ;
; Total registers ; 50 ; ; Total registers ; 50 ;
; I/O pins ; 63 ; ; I/O pins ; 63 ;
; Shareable expanders ; 5 ;
; Maximum fan-out node ; nRES ; ; Maximum fan-out node ; nRES ;
; Maximum fan-out ; 50 ; ; Maximum fan-out ; 50 ;
; Total fan-out ; 993 ; ; Total fan-out ; 962 ;
; Average fan-out ; 5.84 ; ; Average fan-out ; 5.83 ;
+----------------------+----------------------+ +----------------------+----------------------+
@ -271,18 +258,18 @@ Note: In order to hide this table in the UI and the text report file, please set
; Analysis & Synthesis Messages ; ; Analysis & Synthesis Messages ;
+-------------------------------+ +-------------------------------+
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun Sep 01 20:44:13 2019 Info: Processing started: Mon Sep 02 01:41:17 2019
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Warning (20028): Parallel compilation is not licensed and has been disabled Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
Info (12023): Found entity 1: GR8RAM Info (12023): Found entity 1: GR8RAM
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (3) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(137): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(135): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(162): truncated value with size 32 to match size of target (23) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (23)
Info (19000): Inferred 1 megafunctions from design logic Info (19000): Inferred 1 megafunctions from design logic
Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0" Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0"
Info (278001): Inferred 2 megafunctions from design logic Info (278001): Inferred 2 megafunctions from design logic
@ -328,23 +315,22 @@ Warning (21074): Design contains 8 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "A[13]" Warning (15610): No output dependent on input pin "A[13]"
Warning (15610): No output dependent on input pin "A[14]" Warning (15610): No output dependent on input pin "A[14]"
Warning (15610): No output dependent on input pin "A[15]" Warning (15610): No output dependent on input pin "A[15]"
Info (21057): Implemented 170 device resources after synthesis - the final resource count might be different Info (21057): Implemented 165 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 27 input pins Info (21058): Implemented 27 input pins
Info (21059): Implemented 20 output pins Info (21059): Implemented 20 output pins
Info (21060): Implemented 16 bidirectional pins Info (21060): Implemented 16 bidirectional pins
Info (21063): Implemented 102 macrocells Info (21063): Implemented 102 macrocells
Info (21073): Implemented 5 shareable expanders Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 14 warnings
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings Info: Peak virtual memory: 303 megabytes
Info: Peak virtual memory: 4587 megabytes Info: Processing ended: Mon Sep 02 01:41:25 2019
Info: Processing ended: Sun Sep 01 20:44:14 2019 Info: Elapsed time: 00:00:08
Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:08
Info: Total CPU time (on all processors): 00:00:01
+------------------------------------------+ +------------------------------------------+
; Analysis & Synthesis Suppressed Messages ; ; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+ +------------------------------------------+
The suppressed messages can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg. The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.

6
cpld/output_files/GR8RAM.map.smsg
View File

@ -1,3 +1,3 @@
Warning (10273): Verilog HDL warning at GR8RAM.v(41): extended using "x" or "z" Warning (10273): Verilog HDL warning at GR8RAM.v(40): extended using "x" or "z"
Warning (10273): Verilog HDL warning at GR8RAM.v(49): extended using "x" or "z" Warning (10273): Verilog HDL warning at GR8RAM.v(48): extended using "x" or "z"
Warning (10268): Verilog HDL information at GR8RAM.v(177): always construct contains both blocking and non-blocking assignments Warning (10268): Verilog HDL information at GR8RAM.v(175): always construct contains both blocking and non-blocking assignments

4
cpld/output_files/GR8RAM.map.summary
View File

@ -1,5 +1,5 @@
Analysis & Synthesis Status : Successful - Sun Sep 01 20:44:14 2019 Analysis & Synthesis Status : Successful - Mon Sep 02 01:41:25 2019
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX7000S Family : MAX7000S

2
cpld/output_files/GR8RAM.pin
View File

@ -56,7 +56,7 @@
-- Pin directions (input, output or bidir) are based on device operating in user mode. -- Pin directions (input, output or bidir) are based on device operating in user mode.
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
CHIP "GR8RAM" ASSIGNED TO AN: EPM7128SLC84-15 CHIP "GR8RAM" ASSIGNED TO AN: EPM7128SLC84-15
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment

BIN
cpld/output_files/GR8RAM.pof
View File

Binary file not shown.

392
cpld/output_files/GR8RAM.sta.rpt
View File

@ -1,6 +1,6 @@
TimeQuest Timing Analyzer report for GR8RAM TimeQuest Timing Analyzer report for GR8RAM
Sun Sep 01 20:44:17 2019 Mon Sep 02 01:41:42 2019
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
--------------------- ---------------------
@ -8,36 +8,35 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
--------------------- ---------------------
1. Legal Notice 1. Legal Notice
2. TimeQuest Timing Analyzer Summary 2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation 3. Clocks
4. Clocks 4. Fmax Summary
5. Fmax Summary 5. Setup Summary
6. Setup Summary 6. Hold Summary
7. Hold Summary 7. Recovery Summary
8. Recovery Summary 8. Removal Summary
9. Removal Summary 9. Minimum Pulse Width Summary
10. Minimum Pulse Width Summary 10. Setup: 'C7M'
11. Setup: 'C7M' 11. Setup: 'C7M_2'
12. Setup: 'C7M_2' 12. Hold: 'C7M_2'
13. Hold: 'C7M_2' 13. Hold: 'C7M'
14. Hold: 'C7M' 14. Minimum Pulse Width: 'C7M_2'
15. Minimum Pulse Width: 'C7M_2' 15. Minimum Pulse Width: 'C7M'
16. Minimum Pulse Width: 'C7M' 16. Setup Times
17. Setup Times 17. Hold Times
18. Hold Times 18. Clock to Output Times
19. Clock to Output Times 19. Minimum Clock to Output Times
20. Minimum Clock to Output Times 20. Propagation Delay
21. Propagation Delay 21. Minimum Propagation Delay
22. Minimum Propagation Delay 22. Output Enable Times
23. Output Enable Times 23. Minimum Output Enable Times
24. Minimum Output Enable Times 24. Output Disable Times
25. Output Disable Times 25. Minimum Output Disable Times
26. Minimum Output Disable Times 26. Setup Transfers
27. Setup Transfers 27. Hold Transfers
28. Hold Transfers 28. Report TCCS
29. Report TCCS 29. Report RSKM
30. Report RSKM 30. Unconstrained Paths
31. Unconstrained Paths 31. TimeQuest Timing Analyzer Messages
32. TimeQuest Timing Analyzer Messages
@ -73,17 +72,6 @@ applicable agreement for further details.
+--------------------+-------------------------------------------------------------------+ +--------------------+-------------------------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ; ; Clocks ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
@ -109,7 +97,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+---------+---------------+ +-------+---------+---------------+
; Clock ; Slack ; End Point TNS ; ; Clock ; Slack ; End Point TNS ;
+-------+---------+---------------+ +-------+---------+---------------+
; C7M ; -47.000 ; -1802.000 ; ; C7M ; -47.000 ; -1763.000 ;
; C7M_2 ; -27.500 ; -33.000 ; ; C7M_2 ; -27.500 ; -33.000 ;
+-------+---------+---------------+ +-------+---------+---------------+
@ -153,24 +141,24 @@ No paths to report.
+---------+-----------+-----------+--------------+-------------+--------------+------------+------------+ +---------+-----------+-----------+--------------+-------------+--------------+------------+------------+
; -47.000 ; REGEN ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[13] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[12] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[11] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[18] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Addr[18] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[10] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[11] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[19] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Addr[19] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Addr[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[10] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Addr[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Addr[12] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Addr[13] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Addr[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Addr[8] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Addr[8] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; ASel ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; ASel ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; RASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; RASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
@ -183,21 +171,6 @@ No paths to report.
; -47.000 ; REGEN ; Bank[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Bank[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Bank[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Bank[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -47.000 ; REGEN ; Bank[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; Bank[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
; -25.000 ; PHI1reg ; S[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; PHI0seen ; S[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; S[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; S[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; S[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; PHI1reg ; S[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; PHI0seen ; S[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; S[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; S[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; S[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; S[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; S[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; S[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[0] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[2] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[1] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
@ -207,50 +180,65 @@ No paths to report.
; -25.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[2] ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[1] ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; RAMSELreg ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; RAMSELreg ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[2] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[0] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; RAMSELreg ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; RAMSELreg ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[2] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[1] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[0] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[9] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[0] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[8] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[1] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[7] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[2] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[6] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[3] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[5] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[4] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[4] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[5] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[3] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[6] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[2] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[7] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[1] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[8] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[0] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[9] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; RAMSELreg ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[10] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[2] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[11] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[1] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[12] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[0] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[13] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[16] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[14] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[15] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; RAMSELreg ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[14] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[13] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[12] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[11] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[10] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[0] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[9] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[1] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[8] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[2] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[7] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[3] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[6] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[4] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[5] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[5] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[4] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[6] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[3] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; RAMSELreg ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[2] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[1] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; Addr[0] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; RAMSELreg ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[14] ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ; -25.000 ; S[2] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[17] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[16] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[15] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[14] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[13] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[12] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[11] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[10] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[9] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[8] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[7] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[6] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; Addr[5] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
+---------+-----------+-----------+--------------+-------------+--------------+------------+------------+ +---------+-----------+-----------+--------------+-------------+--------------+------------+------------+
@ -263,13 +251,13 @@ No paths to report.
; -5.500 ; S[2] ; CASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; ; -5.500 ; S[2] ; CASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ;
; -5.500 ; S[1] ; CASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; ; -5.500 ; S[1] ; CASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ;
; -5.500 ; S[0] ; CASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; ; -5.500 ; S[0] ; CASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ;
; -5.500 ; S[0] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ;
; -5.500 ; S[2] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; ; -5.500 ; S[2] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ;
; -5.500 ; S[1] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; ; -5.500 ; S[1] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ;
; -5.500 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; ; -5.500 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ;
; -5.500 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; ; -5.500 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ;
; -5.500 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; ; -5.500 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ;
; -5.500 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; ; -5.500 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ;
; -5.500 ; S[0] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ;
+---------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ +---------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+
@ -281,13 +269,13 @@ No paths to report.
; -1.500 ; S[2] ; CASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; ; -1.500 ; S[2] ; CASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ;
; -1.500 ; S[1] ; CASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; ; -1.500 ; S[1] ; CASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ;
; -1.500 ; S[0] ; CASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; ; -1.500 ; S[0] ; CASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ;
; -1.500 ; S[0] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ;
; -1.500 ; S[2] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; ; -1.500 ; S[2] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ;
; -1.500 ; S[1] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; ; -1.500 ; S[1] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ;
; -1.500 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; ; -1.500 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ;
; -1.500 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; ; -1.500 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ;
; -1.500 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; ; -1.500 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ;
; -1.500 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; ; -1.500 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ;
; -1.500 ; S[0] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ;
; 20.500 ; REGEN ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 44.000 ; ; 20.500 ; REGEN ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 44.000 ;
+--------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ +--------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+
@ -297,27 +285,42 @@ No paths to report.
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ +--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ +--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
; 5.000 ; PHI1reg ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI0seen ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[2] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI1reg ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI0seen ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[2] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[2] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; RAMSELreg ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; RAMSELreg ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[9] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[14] ; Addr[14] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[6] ; Addr[6] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[13] ; Addr[13] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[5] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[12] ; Addr[12] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[4] ; Addr[4] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[11] ; Addr[11] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[16] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[16] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[17] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[17] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[1] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[2] ; Addr[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[18] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[18] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[10] ; Addr[10] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[11] ; Addr[11] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[19] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[19] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[3] ; Addr[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[3] ; Addr[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[10] ; Addr[10] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[4] ; Addr[4] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[2] ; Addr[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[12] ; Addr[12] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[9] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[13] ; Addr[13] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[1] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[5] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[6] ; Addr[6] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[14] ; Addr[14] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; Addr[8] ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[8] ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
@ -346,21 +349,6 @@ No paths to report.
; 5.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
; 18.000 ; PHI1reg ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; PHI0seen ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; PHI1reg ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; PHI0seen ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
@ -369,34 +357,34 @@ No paths to report.
; 18.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[2] ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[1] ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[0] ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[2] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; RAMSELreg ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; RAMSELreg ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[2] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[1] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[0] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[0] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[8] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[1] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[7] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[2] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[6] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[3] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[5] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[4] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[4] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[5] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[3] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[6] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[2] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[7] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[1] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[8] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[0] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[9] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; RAMSELreg ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[10] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[2] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[11] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[1] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[12] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[0] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[13] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[15] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; Addr[14] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[14] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; RAMSELreg ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[13] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[12] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[11] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[10] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ +--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
@ -413,8 +401,8 @@ No paths to report.
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; C7M_2|dataout ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; C7M_2|dataout ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M_2 ; Rise ; CASf|[4] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M_2 ; Rise ; CASf|[4] ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; CASf|[4] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; CASf|[4] ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M_2 ; Rise ; RASf|[9] ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M_2 ; Rise ; RASf|[8] ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; RASf|[9] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; RASf|[8] ;
+--------+--------------+----------------+------------------+-------+------------+---------------+ +--------+--------------+----------------+------------------+-------+------------+---------------+
@ -552,7 +540,7 @@ No paths to report.
; D[5] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; ; D[5] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; D[6] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; ; D[6] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; D[7] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; ; D[7] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; PHI1in ; C7M ; 244.000 ; 244.000 ; Rise ; C7M ; ; PHI1in ; C7M ; 101.000 ; 101.000 ; Rise ; C7M ;
; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ; ; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
; nIOSEL ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; ; nIOSEL ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
; nIOSTRB ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; ; nIOSTRB ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
@ -593,7 +581,7 @@ No paths to report.
; D[5] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; ; D[5] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; D[6] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; ; D[6] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; D[7] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; ; D[7] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; PHI1in ; C7M ; -38.000 ; -38.000 ; Rise ; C7M ; ; PHI1in ; C7M ; -12.000 ; -12.000 ; Rise ; C7M ;
; nDEVSEL ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; ; nDEVSEL ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; nIOSEL ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; ; nIOSEL ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
; nIOSTRB ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; ; nIOSTRB ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
@ -622,20 +610,20 @@ No paths to report.
; D[5] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; D[5] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; D[6] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; D[6] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; D[7] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; D[7] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[*] ; C7M ; 29.000 ; 29.000 ; Rise ; C7M ; ; RA[*] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[0] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; RA[0] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[1] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; RA[1] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[2] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; RA[2] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[3] ; C7M ; 29.000 ; 29.000 ; Rise ; C7M ; ; RA[3] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[4] ; C7M ; 29.000 ; 29.000 ; Rise ; C7M ; ; RA[4] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[5] ; C7M ; 29.000 ; 29.000 ; Rise ; C7M ; ; RA[5] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[6] ; C7M ; 29.000 ; 29.000 ; Rise ; C7M ; ; RA[6] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[7] ; C7M ; 29.000 ; 29.000 ; Rise ; C7M ; ; RA[7] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[8] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; RA[8] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[9] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; RA[9] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; RA[10] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; RA[10] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; nCAS0 ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; nCAS0 ; C7M ; 43.000 ; 43.000 ; Rise ; C7M ;
; nCAS1 ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; nCAS1 ; C7M ; 43.000 ; 43.000 ; Rise ; C7M ;
; nRAS ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; nRAS ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; nRCS ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; nRCS ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
; C7Mout ; C7M_2 ; 19.000 ; 19.000 ; Rise ; C7M_2 ; ; C7Mout ; C7M_2 ; 19.000 ; 19.000 ; Rise ; C7M_2 ;
@ -697,6 +685,8 @@ No paths to report.
; A[0] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[0] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[0] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[0] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; nCAS0 ; 41.000 ; ; ; 41.000 ;
; A[0] ; nCAS1 ; 41.000 ; ; ; 41.000 ;
; A[1] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[1] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[1] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[1] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
@ -705,6 +695,8 @@ No paths to report.
; A[1] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[1] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[1] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[1] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; nCAS0 ; 41.000 ; ; ; 41.000 ;
; A[1] ; nCAS1 ; 41.000 ; ; ; 41.000 ;
; A[2] ; D[0] ; ; 19.000 ; 19.000 ; ; ; A[2] ; D[0] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[1] ; ; 19.000 ; 19.000 ; ; ; A[2] ; D[1] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[2] ; ; 19.000 ; 19.000 ; ; ; A[2] ; D[2] ; ; 19.000 ; 19.000 ; ;
@ -713,6 +705,8 @@ No paths to report.
; A[2] ; D[5] ; ; 19.000 ; 19.000 ; ; ; A[2] ; D[5] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[6] ; ; 19.000 ; 19.000 ; ; ; A[2] ; D[6] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[7] ; ; 19.000 ; 19.000 ; ; ; A[2] ; D[7] ; ; 19.000 ; 19.000 ; ;
; A[2] ; nCAS0 ; ; 41.000 ; 41.000 ; ;
; A[2] ; nCAS1 ; ; 41.000 ; 41.000 ; ;
; A[3] ; D[0] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[0] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[1] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[1] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[2] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[2] ; ; 19.000 ; 19.000 ; ;
@ -721,6 +715,8 @@ No paths to report.
; A[3] ; D[5] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[5] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[6] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[6] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[7] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[7] ; ; 19.000 ; 19.000 ; ;
; A[3] ; nCAS0 ; ; 41.000 ; 41.000 ; ;
; A[3] ; nCAS1 ; ; 41.000 ; 41.000 ; ;
; D[0] ; RD[0] ; 19.000 ; ; ; 19.000 ; ; D[0] ; RD[0] ; 19.000 ; ; ; 19.000 ;
; D[1] ; RD[1] ; 19.000 ; ; ; 19.000 ; ; D[1] ; RD[1] ; 19.000 ; ; ; 19.000 ;
; D[2] ; RD[2] ; 19.000 ; ; ; 19.000 ; ; D[2] ; RD[2] ; 19.000 ; ; ; 19.000 ;
@ -729,7 +725,7 @@ No paths to report.
; D[5] ; RD[5] ; 19.000 ; ; ; 19.000 ; ; D[5] ; RD[5] ; 19.000 ; ; ; 19.000 ;
; D[6] ; RD[6] ; 19.000 ; ; ; 19.000 ; ; D[6] ; RD[6] ; 19.000 ; ; ; 19.000 ;
; D[7] ; RD[7] ; 19.000 ; ; ; 19.000 ; ; D[7] ; RD[7] ; 19.000 ; ; ; 19.000 ;
; PHI1in ; PHI1out ; 230.000 ; ; ; 230.000 ; ; PHI1in ; PHI1out ; 100.000 ; ; ; 100.000 ;
; RD[0] ; D[0] ; 19.000 ; ; ; 19.000 ; ; RD[0] ; D[0] ; 19.000 ; ; ; 19.000 ;
; RD[1] ; D[1] ; 19.000 ; ; ; 19.000 ; ; RD[1] ; D[1] ; 19.000 ; ; ; 19.000 ;
; RD[2] ; D[2] ; 19.000 ; ; ; 19.000 ; ; RD[2] ; D[2] ; 19.000 ; ; ; 19.000 ;
@ -746,8 +742,8 @@ No paths to report.
; nDEVSEL ; D[5] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; ; nDEVSEL ; D[5] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ;
; nDEVSEL ; D[6] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; ; nDEVSEL ; D[6] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ;
; nDEVSEL ; D[7] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; ; nDEVSEL ; D[7] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ;
; nDEVSEL ; nCAS0 ; ; 19.000 ; 19.000 ; ; ; nDEVSEL ; nCAS0 ; ; 41.000 ; 41.000 ; ;
; nDEVSEL ; nCAS1 ; ; 19.000 ; 19.000 ; ; ; nDEVSEL ; nCAS1 ; ; 41.000 ; 41.000 ; ;
; nDEVSEL ; nRWE ; 19.000 ; ; ; 19.000 ; ; nDEVSEL ; nRWE ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; D[0] ; ; 26.000 ; 26.000 ; ; ; nIOSEL ; D[0] ; ; 26.000 ; 26.000 ; ;
; nIOSEL ; D[1] ; ; 26.000 ; 26.000 ; ; ; nIOSEL ; D[1] ; ; 26.000 ; 26.000 ; ;
@ -819,6 +815,8 @@ No paths to report.
; A[0] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[0] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[0] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[0] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[0] ; nCAS0 ; 41.000 ; ; ; 41.000 ;
; A[0] ; nCAS1 ; 41.000 ; ; ; 41.000 ;
; A[1] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[1] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[1] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[1] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
@ -827,6 +825,8 @@ No paths to report.
; A[1] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[1] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[1] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; A[1] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; A[1] ; nCAS0 ; 41.000 ; ; ; 41.000 ;
; A[1] ; nCAS1 ; 41.000 ; ; ; 41.000 ;
; A[2] ; D[0] ; ; 19.000 ; 19.000 ; ; ; A[2] ; D[0] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[1] ; ; 19.000 ; 19.000 ; ; ; A[2] ; D[1] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[2] ; ; 19.000 ; 19.000 ; ; ; A[2] ; D[2] ; ; 19.000 ; 19.000 ; ;
@ -835,6 +835,8 @@ No paths to report.
; A[2] ; D[5] ; ; 19.000 ; 19.000 ; ; ; A[2] ; D[5] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[6] ; ; 19.000 ; 19.000 ; ; ; A[2] ; D[6] ; ; 19.000 ; 19.000 ; ;
; A[2] ; D[7] ; ; 19.000 ; 19.000 ; ; ; A[2] ; D[7] ; ; 19.000 ; 19.000 ; ;
; A[2] ; nCAS0 ; ; 41.000 ; 41.000 ; ;
; A[2] ; nCAS1 ; ; 41.000 ; 41.000 ; ;
; A[3] ; D[0] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[0] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[1] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[1] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[2] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[2] ; ; 19.000 ; 19.000 ; ;
@ -843,6 +845,8 @@ No paths to report.
; A[3] ; D[5] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[5] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[6] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[6] ; ; 19.000 ; 19.000 ; ;
; A[3] ; D[7] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[7] ; ; 19.000 ; 19.000 ; ;
; A[3] ; nCAS0 ; ; 41.000 ; 41.000 ; ;
; A[3] ; nCAS1 ; ; 41.000 ; 41.000 ; ;
; D[0] ; RD[0] ; 19.000 ; ; ; 19.000 ; ; D[0] ; RD[0] ; 19.000 ; ; ; 19.000 ;
; D[1] ; RD[1] ; 19.000 ; ; ; 19.000 ; ; D[1] ; RD[1] ; 19.000 ; ; ; 19.000 ;
; D[2] ; RD[2] ; 19.000 ; ; ; 19.000 ; ; D[2] ; RD[2] ; 19.000 ; ; ; 19.000 ;
@ -851,7 +855,7 @@ No paths to report.
; D[5] ; RD[5] ; 19.000 ; ; ; 19.000 ; ; D[5] ; RD[5] ; 19.000 ; ; ; 19.000 ;
; D[6] ; RD[6] ; 19.000 ; ; ; 19.000 ; ; D[6] ; RD[6] ; 19.000 ; ; ; 19.000 ;
; D[7] ; RD[7] ; 19.000 ; ; ; 19.000 ; ; D[7] ; RD[7] ; 19.000 ; ; ; 19.000 ;
; PHI1in ; PHI1out ; 32.000 ; ; ; 32.000 ; ; PHI1in ; PHI1out ; 19.000 ; ; ; 19.000 ;
; RD[0] ; D[0] ; 19.000 ; ; ; 19.000 ; ; RD[0] ; D[0] ; 19.000 ; ; ; 19.000 ;
; RD[1] ; D[1] ; 19.000 ; ; ; 19.000 ; ; RD[1] ; D[1] ; 19.000 ; ; ; 19.000 ;
; RD[2] ; D[2] ; 19.000 ; ; ; 19.000 ; ; RD[2] ; D[2] ; 19.000 ; ; ; 19.000 ;
@ -868,8 +872,8 @@ No paths to report.
; nDEVSEL ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; nDEVSEL ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nDEVSEL ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; nDEVSEL ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nDEVSEL ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; nDEVSEL ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
; nDEVSEL ; nCAS0 ; ; 19.000 ; 19.000 ; ; ; nDEVSEL ; nCAS0 ; ; 41.000 ; 41.000 ; ;
; nDEVSEL ; nCAS1 ; ; 19.000 ; 19.000 ; ; ; nDEVSEL ; nCAS1 ; ; 41.000 ; 41.000 ; ;
; nDEVSEL ; nRWE ; 19.000 ; ; ; 19.000 ; ; nDEVSEL ; nRWE ; 19.000 ; ; ; 19.000 ;
; nIOSEL ; D[0] ; ; 26.000 ; 26.000 ; ; ; nIOSEL ; D[0] ; ; 26.000 ; 26.000 ; ;
; nIOSEL ; D[1] ; ; 26.000 ; 26.000 ; ; ; nIOSEL ; D[1] ; ; 26.000 ; 26.000 ; ;
@ -1038,7 +1042,7 @@ No paths to report.
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+ +------------+----------+----------+----------+----------+----------+
; C7M ; C7M ; 706 ; 0 ; 0 ; 0 ; ; C7M ; C7M ; 706 ; 0 ; 0 ; 0 ;
; C7M ; C7M_2 ; 0 ; 0 ; 17 ; 0 ; ; C7M ; C7M_2 ; 0 ; 0 ; 14 ; 0 ;
+------------+----------+----------+----------+----------+----------+ +------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -1049,7 +1053,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+ +------------+----------+----------+----------+----------+----------+
; C7M ; C7M ; 706 ; 0 ; 0 ; 0 ; ; C7M ; C7M ; 706 ; 0 ; 0 ; 0 ;
; C7M ; C7M_2 ; 0 ; 0 ; 17 ; 0 ; ; C7M ; C7M_2 ; 0 ; 0 ; 14 ; 0 ;
+------------+----------+----------+----------+----------+----------+ +------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -1074,9 +1078,9 @@ No dedicated SERDES Receiver circuitry present in device or used in design
; Illegal Clocks ; 0 ; 0 ; ; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 34 ; 34 ; ; Unconstrained Input Ports ; 34 ; 34 ;
; Unconstrained Input Port Paths ; 421 ; 421 ; ; Unconstrained Input Port Paths ; 428 ; 428 ;
; Unconstrained Output Ports ; 35 ; 35 ; ; Unconstrained Output Ports ; 35 ; 35 ;
; Unconstrained Output Port Paths ; 254 ; 254 ; ; Unconstrained Output Port Paths ; 264 ; 264 ;
+---------------------------------+-------+------+ +---------------------------------+-------+------+
@ -1084,9 +1088,9 @@ No dedicated SERDES Receiver circuitry present in device or used in design
; TimeQuest Timing Analyzer Messages ; ; TimeQuest Timing Analyzer Messages ;
+------------------------------------+ +------------------------------------+
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun Sep 01 20:44:17 2019 Info: Processing started: Mon Sep 02 01:41:37 2019
Info: Command: quartus_sta GR8RAM -c GR8RAM Info: Command: quartus_sta GR8RAM -c GR8RAM
Info: qsta_default_script.tcl version: #1 Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled Warning (20028): Parallel compilation is not licensed and has been disabled
@ -1103,7 +1107,7 @@ Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -47.000 Info (332146): Worst-case setup slack is -47.000
Info (332119): Slack End Point TNS Clock Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= ===================== Info (332119): ========= ============= =====================
Info (332119): -47.000 -1802.000 C7M Info (332119): -47.000 -1763.000 C7M
Info (332119): -27.500 -33.000 C7M_2 Info (332119): -27.500 -33.000 C7M_2
Info (332146): Worst-case hold slack is -1.500 Info (332146): Worst-case hold slack is -1.500
Info (332119): Slack End Point TNS Clock Info (332119): Slack End Point TNS Clock
@ -1120,10 +1124,10 @@ Info (332146): Worst-case minimum pulse width slack is -5.500
Info (332001): The selected device family is not supported by the report_metastability command. Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 4530 megabytes Info: Peak virtual memory: 263 megabytes
Info: Processing ended: Sun Sep 01 20:44:17 2019 Info: Processing ended: Mon Sep 02 01:41:42 2019
Info: Elapsed time: 00:00:00 Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:00 Info: Total CPU time (on all processors): 00:00:05

2
cpld/output_files/GR8RAM.sta.summary
View File

@ -4,7 +4,7 @@ TimeQuest Timing Analyzer Summary
Type : Setup 'C7M' Type : Setup 'C7M'
Slack : -47.000 Slack : -47.000
TNS : -1802.000 TNS : -1763.000
Type : Setup 'C7M_2' Type : Setup 'C7M_2'
Slack : -27.500 Slack : -27.500