mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-12-12 08:30:08 +00:00
Clarified assignments
This commit is contained in:
Zane Kaminski
parent
7ccb2b670e
commit
b0a001aa58
@ -147,48 +147,7 @@ set_location_assignment PIN_2 -to PHI1in
|
||||
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES OFF
|
||||
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES OFF
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to ASel
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Add0
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Add1
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Add2
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Add3
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to AddrHWR_MC
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to AddrLWR_MC
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to AddrMWR_MC
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to BankWR_MC
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to C7M
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to C7M_2
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to CASf
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to CASr
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to CSDBEN
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to DOE
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal0
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal1
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal2
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal3
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal4
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal5
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal6
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal7
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal8
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal9
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal10
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal11
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal12
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal13
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal14
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal15
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal16
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal17
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to IOROMEN
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to MODE
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI0seen
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b0_MC
|
||||
set_global_assignment -name AUTO_TURBO_BIT OFF
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b1_MC
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b2_MC
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b3_MC
|
||||
@ -198,33 +157,7 @@ set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b6_MC
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b7_MC
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b8_MC
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b9_MC
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1in
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI0seen
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1reg
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Q3
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RAMSEL_MC
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RAMSELreg
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RASf
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RASr
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RDOE
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to REGEN
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to SetWR
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to always0
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to always2
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to comb
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nCAS0
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nCAS1
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nDEVSEL
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nINH
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nIOSEL
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nIOSTRB
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nRAS
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nRCS
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nRES
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nROE
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nRWE
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nWE
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A
|
||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b0_MC
|
||||
BIN
cpld/GR8RAM.qws
BIN
cpld/GR8RAM.qws
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
cpld/db/GR8RAM.(13).cnf.cdb
Normal file → Executable file
BIN
cpld/db/GR8RAM.(13).cnf.cdb
Normal file → Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.(13).cnf.hdb
Normal file → Executable file
BIN
cpld/db/GR8RAM.(13).cnf.hdb
Normal file → Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.(14).cnf.cdb
Normal file → Executable file
BIN
cpld/db/GR8RAM.(14).cnf.cdb
Normal file → Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.(14).cnf.hdb
Normal file → Executable file
BIN
cpld/db/GR8RAM.(14).cnf.hdb
Normal file → Executable file
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
cpld/db/GR8RAM.acvq.rdb
Normal file → Executable file
BIN
cpld/db/GR8RAM.acvq.rdb
Normal file → Executable file
Binary file not shown.
@ -1,5 +1,5 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567534158591 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567534158591 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:09:18 2019 " "Processing started: Tue Sep 03 14:09:18 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567534158591 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567534158591 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567534158592 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567534158715 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4521 " "Peak virtual memory: 4521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567534158856 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:09:18 2019 " "Processing ended: Tue Sep 03 14:09:18 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567534158856 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567534158856 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567534158856 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567534158856 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567734309571 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567734309571 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 21:45:09 2019 " "Processing started: Thu Sep 05 21:45:09 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567734309571 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567734309571 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567734309571 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567734311414 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567734311820 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 21:45:11 2019 " "Processing ended: Thu Sep 05 21:45:11 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567734311820 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567734311820 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567734311820 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567734311820 ""}
|
||||
|
||||
Binary file not shown.
BIN
cpld/db/GR8RAM.cmp 26.rdb
Executable file
BIN
cpld/db/GR8RAM.cmp 26.rdb
Executable file
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,3 +1,3 @@
|
||||
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Version_Index = 302049280
|
||||
Creation_Time = Mon Sep 02 21:03:24 2019
|
||||
Creation_Time = Fri Sep 06 16:48:57 2019
|
||||
|
||||
Binary file not shown.
@ -1,3 +1,3 @@
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567534157574 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567534157576 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567534157800 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:09:17 2019 " "Processing ended: Tue Sep 03 14:09:17 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567534157800 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567534157800 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567534157800 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567534157800 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567734307336 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567734307352 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567734307977 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 21:45:07 2019 " "Processing ended: Thu Sep 05 21:45:07 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567734307977 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567734307977 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567734307977 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567734307977 ""}
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,40 +1,40 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567534155639 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567534155640 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:09:15 2019 " "Processing started: Tue Sep 03 14:09:15 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567534155640 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567534155640 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567534155640 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567534155858 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(38) " "Verilog HDL warning at GR8RAM.v(38): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567534155883 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(46) " "Verilog HDL warning at GR8RAM.v(46): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 46 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567534155883 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(194) " "Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 194 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567534155883 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567534155884 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567534155884 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567534155924 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567534155925 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(126) " "Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567534155926 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567534155926 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(163) " "Verilog HDL assignment warning at GR8RAM.v(163): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567534155927 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(168) " "Verilog HDL assignment warning at GR8RAM.v(168): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567534155927 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (7)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567534155927 "|GR8RAM"}
|
||||
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156051 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567534156051 ""}
|
||||
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156051 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 168 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156051 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 163 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156051 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156051 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567534156051 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156077 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156077 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567534156077 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156095 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156095 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156095 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156095 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156095 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567534156095 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156108 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156118 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156119 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156131 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156142 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156143 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156157 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add5 " "Instantiated megafunction \"lpm_add_sub:Add5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 7 " "Parameter \"LPM_WIDTH\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156157 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156157 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156157 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156157 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567534156157 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 250 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156158 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156160 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 191 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156161 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 192 10 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156164 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|altshift:result_ext_latency_ffs lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567534156166 ""}
|
||||
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567534156222 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567534156222 ""}
|
||||
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567534156316 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567534156316 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567534156316 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567534156494 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567534156494 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567534156495 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567534156495 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567534156495 ""} { "Info" "ICUT_CUT_TM_MCELLS" "103 " "Implemented 103 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567534156495 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567534156495 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567534156495 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567534156532 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567534156569 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:09:16 2019 " "Processing ended: Tue Sep 03 14:09:16 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567534156569 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567534156569 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567534156569 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567534156569 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567734290759 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567734290759 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 21:44:50 2019 " "Processing started: Thu Sep 05 21:44:50 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567734290759 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567734290759 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567734290759 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567734295337 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(38) " "Verilog HDL warning at GR8RAM.v(38): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567734295555 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(46) " "Verilog HDL warning at GR8RAM.v(46): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 46 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567734295555 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(194) " "Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 194 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567734295555 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567734295555 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567734295555 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567734296071 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567734296071 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(126) " "Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567734296071 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567734296071 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(163) " "Verilog HDL assignment warning at GR8RAM.v(163): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567734296071 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(168) " "Verilog HDL assignment warning at GR8RAM.v(168): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567734296071 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (7)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567734296071 "|GR8RAM"}
|
||||
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734296337 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567734296337 ""}
|
||||
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734296352 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 168 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734296352 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 163 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734296352 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734296352 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567734296352 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734296946 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734296946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734296946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734296946 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567734296946 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734297243 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297243 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567734297243 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297509 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297790 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734297805 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298024 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298243 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298259 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734298430 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add5 " "Instantiated megafunction \"lpm_add_sub:Add5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 7 " "Parameter \"LPM_WIDTH\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298430 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567734298430 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 250 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298430 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298446 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 191 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298477 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 192 10 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298493 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|altshift:result_ext_latency_ffs lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567734298509 ""}
|
||||
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567734298821 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567734298821 ""}
|
||||
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567734299102 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567734299102 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567734299102 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567734299649 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567734299649 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567734299680 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567734299680 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567734299680 ""} { "Info" "ICUT_CUT_TM_MCELLS" "103 " "Implemented 103 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567734299680 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567734299680 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567734299680 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567734300149 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "304 " "Peak virtual memory: 304 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567734300258 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 21:45:00 2019 " "Processing ended: Thu Sep 05 21:45:00 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567734300258 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567734300258 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567734300258 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567734300258 ""}
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,22 +1,22 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567534159804 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567534159805 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:09:19 2019 " "Processing started: Tue Sep 03 14:09:19 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567534159805 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567534159805 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567534159805 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567534159859 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567534159956 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567534159966 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567534159968 ""}
|
||||
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567534159988 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567534160005 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567534160005 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160006 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160006 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160006 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567534160008 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567534160020 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160023 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160023 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -1888.500 C7M " " -47.500 -1888.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160023 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160023 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567534160023 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160027 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567534160027 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567534160031 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567534160034 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -450.000 C7M " " -4.500 -450.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567534160037 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567534160037 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567534160107 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567534160131 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567534160132 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567534160247 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:09:20 2019 " "Processing ended: Tue Sep 03 14:09:20 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567534160247 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567534160247 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567534160247 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567534160247 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567734315117 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567734315117 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 21:45:12 2019 " "Processing started: Thu Sep 05 21:45:12 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567734315117 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567734315117 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567734315117 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567734315211 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567734317164 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567734317180 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567734317195 ""}
|
||||
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567734317242 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567734317320 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567734317320 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317320 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317320 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317320 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567734317336 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567734317430 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317445 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317445 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -1992.500 C7M " " -47.500 -1992.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317445 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317445 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567734317445 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317461 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317461 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317461 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317461 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567734317461 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567734317477 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567734317492 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -450.000 C7M " " -4.500 -450.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567734317508 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567734317508 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567734317633 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567734317664 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567734317664 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "259 " "Peak virtual memory: 259 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567734317789 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 21:45:17 2019 " "Processing ended: Thu Sep 05 21:45:17 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567734317789 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567734317789 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567734317789 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567734317789 ""}
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,5 +1,5 @@
|
||||
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=7 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
|
||||
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END
|
||||
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
|
||||
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END
|
||||
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
|
||||
@ -1,78 +1,78 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567533898320 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567533898321 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:04:58 2019 " "Processing started: Tue Sep 03 14:04:58 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567533898321 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567533898321 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567533898321 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567533898533 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(38) " "Verilog HDL warning at GR8RAM.v(38): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567533898558 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(46) " "Verilog HDL warning at GR8RAM.v(46): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 46 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567533898558 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(194) " "Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 194 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567533898558 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567533898559 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567533898559 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567533898605 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567533898607 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(126) " "Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567533898607 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567533898607 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(163) " "Verilog HDL assignment warning at GR8RAM.v(163): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567533898607 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(168) " "Verilog HDL assignment warning at GR8RAM.v(168): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567533898607 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (7)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567533898607 "|GR8RAM"}
|
||||
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898686 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567533898686 ""}
|
||||
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898686 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 168 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898686 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 163 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898686 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898686 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567533898686 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898719 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898719 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898719 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898719 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567533898719 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898736 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898736 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567533898736 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898750 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898760 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898761 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898774 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898783 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898784 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533898798 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add5 " "Instantiated megafunction \"lpm_add_sub:Add5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 7 " "Parameter \"LPM_WIDTH\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898798 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898798 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898798 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898798 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567533898798 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 250 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898799 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898801 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 191 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898802 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 192 10 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898804 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|altshift:result_ext_latency_ffs lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567533898806 ""}
|
||||
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567533898861 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567533898861 ""}
|
||||
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567533898953 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567533898953 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567533898953 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567533899135 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567533899135 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567533899135 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567533899135 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567533899135 ""} { "Info" "ICUT_CUT_TM_MCELLS" "103 " "Implemented 103 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567533899135 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567533899135 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567533899135 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567533899176 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567533899220 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:04:59 2019 " "Processing ended: Tue Sep 03 14:04:59 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567533899220 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567533899220 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567533899220 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567533899220 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567533900167 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567533900167 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:04:59 2019 " "Processing started: Tue Sep 03 14:04:59 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567533900167 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1567533900167 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1567533900167 ""}
|
||||
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1567533900219 ""}
|
||||
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1567533900219 ""}
|
||||
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1567533900220 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567533900261 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567533900263 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567533900441 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:05:00 2019 " "Processing ended: Tue Sep 03 14:05:00 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567533900441 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567533900441 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567533900441 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567533900441 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1567533901287 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567533901287 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:05:01 2019 " "Processing started: Tue Sep 03 14:05:01 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567533901287 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567533901287 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567533901287 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567533901404 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4521 " "Peak virtual memory: 4521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567533901536 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:05:01 2019 " "Processing ended: Tue Sep 03 14:05:01 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567533901536 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567533901536 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567533901536 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567533901536 ""}
|
||||
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1567533902188 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1567533902511 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902512 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 03 14:05:02 2019 " "Processing started: Tue Sep 03 14:05:02 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567533902512 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567533902512 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567533902512 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567533902568 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567533902719 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567533902726 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567533902728 ""}
|
||||
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567533902748 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567533902762 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567533902762 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902763 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902763 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902763 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567533902765 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567533902776 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -1888.500 C7M " " -47.500 -1888.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902778 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567533902778 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902782 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902782 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902782 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902782 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567533902782 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567533902786 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567533902789 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902792 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902792 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902792 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -450.000 C7M " " -4.500 -450.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567533902792 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567533902792 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567533902856 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567533902887 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567533902888 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4541 " "Peak virtual memory: 4541 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567533902965 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 03 14:05:02 2019 " "Processing ended: Tue Sep 03 14:05:02 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567533902965 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567533902965 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567533902965 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567533902965 ""}
|
||||
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus II Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567533903599 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567725517560 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567725517560 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 19:18:37 2019 " "Processing started: Thu Sep 05 19:18:37 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567725517560 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567725517560 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567725517560 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567725522623 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(38) " "Verilog HDL warning at GR8RAM.v(38): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567725522951 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(46) " "Verilog HDL warning at GR8RAM.v(46): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 46 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567725522951 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(194) " "Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 194 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567725522951 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567725522967 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567725522967 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567725523233 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567725523248 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(126) " "Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567725523264 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567725523264 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(163) " "Verilog HDL assignment warning at GR8RAM.v(163): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567725523264 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(168) " "Verilog HDL assignment warning at GR8RAM.v(168): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567725523264 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (7)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567725523264 "|GR8RAM"}
|
||||
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725523811 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567725523811 ""}
|
||||
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725523811 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 168 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725523811 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 163 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725523811 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725523811 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567725523811 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725524280 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524280 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524280 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524280 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567725524280 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725524561 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524561 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524561 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524561 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524561 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567725524561 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524920 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725525170 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725525233 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725525561 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725525764 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725525811 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725526061 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add5 " "Instantiated megafunction \"lpm_add_sub:Add5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 7 " "Parameter \"LPM_WIDTH\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526061 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526061 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526061 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526061 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567725526061 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 250 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526108 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526139 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 191 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526170 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 192 10 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526217 ""}
|
||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|altshift:result_ext_latency_ffs lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526264 ""}
|
||||
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567725526655 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567725526655 ""}
|
||||
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567725526874 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567725526874 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567725526874 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567725527295 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567725527311 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567725527311 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567725527311 ""} { "Info" "ICUT_CUT_TM_MCELLS" "103 " "Implemented 103 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567725527311 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567725527311 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567725527311 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567725527827 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "312 " "Peak virtual memory: 312 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567725527983 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 19:18:47 2019 " "Processing ended: Thu Sep 05 19:18:47 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567725527983 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567725527983 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567725527983 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567725527983 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567725531546 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567725531561 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 19:18:49 2019 " "Processing started: Thu Sep 05 19:18:49 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567725531561 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1567725531561 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1567725531561 ""}
|
||||
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1567725531718 ""}
|
||||
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1567725531718 ""}
|
||||
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1567725531718 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567725533624 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567725533640 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567725534390 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 19:18:54 2019 " "Processing ended: Thu Sep 05 19:18:54 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567725534390 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567725534390 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567725534390 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567725534390 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1567725536421 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567725536437 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 19:18:56 2019 " "Processing started: Thu Sep 05 19:18:56 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567725536437 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567725536437 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567725536437 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567725538953 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567725539359 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 19:18:59 2019 " "Processing ended: Thu Sep 05 19:18:59 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567725539359 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567725539359 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567725539359 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567725539359 ""}
|
||||
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1567725540062 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1567725542547 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567725542547 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 19:19:00 2019 " "Processing started: Thu Sep 05 19:19:00 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567725542547 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567725542547 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567725542547 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567725542640 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567725544453 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567725544469 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567725544484 ""}
|
||||
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567725544547 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567725544594 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567725544594 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544594 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544594 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544594 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567725544609 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567725544719 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -21.500 " "Worst-case setup slack is -21.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544766 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544766 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -21.500 -926.500 C7M " " -21.500 -926.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544766 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.500 -20.000 C7M_2 " " -14.500 -20.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544766 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567725544766 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544781 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544781 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544781 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544781 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567725544781 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567725544797 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567725544797 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544812 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544812 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544812 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -450.000 C7M " " -4.500 -450.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544812 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567725544812 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567725544953 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567725545000 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567725545000 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "267 " "Peak virtual memory: 267 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567725545125 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 19:19:05 2019 " "Processing ended: Thu Sep 05 19:19:05 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567725545125 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567725545125 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567725545125 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567725545125 ""}
|
||||
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus II Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567725546000 ""}
|
||||
|
||||
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
Assembler report for GR8RAM
|
||||
Tue Sep 03 14:09:18 2019
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Thu Sep 05 21:45:11 2019
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -10,7 +10,7 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof
|
||||
5. Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof
|
||||
6. Assembler Messages
|
||||
|
||||
|
||||
@ -37,7 +37,7 @@ applicable agreement for further details.
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Tue Sep 03 14:09:18 2019 ;
|
||||
; Assembler Status ; Successful - Thu Sep 05 21:45:11 2019 ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX7000S ;
|
||||
@ -73,39 +73,39 @@ applicable agreement for further details.
|
||||
+-----------------------------------------------------------------------------+----------+---------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------+
|
||||
+----------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+--------------------------------------------------------------------+
|
||||
+----------------------------------------------+
|
||||
; File Name ;
|
||||
+--------------------------------------------------------------------+
|
||||
; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||
+--------------------------------------------------------------------+
|
||||
+----------------------------------------------+
|
||||
; Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||
+----------------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------+
|
||||
; Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||
+----------------+-----------------------------------------------------------------------------+
|
||||
+------------------------------------------------------------------------+
|
||||
; Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||
+----------------+-------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+-----------------------------------------------------------------------------+
|
||||
+----------------+-------------------------------------------------------+
|
||||
; Device ; EPM7128SLC84-15 ;
|
||||
; JTAG usercode ; 0x00000000 ;
|
||||
; Checksum ; 0x0017D254 ;
|
||||
+----------------+-----------------------------------------------------------------------------+
|
||||
; Checksum ; 0x0017D4EA ;
|
||||
+----------------+-------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
; Assembler Messages ;
|
||||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 64-Bit Assembler
|
||||
Info: Running Quartus II 32-bit Assembler
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Tue Sep 03 14:09:18 2019
|
||||
Info: Processing started: Thu Sep 05 21:45:09 2019
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 4521 megabytes
|
||||
Info: Processing ended: Tue Sep 03 14:09:18 2019
|
||||
Info: Elapsed time: 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 277 megabytes
|
||||
Info: Processing ended: Thu Sep 05 21:45:11 2019
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
||||
|
||||
@ -1 +1 @@
|
||||
Tue Sep 03 14:09:20 2019
|
||||
Thu Sep 05 21:45:18 2019
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Fitter report for GR8RAM
|
||||
Tue Sep 03 14:09:17 2019
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Thu Sep 05 21:45:07 2019
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -9,27 +9,26 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||
1. Legal Notice
|
||||
2. Fitter Summary
|
||||
3. Fitter Settings
|
||||
4. Parallel Compilation
|
||||
5. Pin-Out File
|
||||
6. Fitter Resource Usage Summary
|
||||
7. Input Pins
|
||||
8. Output Pins
|
||||
9. Bidir Pins
|
||||
10. All Package Pins
|
||||
11. I/O Standard
|
||||
12. Dedicated Inputs I/O
|
||||
13. Output Pin Default Load For Reported TCO
|
||||
14. Fitter Resource Utilization by Entity
|
||||
15. Control Signals
|
||||
16. Global & Other Fast Signals
|
||||
17. Non-Global High Fan-Out Signals
|
||||
18. Other Routing Usage Summary
|
||||
19. LAB External Interconnect
|
||||
20. LAB Macrocells
|
||||
21. Shareable Expander
|
||||
22. Logic Cell Interconnection
|
||||
23. Fitter Device Options
|
||||
24. Fitter Messages
|
||||
4. Pin-Out File
|
||||
5. Fitter Resource Usage Summary
|
||||
6. Input Pins
|
||||
7. Output Pins
|
||||
8. Bidir Pins
|
||||
9. All Package Pins
|
||||
10. I/O Standard
|
||||
11. Dedicated Inputs I/O
|
||||
12. Output Pin Default Load For Reported TCO
|
||||
13. Fitter Resource Utilization by Entity
|
||||
14. Control Signals
|
||||
15. Global & Other Fast Signals
|
||||
16. Non-Global High Fan-Out Signals
|
||||
17. Other Routing Usage Summary
|
||||
18. LAB External Interconnect
|
||||
19. LAB Macrocells
|
||||
20. Shareable Expander
|
||||
21. Logic Cell Interconnection
|
||||
22. Fitter Device Options
|
||||
23. Fitter Messages
|
||||
|
||||
|
||||
|
||||
@ -55,8 +54,8 @@ applicable agreement for further details.
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+---------------------------+-------------------------------------------------+
|
||||
; Fitter Status ; Successful - Tue Sep 03 14:09:17 2019 ;
|
||||
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Fitter Status ; Successful - Thu Sep 05 21:45:07 2019 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX7000S ;
|
||||
@ -87,21 +86,10 @@ applicable agreement for further details.
|
||||
+----------------------------------------------------------------------------+-----------------------+---------------+
|
||||
|
||||
|
||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||
+-------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+--------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+--------+
|
||||
; Number detected on machine ; 8 ;
|
||||
; Maximum allowed ; 1 ;
|
||||
+----------------------------+--------+
|
||||
|
||||
|
||||
+--------------+
|
||||
; Pin-Out File ;
|
||||
+--------------+
|
||||
The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||
The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||
|
||||
|
||||
+---------------------------------------------------+
|
||||
@ -119,7 +107,7 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/outp
|
||||
; Global signals ; 2 ;
|
||||
; Shareable expanders ; 1 / 128 ( < 1 % ) ;
|
||||
; Parallel expanders ; 0 / 120 ( 0 % ) ;
|
||||
; Cells using turbo bit ; 59 / 128 ( 46 % ) ;
|
||||
; Cells using turbo bit ; 43 / 128 ( 34 % ) ;
|
||||
; Maximum fan-out ; 52 ;
|
||||
; Highest non-global fan-out ; 51 ;
|
||||
; Total fan-out ; 830 ;
|
||||
@ -724,10 +712,10 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
+-----------------+
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM"
|
||||
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 4708 megabytes
|
||||
Info: Processing ended: Tue Sep 03 14:09:17 2019
|
||||
Info: Elapsed time: 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
Info: Quartus II 32-bit Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 287 megabytes
|
||||
Info: Processing ended: Thu Sep 05 21:45:07 2019
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info: Total CPU time (on all processors): 00:00:06
|
||||
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Fitter Status : Successful - Tue Sep 03 14:09:17 2019
|
||||
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Fitter Status : Successful - Thu Sep 05 21:45:07 2019
|
||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : GR8RAM
|
||||
Top-level Entity Name : GR8RAM
|
||||
Family : MAX7000S
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Flow report for GR8RAM
|
||||
Tue Sep 03 14:09:20 2019
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Thu Sep 05 21:45:17 2019
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -40,8 +40,8 @@ applicable agreement for further details.
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+---------------------------+-------------------------------------------------+
|
||||
; Flow Status ; Successful - Tue Sep 03 14:09:18 2019 ;
|
||||
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Flow Status ; Successful - Thu Sep 05 21:45:11 2019 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX7000S ;
|
||||
@ -57,21 +57,21 @@ applicable agreement for further details.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 09/03/2019 14:09:15 ;
|
||||
; Start date & time ; 09/05/2019 21:44:55 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
+-------------------+---------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------+
|
||||
+---------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Non-Default Global Settings ;
|
||||
+--------------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||
+--------------------------------------------+-----------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+--------------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||
+--------------------------------------------+-----------------------------+---------------+-------------+------------+
|
||||
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
|
||||
; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ;
|
||||
; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 207120313862967.156753415530004 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 52238299365.156773429502244 ; -- ; -- ; -- ;
|
||||
; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ;
|
||||
; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ;
|
||||
; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ;
|
||||
@ -89,7 +89,7 @@ applicable agreement for further details.
|
||||
; STATE_MACHINE_PROCESSING ; User-Encoded ; Auto ; -- ; -- ;
|
||||
; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ;
|
||||
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
|
||||
+--------------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||
+--------------------------------------------+-----------------------------+---------------+-------------+------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------+
|
||||
@ -97,24 +97,24 @@ applicable agreement for further details.
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4587 MB ; 00:00:01 ;
|
||||
; Fitter ; 00:00:00 ; 1.0 ; 4708 MB ; 00:00:01 ;
|
||||
; Assembler ; 00:00:00 ; 1.0 ; 4521 MB ; 00:00:00 ;
|
||||
; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4530 MB ; 00:00:00 ;
|
||||
; Total ; 00:00:02 ; -- ; -- ; 00:00:02 ;
|
||||
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 304 MB ; 00:00:09 ;
|
||||
; Fitter ; 00:00:06 ; 1.0 ; 287 MB ; 00:00:06 ;
|
||||
; Assembler ; 00:00:02 ; 1.0 ; 275 MB ; 00:00:02 ;
|
||||
; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 259 MB ; 00:00:05 ;
|
||||
; Total ; 00:00:23 ; -- ; -- ; 00:00:22 ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------+
|
||||
+-----------------------------------------------------------------------------------------+
|
||||
; Flow OS Summary ;
|
||||
+---------------------------+------------------+-----------+------------+----------------+
|
||||
+---------------------------+------------------+------------+------------+----------------+
|
||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||
+---------------------------+------------------+-----------+------------+----------------+
|
||||
; Analysis & Synthesis ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; Fitter ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; Assembler ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; TimeQuest Timing Analyzer ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
+---------------------------+------------------+-----------+------------+----------------+
|
||||
+---------------------------+------------------+------------+------------+----------------+
|
||||
; Analysis & Synthesis ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
|
||||
; Fitter ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
|
||||
; Assembler ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
|
||||
; TimeQuest Timing Analyzer ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
|
||||
+---------------------------+------------------+------------+------------+----------------+
|
||||
|
||||
|
||||
------------
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="6680f745e8da7e3a7216"/>
|
||||
<hash md5_digest_80b="377ae0e3d641f83b46e8"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Analysis & Synthesis report for GR8RAM
|
||||
Tue Sep 03 14:09:16 2019
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Thu Sep 05 21:45:00 2019
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -9,17 +9,16 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||
1. Legal Notice
|
||||
2. Analysis & Synthesis Summary
|
||||
3. Analysis & Synthesis Settings
|
||||
4. Parallel Compilation
|
||||
5. Analysis & Synthesis Source Files Read
|
||||
6. Analysis & Synthesis Resource Usage Summary
|
||||
7. Analysis & Synthesis Resource Utilization by Entity
|
||||
8. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0
|
||||
9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0
|
||||
10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4
|
||||
11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3
|
||||
12. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5
|
||||
13. Analysis & Synthesis Messages
|
||||
14. Analysis & Synthesis Suppressed Messages
|
||||
4. Analysis & Synthesis Source Files Read
|
||||
5. Analysis & Synthesis Resource Usage Summary
|
||||
6. Analysis & Synthesis Resource Utilization by Entity
|
||||
7. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0
|
||||
8. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0
|
||||
9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4
|
||||
10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3
|
||||
11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5
|
||||
12. Analysis & Synthesis Messages
|
||||
13. Analysis & Synthesis Suppressed Messages
|
||||
|
||||
|
||||
|
||||
@ -45,8 +44,8 @@ applicable agreement for further details.
|
||||
+-------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+-------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Tue Sep 03 14:09:16 2019 ;
|
||||
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Analysis & Synthesis Status ; Successful - Thu Sep 05 21:45:00 2019 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX7000S ;
|
||||
@ -119,23 +118,12 @@ applicable agreement for further details.
|
||||
+----------------------------------------------------------------------------+-----------------+---------------+
|
||||
|
||||
|
||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||
+-------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+--------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+--------+
|
||||
; Number detected on machine ; 8 ;
|
||||
; Maximum allowed ; 1 ;
|
||||
+----------------------------+--------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
|
||||
; GR8RAM.v ; yes ; User Verilog HDL File ; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ; ;
|
||||
; GR8RAM.v ; yes ; User Verilog HDL File ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ; ;
|
||||
; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ;
|
||||
; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ;
|
||||
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
|
||||
@ -329,9 +317,9 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||
; Analysis & Synthesis Messages ;
|
||||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 64-Bit Analysis & Synthesis
|
||||
Info: Running Quartus II 32-bit Analysis & Synthesis
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Tue Sep 03 14:09:15 2019
|
||||
Info: Processing started: Thu Sep 05 21:44:50 2019
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
||||
@ -398,17 +386,17 @@ Info (21057): Implemented 165 device resources after synthesis - the final resou
|
||||
Info (21060): Implemented 16 bidirectional pins
|
||||
Info (21063): Implemented 103 macrocells
|
||||
Info (21073): Implemented 1 shareable expanders
|
||||
Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
||||
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings
|
||||
Info: Peak virtual memory: 4587 megabytes
|
||||
Info: Processing ended: Tue Sep 03 14:09:16 2019
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings
|
||||
Info: Peak virtual memory: 304 megabytes
|
||||
Info: Processing ended: Thu Sep 05 21:45:00 2019
|
||||
Info: Elapsed time: 00:00:10
|
||||
Info: Total CPU time (on all processors): 00:00:09
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Analysis & Synthesis Suppressed Messages ;
|
||||
+------------------------------------------+
|
||||
The suppressed messages can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
||||
The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
||||
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Analysis & Synthesis Status : Successful - Tue Sep 03 14:09:16 2019
|
||||
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Analysis & Synthesis Status : Successful - Thu Sep 05 21:45:00 2019
|
||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : GR8RAM
|
||||
Top-level Entity Name : GR8RAM
|
||||
Family : MAX7000S
|
||||
|
||||
@ -56,7 +56,7 @@
|
||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
CHIP "GR8RAM" ASSIGNED TO AN: EPM7128SLC84-15
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
|
||||
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
TimeQuest Timing Analyzer report for GR8RAM
|
||||
Tue Sep 03 14:09:20 2019
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Thu Sep 05 21:45:17 2019
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -8,36 +8,35 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. TimeQuest Timing Analyzer Summary
|
||||
3. Parallel Compilation
|
||||
4. Clocks
|
||||
5. Fmax Summary
|
||||
6. Setup Summary
|
||||
7. Hold Summary
|
||||
8. Recovery Summary
|
||||
9. Removal Summary
|
||||
10. Minimum Pulse Width Summary
|
||||
11. Setup: 'C7M'
|
||||
12. Setup: 'C7M_2'
|
||||
13. Hold: 'C7M_2'
|
||||
14. Hold: 'C7M'
|
||||
15. Minimum Pulse Width: 'C7M_2'
|
||||
16. Minimum Pulse Width: 'C7M'
|
||||
17. Setup Times
|
||||
18. Hold Times
|
||||
19. Clock to Output Times
|
||||
20. Minimum Clock to Output Times
|
||||
21. Propagation Delay
|
||||
22. Minimum Propagation Delay
|
||||
23. Output Enable Times
|
||||
24. Minimum Output Enable Times
|
||||
25. Output Disable Times
|
||||
26. Minimum Output Disable Times
|
||||
27. Setup Transfers
|
||||
28. Hold Transfers
|
||||
29. Report TCCS
|
||||
30. Report RSKM
|
||||
31. Unconstrained Paths
|
||||
32. TimeQuest Timing Analyzer Messages
|
||||
3. Clocks
|
||||
4. Fmax Summary
|
||||
5. Setup Summary
|
||||
6. Hold Summary
|
||||
7. Recovery Summary
|
||||
8. Removal Summary
|
||||
9. Minimum Pulse Width Summary
|
||||
10. Setup: 'C7M'
|
||||
11. Setup: 'C7M_2'
|
||||
12. Hold: 'C7M_2'
|
||||
13. Hold: 'C7M'
|
||||
14. Minimum Pulse Width: 'C7M_2'
|
||||
15. Minimum Pulse Width: 'C7M'
|
||||
16. Setup Times
|
||||
17. Hold Times
|
||||
18. Clock to Output Times
|
||||
19. Minimum Clock to Output Times
|
||||
20. Propagation Delay
|
||||
21. Minimum Propagation Delay
|
||||
22. Output Enable Times
|
||||
23. Minimum Output Enable Times
|
||||
24. Output Disable Times
|
||||
25. Minimum Output Disable Times
|
||||
26. Setup Transfers
|
||||
27. Hold Transfers
|
||||
28. Report TCCS
|
||||
29. Report RSKM
|
||||
30. Unconstrained Paths
|
||||
31. TimeQuest Timing Analyzer Messages
|
||||
|
||||
|
||||
|
||||
@ -73,17 +72,6 @@ applicable agreement for further details.
|
||||
+--------------------+-------------------------------------------------------------------+
|
||||
|
||||
|
||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||
+-------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+--------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+--------+
|
||||
; Number detected on machine ; 8 ;
|
||||
; Maximum allowed ; 1 ;
|
||||
+----------------------------+--------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Clocks ;
|
||||
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
|
||||
@ -109,7 +97,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; C7M ; -47.500 ; -1888.500 ;
|
||||
; C7M ; -47.500 ; -1992.500 ;
|
||||
; C7M_2 ; -27.500 ; -33.000 ;
|
||||
+-------+---------+---------------+
|
||||
|
||||
@ -151,9 +139,11 @@ No paths to report.
|
||||
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||
; -47.500 ; REGEN ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
@ -173,6 +163,7 @@ No paths to report.
|
||||
; -47.500 ; REGEN ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[7] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Bank[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
; -47.500 ; REGEN ; Bank[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
||||
@ -185,9 +176,12 @@ No paths to report.
|
||||
; -47.000 ; REGEN ; RASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||
; -47.000 ; REGEN ; ASel ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||
; -47.000 ; REGEN ; CASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||
; -34.500 ; REGEN ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ;
|
||||
; -34.500 ; REGEN ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ;
|
||||
; -34.500 ; REGEN ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ;
|
||||
; -46.500 ; S[0] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ;
|
||||
; -46.500 ; S[2] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ;
|
||||
; -46.000 ; IncAddrL ; IncAddrM ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ;
|
||||
; -25.500 ; S[0] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
@ -197,6 +191,9 @@ No paths to report.
|
||||
; -25.500 ; S[2] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
@ -242,15 +239,6 @@ No paths to report.
|
||||
; -25.500 ; S[2] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[14] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[14] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[14] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[0] ; Addr[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[2] ; Addr[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
; -25.500 ; S[1] ; Addr[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
||||
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
@ -292,11 +280,11 @@ No paths to report.
|
||||
+--------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'C7M' ;
|
||||
+-------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; 5.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[2] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
@ -314,46 +302,12 @@ No paths to report.
|
||||
; 5.000 ; S[0] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; IncAddrL ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[1] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; IncAddrH ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; IncAddrM ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[15] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[14] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[13] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[12] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[11] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[10] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[9] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[8] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[16] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[17] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[9] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
@ -373,31 +327,65 @@ No paths to report.
|
||||
; 5.000 ; Addr[22] ; Addr[22] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[6] ; Addr[6] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[7] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; IncAddrL ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[6] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[5] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[4] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[3] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[2] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[1] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[0] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; IncAddrM ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.000 ; Addr[8] ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; S[0] ; IncAddrL ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; S[2] ; IncAddrL ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; S[1] ; IncAddrL ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; S[2] ; IncAddrH ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; S[0] ; IncAddrH ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; S[1] ; IncAddrH ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; S[2] ; IncAddrM ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; S[0] ; IncAddrM ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; S[1] ; IncAddrM ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; S[2] ; FullIOEN ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; S[1] ; FullIOEN ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; S[0] ; FullIOEN ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
; 5.500 ; REGEN ; FullIOEN ; C7M ; C7M ; -0.500 ; 0.000 ; 9.000 ;
|
||||
+-------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; 18.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; CSDBEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[1] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[0] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; S[2] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrL ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrL ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[0] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[14] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[13] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[12] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[11] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[10] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[9] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[8] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrM ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrH ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; IncAddrM ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
; 18.000 ; Addr[15] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------+
|
||||
@ -594,22 +582,22 @@ No paths to report.
|
||||
; nDEVSEL ; C7M ; -38.000 ; -38.000 ; Rise ; C7M ;
|
||||
; nIOSEL ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||
; nIOSTRB ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||
; A[*] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; A[0] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; A[1] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; A[2] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; A[3] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; D[*] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; D[0] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; D[1] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; D[2] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; D[3] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; D[4] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; D[5] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; D[6] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; D[7] ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; nDEVSEL ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; nWE ; C7M ; -3.000 ; -3.000 ; Fall ; C7M ;
|
||||
; A[*] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; A[0] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; A[1] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; A[2] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; A[3] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[*] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[0] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[1] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[2] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[3] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[4] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[5] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[6] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; D[7] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; nDEVSEL ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; nWE ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
||||
; A[*] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ;
|
||||
; A[0] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ;
|
||||
; A[1] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ;
|
||||
@ -637,10 +625,10 @@ No paths to report.
|
||||
; RA[8] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
|
||||
; RA[9] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
|
||||
; RA[10] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
|
||||
; nCAS0 ; C7M ; 43.000 ; 43.000 ; Rise ; C7M ;
|
||||
; nCAS1 ; C7M ; 43.000 ; 43.000 ; Rise ; C7M ;
|
||||
; nRAS ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
|
||||
; nRCS ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
|
||||
; nCAS0 ; C7M ; 56.000 ; 56.000 ; Rise ; C7M ;
|
||||
; nCAS1 ; C7M ; 56.000 ; 56.000 ; Rise ; C7M ;
|
||||
; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; D[*] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; D[0] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; D[1] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
@ -662,11 +650,11 @@ No paths to report.
|
||||
; RA[8] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; RA[9] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; RA[10] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; nCAS0 ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; nCAS1 ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; nCAS0 ; C7M_2 ; 41.000 ; 41.000 ; Fall ; C7M_2 ;
|
||||
; nCAS1 ; C7M_2 ; 41.000 ; 41.000 ; Fall ; C7M_2 ;
|
||||
; nRAS ; C7M_2 ; 41.000 ; 41.000 ; Fall ; C7M_2 ;
|
||||
; nCAS0 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
||||
; nCAS1 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
||||
; nCAS0 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
||||
; nCAS1 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
||||
; nRAS ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
|
||||
|
||||
@ -687,10 +675,10 @@ No paths to report.
|
||||
; RA[8] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
|
||||
; RA[9] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
|
||||
; RA[10] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
|
||||
; nCAS0 ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
|
||||
; nCAS1 ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
|
||||
; nRAS ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
|
||||
; nRCS ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ;
|
||||
; nCAS0 ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; nCAS1 ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||
; D[*] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; D[0] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; D[1] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
@ -712,11 +700,11 @@ No paths to report.
|
||||
; RA[8] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; RA[9] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; RA[10] ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; nCAS0 ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; nCAS1 ; C7M ; 21.000 ; 21.000 ; Fall ; C7M ;
|
||||
; nCAS0 ; C7M_2 ; 41.000 ; 41.000 ; Fall ; C7M_2 ;
|
||||
; nCAS1 ; C7M_2 ; 41.000 ; 41.000 ; Fall ; C7M_2 ;
|
||||
; nRAS ; C7M_2 ; 41.000 ; 41.000 ; Fall ; C7M_2 ;
|
||||
; nCAS0 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
||||
; nCAS1 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
||||
; nCAS0 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
||||
; nCAS1 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
||||
; nRAS ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
|
||||
|
||||
@ -733,8 +721,8 @@ No paths to report.
|
||||
; A[0] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[0] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[0] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[0] ; nCAS0 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[0] ; nCAS1 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[0] ; nCAS0 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[0] ; nCAS1 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[1] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[1] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[1] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
@ -743,8 +731,8 @@ No paths to report.
|
||||
; A[1] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[1] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[1] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[1] ; nCAS0 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[1] ; nCAS1 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[1] ; nCAS0 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[1] ; nCAS1 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[2] ; D[0] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[2] ; D[1] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[2] ; D[2] ; ; 19.000 ; 19.000 ; ;
|
||||
@ -753,8 +741,8 @@ No paths to report.
|
||||
; A[2] ; D[5] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[2] ; D[6] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[2] ; D[7] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[2] ; nCAS0 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[2] ; nCAS1 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[2] ; nCAS0 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[2] ; nCAS1 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[3] ; D[0] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[3] ; D[1] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[3] ; D[2] ; ; 19.000 ; 19.000 ; ;
|
||||
@ -763,8 +751,8 @@ No paths to report.
|
||||
; A[3] ; D[5] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[3] ; D[6] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[3] ; D[7] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[3] ; nCAS0 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[3] ; nCAS1 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[3] ; nCAS0 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[3] ; nCAS1 ; ; 54.000 ; 54.000 ; ;
|
||||
; D[0] ; RD[0] ; 19.000 ; ; ; 19.000 ;
|
||||
; D[1] ; RD[1] ; 19.000 ; ; ; 19.000 ;
|
||||
; D[2] ; RD[2] ; 19.000 ; ; ; 19.000 ;
|
||||
@ -781,25 +769,25 @@ No paths to report.
|
||||
; RD[5] ; D[5] ; 19.000 ; ; ; 19.000 ;
|
||||
; RD[6] ; D[6] ; 19.000 ; ; ; 19.000 ;
|
||||
; RD[7] ; D[7] ; 19.000 ; ; ; 19.000 ;
|
||||
; nDEVSEL ; D[0] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[1] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[2] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[3] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[4] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[5] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[6] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[7] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ;
|
||||
; nDEVSEL ; nCAS0 ; ; 41.000 ; 41.000 ; ;
|
||||
; nDEVSEL ; nCAS1 ; ; 41.000 ; 41.000 ; ;
|
||||
; nDEVSEL ; nRWE ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSEL ; D[0] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[1] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[2] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[3] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[4] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[5] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[6] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[7] ; ; 26.000 ; 26.000 ; ;
|
||||
; nDEVSEL ; D[0] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[1] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[2] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[3] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[4] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[5] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[6] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[7] ; 19.000 ; 39.000 ; 39.000 ; 19.000 ;
|
||||
; nDEVSEL ; nCAS0 ; ; 54.000 ; 54.000 ; ;
|
||||
; nDEVSEL ; nCAS1 ; ; 54.000 ; 54.000 ; ;
|
||||
; nDEVSEL ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nIOSEL ; D[0] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[1] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[2] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[3] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[4] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[5] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[6] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[7] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; RA[0] ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSEL ; RA[1] ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSEL ; RA[2] ; 19.000 ; ; ; 19.000 ;
|
||||
@ -808,16 +796,16 @@ No paths to report.
|
||||
; nIOSEL ; RA[5] ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSEL ; RA[6] ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSEL ; RA[7] ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSEL ; nRCS ; ; 19.000 ; 19.000 ; ;
|
||||
; nIOSEL ; nRWE ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSTRB ; D[0] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[1] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[2] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[3] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[4] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[5] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[6] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[7] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; nRCS ; ; 32.000 ; 32.000 ; ;
|
||||
; nIOSEL ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nIOSTRB ; D[0] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[1] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[2] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[3] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[4] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[5] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[6] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[7] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; RA[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nIOSTRB ; RA[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nIOSTRB ; RA[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
@ -826,26 +814,26 @@ No paths to report.
|
||||
; nIOSTRB ; RA[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nIOSTRB ; RA[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nIOSTRB ; RA[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nIOSTRB ; nRCS ; ; 19.000 ; 19.000 ; ;
|
||||
; nIOSTRB ; nRWE ; 19.000 ; ; ; 19.000 ;
|
||||
; nWE ; D[0] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[1] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[2] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[3] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[4] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[5] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[6] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[7] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; RD[0] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[1] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[2] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[3] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[4] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[5] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[6] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[7] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; nROE ; ; 19.000 ; 19.000 ; ;
|
||||
; nWE ; nRWE ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSTRB ; nRCS ; ; 32.000 ; 32.000 ; ;
|
||||
; nIOSTRB ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nWE ; D[0] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[1] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[2] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[3] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[4] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[5] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[6] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[7] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; RD[0] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[1] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[2] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[3] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[4] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[5] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[6] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[7] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; nROE ; ; 32.000 ; 32.000 ; ;
|
||||
; nWE ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
+------------+-------------+--------+--------+--------+--------+
|
||||
|
||||
|
||||
@ -862,8 +850,8 @@ No paths to report.
|
||||
; A[0] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[0] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[0] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[0] ; nCAS0 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[0] ; nCAS1 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[0] ; nCAS0 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[0] ; nCAS1 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[1] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[1] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[1] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
@ -872,8 +860,8 @@ No paths to report.
|
||||
; A[1] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[1] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[1] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; A[1] ; nCAS0 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[1] ; nCAS1 ; 41.000 ; ; ; 41.000 ;
|
||||
; A[1] ; nCAS0 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[1] ; nCAS1 ; 54.000 ; ; ; 54.000 ;
|
||||
; A[2] ; D[0] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[2] ; D[1] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[2] ; D[2] ; ; 19.000 ; 19.000 ; ;
|
||||
@ -882,8 +870,8 @@ No paths to report.
|
||||
; A[2] ; D[5] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[2] ; D[6] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[2] ; D[7] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[2] ; nCAS0 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[2] ; nCAS1 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[2] ; nCAS0 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[2] ; nCAS1 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[3] ; D[0] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[3] ; D[1] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[3] ; D[2] ; ; 19.000 ; 19.000 ; ;
|
||||
@ -892,8 +880,8 @@ No paths to report.
|
||||
; A[3] ; D[5] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[3] ; D[6] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[3] ; D[7] ; ; 19.000 ; 19.000 ; ;
|
||||
; A[3] ; nCAS0 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[3] ; nCAS1 ; ; 41.000 ; 41.000 ; ;
|
||||
; A[3] ; nCAS0 ; ; 54.000 ; 54.000 ; ;
|
||||
; A[3] ; nCAS1 ; ; 54.000 ; 54.000 ; ;
|
||||
; D[0] ; RD[0] ; 19.000 ; ; ; 19.000 ;
|
||||
; D[1] ; RD[1] ; 19.000 ; ; ; 19.000 ;
|
||||
; D[2] ; RD[2] ; 19.000 ; ; ; 19.000 ;
|
||||
@ -918,17 +906,17 @@ No paths to report.
|
||||
; nDEVSEL ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nDEVSEL ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nDEVSEL ; nCAS0 ; ; 41.000 ; 41.000 ; ;
|
||||
; nDEVSEL ; nCAS1 ; ; 41.000 ; 41.000 ; ;
|
||||
; nDEVSEL ; nRWE ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSEL ; D[0] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[1] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[2] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[3] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[4] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[5] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[6] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; D[7] ; ; 26.000 ; 26.000 ; ;
|
||||
; nDEVSEL ; nCAS0 ; ; 54.000 ; 54.000 ; ;
|
||||
; nDEVSEL ; nCAS1 ; ; 54.000 ; 54.000 ; ;
|
||||
; nDEVSEL ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nIOSEL ; D[0] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[1] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[2] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[3] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[4] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[5] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[6] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; D[7] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSEL ; RA[0] ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSEL ; RA[1] ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSEL ; RA[2] ; 19.000 ; ; ; 19.000 ;
|
||||
@ -937,16 +925,16 @@ No paths to report.
|
||||
; nIOSEL ; RA[5] ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSEL ; RA[6] ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSEL ; RA[7] ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSEL ; nRCS ; ; 19.000 ; 19.000 ; ;
|
||||
; nIOSEL ; nRWE ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSTRB ; D[0] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[1] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[2] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[3] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[4] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[5] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[6] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSTRB ; D[7] ; ; 26.000 ; 26.000 ; ;
|
||||
; nIOSEL ; nRCS ; ; 32.000 ; 32.000 ; ;
|
||||
; nIOSEL ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nIOSTRB ; D[0] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[1] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[2] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[3] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[4] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[5] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[6] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; D[7] ; ; 39.000 ; 39.000 ; ;
|
||||
; nIOSTRB ; RA[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nIOSTRB ; RA[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nIOSTRB ; RA[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
@ -955,26 +943,26 @@ No paths to report.
|
||||
; nIOSTRB ; RA[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nIOSTRB ; RA[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nIOSTRB ; RA[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ;
|
||||
; nIOSTRB ; nRCS ; ; 19.000 ; 19.000 ; ;
|
||||
; nIOSTRB ; nRWE ; 19.000 ; ; ; 19.000 ;
|
||||
; nWE ; D[0] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[1] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[2] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[3] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[4] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[5] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[6] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; D[7] ; 26.000 ; ; ; 26.000 ;
|
||||
; nWE ; RD[0] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[1] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[2] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[3] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[4] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[5] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[6] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; RD[7] ; ; 26.000 ; 26.000 ; ;
|
||||
; nWE ; nROE ; ; 19.000 ; 19.000 ; ;
|
||||
; nWE ; nRWE ; 19.000 ; ; ; 19.000 ;
|
||||
; nIOSTRB ; nRCS ; ; 32.000 ; 32.000 ; ;
|
||||
; nIOSTRB ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
; nWE ; D[0] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[1] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[2] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[3] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[4] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[5] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[6] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; D[7] ; 39.000 ; ; ; 39.000 ;
|
||||
; nWE ; RD[0] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[1] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[2] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[3] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[4] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[5] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[6] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; RD[7] ; ; 39.000 ; 39.000 ; ;
|
||||
; nWE ; nROE ; ; 32.000 ; 32.000 ; ;
|
||||
; nWE ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||
+------------+-------------+--------+--------+--------+--------+
|
||||
|
||||
|
||||
@ -983,24 +971,24 @@ No paths to report.
|
||||
+-----------+------------+--------+------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+--------+------+------------+-----------------+
|
||||
; D[*] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[0] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[1] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[2] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[3] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[4] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[5] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[6] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[7] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[*] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[0] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[1] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[2] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[3] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[4] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[5] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[6] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[7] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[*] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[0] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[1] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[2] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[3] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[4] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[5] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[6] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[7] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[*] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[0] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[1] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[2] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[3] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[4] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[5] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[6] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[7] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
+-----------+------------+--------+------+------------+-----------------+
|
||||
|
||||
|
||||
@ -1009,24 +997,24 @@ No paths to report.
|
||||
+-----------+------------+--------+------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+--------+------+------------+-----------------+
|
||||
; D[*] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[0] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[1] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[2] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[3] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[4] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[5] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[6] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[7] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[*] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[0] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[1] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[2] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[3] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[4] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[5] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[6] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[7] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[*] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[0] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[1] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[2] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[3] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[4] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[5] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[6] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[7] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[*] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[0] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[1] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[2] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[3] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[4] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[5] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[6] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[7] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
+-----------+------------+--------+------+------------+-----------------+
|
||||
|
||||
|
||||
@ -1035,24 +1023,24 @@ No paths to report.
|
||||
+-----------+------------+-----------+-----------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-----------+-----------+------------+-----------------+
|
||||
; D[*] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[0] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[1] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[2] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[3] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[4] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[5] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[6] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[7] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[*] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[0] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[1] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[2] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[3] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[4] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[5] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[6] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[7] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[*] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[0] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[1] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[2] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[3] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[4] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[5] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[6] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[7] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[*] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[0] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[1] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[2] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[3] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[4] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[5] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[6] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[7] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
+-----------+------------+-----------+-----------+------------+-----------------+
|
||||
|
||||
|
||||
@ -1061,24 +1049,24 @@ No paths to report.
|
||||
+-----------+------------+-----------+-----------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-----------+-----------+------------+-----------------+
|
||||
; D[*] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[0] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[1] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[2] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[3] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[4] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[5] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[6] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[7] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[*] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[0] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[1] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[2] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[3] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[4] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[5] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[6] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; RD[7] ; C7M ; 28.000 ; ; Rise ; C7M ;
|
||||
; D[*] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[0] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[1] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[2] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[3] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[4] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[5] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[6] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; D[7] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[*] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[0] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[1] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[2] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[3] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[4] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[5] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[6] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
; RD[7] ; C7M ; 41.000 ; ; Rise ; C7M ;
|
||||
+-----------+------------+-----------+-----------+------------+-----------------+
|
||||
|
||||
|
||||
@ -1134,9 +1122,9 @@ No dedicated SERDES Receiver circuitry present in device or used in design
|
||||
; TimeQuest Timing Analyzer Messages ;
|
||||
+------------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
|
||||
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Tue Sep 03 14:09:19 2019
|
||||
Info: Processing started: Thu Sep 05 21:45:12 2019
|
||||
Info: Command: quartus_sta GR8RAM -c GR8RAM
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
@ -1153,7 +1141,7 @@ Critical Warning (332148): Timing requirements not met
|
||||
Info (332146): Worst-case setup slack is -47.500
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): -47.500 -1888.500 C7M
|
||||
Info (332119): -47.500 -1992.500 C7M
|
||||
Info (332119): -27.500 -33.000 C7M_2
|
||||
Info (332146): Worst-case hold slack is -1.500
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
@ -1170,10 +1158,10 @@ Info (332146): Worst-case minimum pulse width slack is -5.500
|
||||
Info (332001): The selected device family is not supported by the report_metastability command.
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
|
||||
Info: Peak virtual memory: 4530 megabytes
|
||||
Info: Processing ended: Tue Sep 03 14:09:20 2019
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
|
||||
Info: Peak virtual memory: 259 megabytes
|
||||
Info: Processing ended: Thu Sep 05 21:45:17 2019
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:05
|
||||
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@ TimeQuest Timing Analyzer Summary
|
||||
|
||||
Type : Setup 'C7M'
|
||||
Slack : -47.500
|
||||
TNS : -1888.500
|
||||
TNS : -1992.500
|
||||
|
||||
Type : Setup 'C7M_2'
|
||||
Slack : -27.500
|
||||
|
||||
Loading…
Reference in New Issue
Block a user