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This commit is contained in:
Zane Kaminski
2025-03-30 05:03:20 -04:00
parent 2e635072c8
commit d40c6cf8bf
312 changed files with 40965 additions and 319 deletions
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Documentation/Architecture.graffle
BIN
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Binary file not shown.
Hardware/LCMXO2/GR8RAM.kicad_pro
+55 -11
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@@ -3,14 +3,17 @@
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.15,
"copper_line_width": 0.15239999999999998,
"copper_line_width": 0.1524,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
@@ -21,13 +24,13 @@
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_line_width": 0.1,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
@@ -74,9 +77,11 @@
"duplicate_footprints": "error",
"extra_footprint": "error",
"footprint": "error",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
@@ -122,24 +127,21 @@
"min_copper_edge_clearance": 0.4064,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.5,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.15,
"min_via_annular_width": 0.09999999999999999,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
@@ -148,29 +150,35 @@
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
@@ -191,6 +199,32 @@
1.27,
1.524
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 1.0
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [
{
"diameter": 0.0,
@@ -220,6 +254,13 @@
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_presets": [],
"viewports": []
},
@@ -478,8 +519,11 @@
"gencad": "",
"idf": "",
"netlist": "GR8RAM.net",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
cpld/BusInterface.v
+167
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@@ -0,0 +1,167 @@
module BusInterface(
/* Clock signal inputs */
input CLK,
input PHI0,
/* Apple II reset input */
input nRES,
/* Card select signal inputs */
input nDEVSEL,
input nIOSEL,
input nIOSTRB,
/* Buffered address, write enable inputs */
input [10:0] BA,
input nWE,
/* Data bus mux inputs */
input [7:0] RDD,
input [23:0] Addr,
/* Buffered data bus output and BD buffer control */
inout [7:0] BD,
output nDoutOE,
output nDinOE,
/* Write data output to slinky registers and RAM controller */
output reg [7:0] WRD,
/* Bus command enable input from initialization controller */
input BusEnable,
/* SDRAM command outputs */
output reg RAMRD,
output reg RAMWR,
output reg ROMRD,
output reg RAMRef,
/* Register command outputs */
output reg BankWR,
output reg AddrInc,
output reg AddrHWR,
output reg AddrMWR,
output reg AddrLWR,
output reg RegReset);
/* PHI0 synchronization */
reg [4:0] PHI0r;
always @(negedge CLK) PHI0r[0] <= PHI0;
always @(posedge CLK) PHI0r[4:1] <= PHI0r[3:0];
wire PHI0rise = !PHI0r[2] && PHI0r[1];
/* Reset synchronization */
reg nRESr; always @(negedge PHI0) nRESr <= nRES;
/* Bus state counter
* S0 - idle/bus disabled
* S1-SB - PHI0
* SC - wait until PHI1
* SD-SF - PHI1 */
reg [3:0] S = 0;
always @(posedge CLK) begin
if (S==4'h0 && BusEnable && PHI0rise) S <= 4'h1;
else if (S==4'hC && !PHI0r[2]) S <= 4'hD;
else S <= S+4'h1;
end
/* Refresh counter */
reg [2:0] RefC;
wire [2:0] RefCTC = RefC[2:0]==3'h6;
always @(posedge CLK) begin
if (RefC==RefCTC) RefC <= 3'h0;
else RefC <= RefC+3'h1;
end
/* Register reset command generation */
always @(posedge CLK) begin
if (S==4'h0 && !BusEnable) RegReset <= 1;
else if (S==4'h1) RegReset <= !nRESr;
end
/* Register enable */
reg RegEN;
always @(posedge CLK) begin
if (RegReset) RegEN <= 0;
else if (S==4'h6 && !nIOSEL) RegEN <= 1;
end
/* IOSTRB ROM enable */
reg IOROMEN;
always @(posedge CLK) begin
if (RegReset) IOROMEN <= 0;
else if (S==4'h6 && !nIOSEL && BA[10:0]==11'h7FF) IOROMEN <= 0;
else if (S==4'h6 && !nIOSEL) IOROMEN <= 1;
end
/* Write data latch */
always @(negedge PHI0) WRD[7:0] <= BD[7:0];
/* Register and RAM write command generation */
reg BankWRpre;
reg RAMWRpre;
reg AddrHWRpre;
reg AddrMWRpre;
reg AddrLWRpre;
always @(posedge CLK) begin
if (S==6) begin
BankWRpre <= S==4'h6 && !nDEVSEL && BA[3:0]==4'hF && !nWE;
RAMWRpre <= S==4'h6 && !nDEVSEL && BA[3:0]==4'h3 && !nWE;
AddrHWRpre <= S==4'h6 && !nDEVSEL && BA[3:0]==4'h2 && !nWE;
AddrMWRpre <= S==4'h6 && !nDEVSEL && BA[3:0]==4'h1 && !nWE;
AddrLWRpre <= S==4'h6 && !nDEVSEL && BA[3:0]==4'h0 && !nWE;
end else if (S==0) begin
BankWRpre <= 0;
RAMWRpre <= 0;
AddrHWRpre <= 0;
AddrMWRpre <= 0;
AddrLWRpre <= 0;
end
BankWR <= S==4'hD && BankWRpre && RegEN;
RAMWR <= S==4'hD && RAMWRpre && RegEN;
AddrHWR <= S==4'hD && AddrHWRpre && RegEN;
AddrMWR <= S==4'hD && AddrMWRpre && RegEN;
AddrLWR <= S==4'hD && AddrLWRpre && RegEN;
end
/* Address increment command generation after RAMWR */
always @(posedge CLK) AddrInc <= S==4'hF && RAMWRpre;
/* RAM read command generation */
always @(posedge CLK) begin
RAMRD <= S==4'h6 && !nDEVSEL && BA[3:0]==4'h3 && nWE;
ROMRD <= S==4'h6 && (!nIOSEL || (!nIOSTRB && IOROMEN && BA[10:0]!=11'h7FF));
end
/* RAM refresh command generation */
always @(posedge CLK) RAMRef <= S==4'h1 && RefCTC;
/* Data bus output mux */
reg [7:0] BDout;
reg BDoutLE;
always @(posedge CLK) BDoutLE <= S==4'hB;
always @(posedge CLK) begin
if (BDoutLE) begin
if (nDEVSEL) BDout[7:0] <= RDD[7:0];
else case (BA[3:0])
4'hF: BDout[7:0] <= 0;
4'hE: BDout[7:0] <= 0;
4'hD: BDout[7:0] <= 0;
4'hC: BDout[7:0] <= 0;
4'hB: BDout[7:0] <= 0;
4'hA: BDout[7:0] <= 0;
4'h9: BDout[7:0] <= 0;
4'h8: BDout[7:0] <= 0;
4'h7: BDout[7:0] <= 8'h10; // Hex 10 (meaning firmware 1.0)
4'h6: BDout[7:0] <= 8'h41; // ASCII "B" (meaning rev. B)
4'h5: BDout[7:0] <= 8'h05; // Hex 05 (meaning "4205")
4'h4: BDout[7:0] <= 8'h47; // ASCII "G" (meaning "GW")
4'h3: BDout[7:0] <= RDD[7:0];
4'h2: BDout[7:0] <= Addr[23:16];
4'h1: BDout[7:0] <= Addr[15:8];
4'h0: BDout[7:0] <= Addr[7:0];
endcase
end
end
/* Card select signal */
wire CardSEL = !nDEVSEL || !nIOSEL || (!nIOSTRB && IOROMEN && BA[10:0]!=11'h7FF);
/* Data bus buffer OE control */
assign nDinOE = !(PHI0 && !nWE);
assign nDoutOE = !(CardSEL && nWE && PHI0r[4] && PHI0);
wire BDOE = (CardSEL && nWE && PHI0r[4]);
assign BD[7:0] = BDOE ? BDout[7:0] : 8'bZ;
endmodule
cpld/GR8RAM-LCMXO2.lpf
+149
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@@ -0,0 +1,149 @@
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "PHI0" SITE "17" ;
LOCATE COMP "MISO" SITE "98" ;
LOCATE COMP "BA[0]" SITE "74" ;
LOCATE COMP "BA[1]" SITE "78" ;
LOCATE COMP "BA[2]" SITE "83" ;
LOCATE COMP "BA[3]" SITE "84" ;
LOCATE COMP "BA[4]" SITE "4" ;
LOCATE COMP "BA[5]" SITE "85" ;
LOCATE COMP "BA[6]" SITE "86" ;
LOCATE COMP "BA[7]" SITE "87" ;
LOCATE COMP "BA[8]" SITE "99" ;
LOCATE COMP "BA[9]" SITE "2" ;
LOCATE COMP "BA[10]" SITE "3" ;
LOCATE COMP "BA[11]" SITE "8" ;
LOCATE COMP "BA[12]" SITE "9" ;
LOCATE COMP "BA[13]" SITE "10" ;
LOCATE COMP "BA[14]" SITE "13" ;
LOCATE COMP "BA[15]" SITE "14" ;
LOCATE COMP "SW[1]" SITE "64" ;
LOCATE COMP "SW[2]" SITE "63" ;
LOCATE COMP "nDEVSEL" SITE "16" ;
LOCATE COMP "nIOSEL" SITE "15" ;
LOCATE COMP "nIOSTRB" SITE "18" ;
LOCATE COMP "nRESin" SITE "20" ;
LOCATE COMP "nWE" SITE "19" ;
LOCATE COMP "DQMH" SITE "34" ;
LOCATE COMP "DQML" SITE "32" ;
LOCATE COMP "RCKE" SITE "40" ;
LOCATE COMP "RA[0]" SITE "54" ;
LOCATE COMP "RA[1]" SITE "59" ;
LOCATE COMP "RA[2]" SITE "58" ;
LOCATE COMP "RA[3]" SITE "60" ;
LOCATE COMP "RA[4]" SITE "51" ;
LOCATE COMP "RA[5]" SITE "52" ;
LOCATE COMP "RA[6]" SITE "62" ;
LOCATE COMP "RA[7]" SITE "57" ;
LOCATE COMP "RA[8]" SITE "53" ;
LOCATE COMP "RA[9]" SITE "49" ;
LOCATE COMP "RA[10]" SITE "47" ;
LOCATE COMP "RA[11]" SITE "45" ;
LOCATE COMP "RA[12]" SITE "42" ;
LOCATE COMP "RBA[0]" SITE "43" ;
LOCATE COMP "RBA[1]" SITE "48" ;
LOCATE COMP "FCK" SITE "96" ;
LOCATE COMP "nFCS" SITE "88" ;
LOCATE COMP "nCAS" SITE "36" ;
LOCATE COMP "nDinOE" SITE "77" ;
LOCATE COMP "nDoutOE" SITE "1" ;
LOCATE COMP "nIRQout" SITE "12" ;
LOCATE COMP "nRAS" SITE "37" ;
LOCATE COMP "nRCS" SITE "41" ;
LOCATE COMP "nRESout" SITE "7" ;
LOCATE COMP "nRWE" SITE "35" ;
LOCATE COMP "MOSI" SITE "97" ;
LOCATE COMP "BD[0]" SITE "65" ;
LOCATE COMP "BD[1]" SITE "66" ;
LOCATE COMP "BD[2]" SITE "67" ;
LOCATE COMP "BD[3]" SITE "68" ;
LOCATE COMP "BD[4]" SITE "69" ;
LOCATE COMP "BD[5]" SITE "70" ;
LOCATE COMP "BD[6]" SITE "71" ;
LOCATE COMP "RD[0]" SITE "25" ;
LOCATE COMP "RD[1]" SITE "24" ;
LOCATE COMP "RD[2]" SITE "21" ;
LOCATE COMP "RD[3]" SITE "27" ;
LOCATE COMP "RD[4]" SITE "28" ;
LOCATE COMP "RD[5]" SITE "29" ;
LOCATE COMP "RD[6]" SITE "30" ;
LOCATE COMP "RD[7]" SITE "31" ;
LOCATE COMP "BD[7]" SITE "75" ;
IOBUF PORT "PHI0" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "MISO" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "BA[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "SW[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "SW[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "nDEVSEL" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "nIOSEL" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "nIOSTRB" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "nRESin" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "nWE" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "DQMH" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "DQML" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RCKE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RA[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "FCK" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=24 SLEWRATE=FAST ;
IOBUF PORT "nFCS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 ;
IOBUF PORT "nCAS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "nDinOE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "nDoutOE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "nIRQout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "nRAS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "nRCS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "nRESout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "nRWE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
IOBUF PORT "MOSI" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "BD[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "BD[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "BD[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "BD[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "BD[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "BD[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "BD[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "BD[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "RD[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "RD[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "RD[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "RD[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "RD[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "RD[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "RD[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "RD[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
IOBUF PORT "CLKin" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
LOCATE COMP "CLKin" SITE "38" ;
LOCATE COMP "RCLK" SITE "39" ;
IOBUF PORT "RCLK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=24 SLEWRATE=FAST ;
VOLTAGE 3.300 V;
LOCATE COMP "LED" SITE "81" ;
IOBUF PORT "LED" IO_TYPE=LVCMOS33 DRIVE=24 PULLMODE=NONE ;
cpld/GR8RAM-LCMXO2.mem
+7
View File
@@ -0,0 +1,7 @@
// Auto-generated by memint 08/19/2023 20:50:21
#Format=Hex
#Depth=16
#Width=8
#AddrRadix=3
#DataRadix=3
#Data
cpld/GR8RAM.sdc
+2
View File
@@ -0,0 +1,2 @@
create_clock [get_nets CLK] -period 22.558087ns
create_clock [get_ports PHI0] -period 977ns
cpld/GR8RAM.v
+164 -308
View File
@@ -1,334 +1,190 @@
module GR8RAM2(
/* Clock signals */
input C25M,
module GR8RAM(
/* Apple II PHI0 clock */
input PHI0,
/* 25 MHz crystal oscillator input (not usually mounted) */
input CLKin /* synthesis syn_force_pads=1 syn_noprune=1 */,
/* LED output */
output LED,
/* Reset and IRQ */
input nRESin,
output reg nRESout,
input [1:0] SetFW,
output reg nIRQout,
input [15:0] BA,
output nRESout,
output nIRQout,
/* DIP switch inputs */
input [2:1] SW,
/* Buffered address, write enable, data buses */
input [15:0] BA /* synthesis syn_force_pads=1 syn_noprune=1 */,
input nWE,
inout [7:0] BD,
output BDdir,
output nDoutOE,
output nDinOE,
/* Card select signals */
input nIOSEL,
input nDEVSEL,
input nIOSTRB,
/* SDRAM bus */
output reg [1:0] RBA,
output reg [12:0] RA,
output RCLK,
output [1:0] RBA,
output [12:0] RA,
output nRCS,
output reg nRAS,
output reg nCAS,
output reg nRWE,
output reg DQML,
output reg DQMH,
output reg RCKE,
output reg [7:0] RD,
output RCKE,
output nRAS,
output nCAS,
output nRWE,
output DQML,
output DQMH,
inout [7:0] RD,
/* SPI NOR flash */
output reg nFCS,
output reg FCK,
inout MISO,
inout MOSI);
/* PHI0 synchronization signals */
reg PHI0r0, PHI0r1;
always @(negedge C25M) begin PHI0r0 <= PHI0; end
always @(posedge C25M) begin PHI0r1 <= PHI0r0; end
inout nFCS,
output FCK,
inout MOSI,
input MISO);
/* Reset synchronization */
reg nRESr0, nRESr;
always @(negedge C25M) nRESr0 <= nRESin;
always @(posedge C25M) nRESr <= nRESr0;
wire RES = RES;
assign LED = 1;
/* Internal clock */
wire CLK;
defparam OSCH_inst.NOM_FREQ = "44.33";
OSCH OSCH_inst(.STDBY(1'b0), .OSC(CLK), .SEDSTDBY());
/* Firmware select */
input [1:0] SetFW;
reg [1:0] SetFWr;
reg SetFWLoaded = 0;
always @(posedge C25M) begin
if (!SetFWLoaded) begin
SetFWLoaded <= 1;
SetFWr[1:0] <= SetFW[1:0];
end
end
wire [1:0] SetROM = ~SetFWr[1:0];
wire SetEN16MB = SetROM[1:0]==2'b11;
wire SetEN24b = SetROM[1];
/* Apple II bus interface */
wire [7:0] BI_WRD;
wire BI_RAMRD, BI_ROMRD, BI_RAMWR, BI_RAMRef;
wire AddrHWR, AddrMWR, AddrLWR, AddrInc, BankWR, RegReset;
/* State counters */
reg [2:0] IS = 0;
reg [24:0] S = 0;
wire Ready = IS[2];
/* Slinky address and ROM bank registers */
wire [23:0] Addr;
wire Bank;
/* Reset output disable */
assign nRESout = Ready;
/* Init controller */
wire InitDone;
wire [2:0] IC_RAMCmd;
wire [24:0] IC_Addr;
wire [7:0] IC_WRD;
wire [1:0] SetSize;
wire SetRamFactorEN;
wire SetRestoreEN;
/* SDRAM controller */
wire [7:0] RDD;
/* Init state counter control */
// IS 0 - wait and issue NOP CKE (ends at S[19:0]==20'hFFFFF)
// IS 1 - Load mode and AREF, issue SPI NOR read (ends at S[4:0]==5'h3F)
// IS 2 - Write driver (ends at S[16:0]==17'h1FFFF)
// IS 3 - Write image (ends at S[24:0]==25'h1FFFFFF)
// IS 7 - Operating mode
always @(posedge C25M) begin
case (IS[2:0]) begin
3'h0: if (S[19:0]== 20'hFFFFF) IS[2:0] <= 3'h1;
3'h1: if (S[19:0]== 5'h3F) IS[2:0] <= 3'h2;
3'h2: if (S[19:0]== 17'h1FFFF) IS[2:0] <= 3'h3;
3'h3: if (S[19:0]==25'h1FFFFFF) IS[2:0] <= 3'h7;
end
end
/* Apple II bus interface */
BusInterface bi(
/* Clock signal inputs */
.CLK(CLK),
.PHI0(PHI0),
/* Apple II reset input */
.nRES (nRESin),
/* Card select signal inputs */
.nDEVSEL(nDEVSEL),
.nIOSEL(nIOSEL),
.nIOSTRB(nIOSTRB),
/* Buffered address, write enable inputs */
.BA(BA[10:0]),
.nWE(nWE),
/* Data bus mux inputs */
.RDD(RDD),
.Addr(Addr),
/* Data bus output and BD buffer control */
.BD(BD),
.nDoutOE(nDoutOE),
.nDinOE(nDinOE),
/* Write data output to slinky registers and RAM controller */
.WRD(BI_WRD),
/* Initialization done input from initialization controller */
.BusEnable(InitDone),
/* SDRAM command outputs */
.RAMRD(BI_RAMRD),
.ROMRD(BI_ROMRD),
.RAMWR(BI_RAMWR),
.RAMRef(BI_RAMRef),
/* Register command outputs */
.AddrHWR(AddrHWR),
.AddrMWR(AddrMWR),
.AddrLWR(AddrLWR),
.AddrInc(AddrInc),
.BankWR(BankWR),
.RegReset(RegReset));
/* RAM state counter control */
always @(posedge C25M) begin
if (IS[2:0]==3'h0 && S[19:0]== 20'hFFFFF ||
IS[2:0]==3'h1 && S[19:0]== 5'h3F ||
IS[2:0]==3'h2 && S[19:0]== 17'h1FFFF ||
IS[2:0]==3'h3 && S[19:0]==25'h1FFFFFF) S <= 0;
else if (Ready) begin
S[24:4] <= 0;
if (S[3:0]==0 && PHI0r1) S[2:0] <= 4'h1;
else if (S[3:0]!=0) S[3:0] <= S[3:0]+4'h1;
end else S[24:0] <= S[24:0]+25'h1;
end
/* IOROMEN control */
reg IOROMEN = 0;
always @(posedge C25M) begin
if (RES) IOROMEN <= 0;
else if (S[2:0]==3'h2) begin
if (!nIOSTRB && BA[10:0]==11'h7FF) IOROMEN <= 0;
else if (!nIOSEL) IOROMEN <= 1;
end
end
/* Slinky address and ROM bank registers */
SlinkyRegisters registers(
/* Clock signal */
.CLK(CLK),
/* Slinky/RamFactor mode bit */
.SetRamFactorEN(SetRamFactorEN),
/* Register command inputs */
.AddrHWR(AddrHWR),
.AddrMWR(AddrMWR),
.AddrLWR(AddrLWR),
.AddrInc(AddrInc),
.BankWR(BankWR),
.RegReset(RegReset),
/* Write data input */
.WRD(BI_WRD),
/* Slinky address register output */
.Addr(Addr),
/* ROM bank register output */
.Bank(Bank));
/* RegEN control */
reg RegEN = 0;
always @(posedge C25M) begin
if (RES) RegEN <= 0;
else if (S[2:0]==3'h2 && !nIOSEL) RegEN <= 1;
end
/* ROM bank register */
reg Bank = 0;
always @(posedge C25M, negedge nRESr) begin
if (RES) Bank <= 0;
else if (S[2:0]==3'h4 && BankSEL && !nWEr) begin
Bank <= RD[0];
end
end
/* Init controller */
InitController ic(
/* Clock signal */
.CLK(CLK),
/* Settings input and outputs */
.SW({ RD[0], SW[2:1] }),
.SetSize(SetSize),
.SetRamFactorEN(SetRamFactorEN),
.SetRestoreEN(SetRestoreEN),
/* Initialization done and POR outputs */
.InitDone(InitDone),
/* SDRAM command outputs */
.RAMCmd(IC_RAMCmd),
.RAMAddr(IC_Addr),
/* SDRAM write data output */
.WRD(IC_WRD),
/* SPI flash bus */
.nFCS(nFCS),
.FCK(FCK),
.MOSI(MOSI),
.MISO(MISO));
/* RAMROMCS command signal */
reg RAMROMCS;
always @(posedge C25M) begin
if (S[3:0]==4'h0) RAMROMCS <= !RES &&PHI0r1 && BA[15:12]==4'hC;
else if S[3:0]==4'h1) begin
RAMROMCS <= !RES && (
(!nIOSEL) ||
(!nIOSTRB && IOROMEN) ||
(!nDEVSEL && RegEN && A[3:0]==4'h3));
end else if (S[3:0]==4'h9) RAMROMCS <= !RES && RefC[2:0]==0;
end
/* Register select command signals */
reg RAMRegSEL;
reg AddrHWR, AddrMWR, AddrLWR;
always @(posedge C25M) begin
RAMRegSEL <= !RES && S[3:0]==4'h6 !nDEVSEL && BA[3:0]==4'h3;
AddrHWR <= !RES && S[3:0]==4'h6 !nDEVSEL && BA[3:0]==4'h2;
AddrMWR <= !RES && S[3:0]==4'h6 !nDEVSEL && BA[3:0]==4'h1;
AddrLWR <= !RES && S[3:0]==4'h6 !nDEVSEL && BA[3:0]==4'h0;
end
/* SDRAM controller */
SDRAMController ram(
/* Clock signal */
.CLK(CLK),
/* POR input from init controller */
.InitDone(InitDone),
/* Command inputs from bus interface */
.BI_RAMRD(BI_RAMRD),
.BI_RAMWR(BI_RAMWR),
.BI_RAMRef(BI_RAMRef),
.Addr(Addr),
.BD(BD),
/* Command inputs from init controller */
.IC_RAMCmd(IC_RAMCmd),
.IC_Addr(IC_Addr),
.IC_WRD(IC_WRD),
/* SDRAM bus */
.RCLK(RCLK),
.RBA(RBA),
.RA(RA),
.nRCS(nRCS),
.RCKE(RCKE),
.nRAS(nRAS),
.nCAS(nCAS),
.nRWE(nRWE),
.DQML(DQML),
.DQMH(DQMH),
.RD(RD),
/* SDRAM read data */
.RDD(RDD));
/* Slinky address registers */
reg [23:0] Addr = 0;
reg AddrIncL = 0;
reg AddrIncM = 0;
reg AddrIncH = 0;
always @(posedge C25M, negedge nRESr) begin
if (RES) begin
Addr[23:0] <= 0;
AddrIncL <= 0;
AddrIncM <= 0;
AddrIncH <= 0;
end else begin
if (RAMRegSEL) AddrIncL <= 1;
else AddrIncL <= 0;
/* Reset output is InitDone */
assign nRESout = InitDone;
if (AddrLWR) begin
Addr[7:0] <= RD[7:0];
AddrIncM <= Addr[7] && !RD[7];
end else if (AddrIncL) begin
Addr[7:0] <= Addr[7:0]+1;
AddrIncM <= Addr[7:0]==8'hFF;
end else AddrIncM <= 0;
/* IRQ always disabled */
assign nIRQout = 1;
if (AddrMWR) begin
Addr[15:8] <= RD[7:0];
AddrIncH <= Addr[15] && !RD[7];
end else if (AddrIncM) begin
Addr[15:8] <= Addr[15:8]+1;
AddrIncH <= Addr[15:8]==8'hFF;
end else AddrIncH <= 0;
if (AddrHWR) begin
Addr[23:16] <= RD[7:0];
end else if (AddrIncH) begin
Addr[23:16] <= Addr[23:16]+1;
end
end
end
/* Apple II data output latch */
reg [7:0] BDout;
always @(negedge C25M) begin
if (S[2:0]==4'h6) begin
if (!nDEVSEL) case (BA[1:0])
4'h3: BDout[7:0] <= RD[7:0];
4'h2: BDout[7:0] <= SetEN24b ? Addr[23:16] { 4'hF, Addr[19:16] };
4'h1: BDout[7:0] <= Addr[15:8];
4'h0: BDout[7:0] <= Addr[7:0];
defaut: BDout[7:0] <= 0;
endcase else BDout[7:0] <= RD[7:0];
end
end
always @(posedge C25M) begin
case (IS[2:0])
3'h0: begin
// NOP CKE
end 3'h1: case (S[4:0])
5'h00: begin
// PC all CKE
end 5'h08: begin
// LDM CKE
end 5'h10, 5'h12, 5'h14, 5'h16,
5'h18, 5'h1A, 5'h1C, 5'h1E: begin
// AREF CKE
end default: begin
// NOP CKE
end
endcase 3'h2, 3'h3: case (S[2:0])
3'h0: begin
// NOP CKE
end 3'h1: begin
// AREF CKE
end 3'h2: begin
// NOP CKE
end 3'h3: begin
// ACT CKE
end 3'h4: begin
// WR CKE
end 3'h5: begin
// WR CKE
end 3'h6: begin
// NOP CKE
end 3'h7: begin
// PC all CKD
end
endcase default: case (S[3:0])
4'h1: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// NOP CKE
end else begin
// NOP CKD
end
end 4'h2: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// ACT CKE
end else begin
// NOP CKD
end
end 4'h3: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// RD CKE
end else begin
// NOP CKD
end
end 4'h4: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// PC all CKE
end else begin
// NOP CKD
end
end 4'h5: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// NOP CKD
end else begin
// NOP CKE
end
end 4'h6: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// NOP CKD
end else begin
// ACT CKE
end
end 4'h7: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// NOP CKD
end else begin
// WR CKE
end
end 4'h8: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// NOP CKD
end else begin
// NOP CKE
end
end 4'h9: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// NOP CKD
end else begin
// PC all CKD
end
end 4'hA: begin
if (!RAMROMCS) begin
// NOP CKD
end else begin
// NOP CKE
end
end 4'hB: begin
if (!RAMROMCS) begin
// NOP CKD
end else begin
// AREF CKE
end
end default: begin
// NOP CKD
end
endcase
endcase
end
/* DMA/INT in/out */
input INTin, DMAin;
output INTout = INTin;
output DMAout = DMAin;
/* Unused Pins */
output RAdir = 1;
output nDMAout = 1;
output nNMIout = 1;
output nINHout = 1;
output nRDYout = 1;
output nIRQout = 1;
output RWout = 1;
endmodule
cpld/IIci PDS (75)
+45
View File
@@ -0,0 +1,45 @@
SE/30 PDS (54)
--------
(1) CPUCLK
(32) AD[31:0]
(3) ALE, nAOE, nDOE
(2) /RESETin, /RESETout
(5) /AS, /DS, R/W, SIZ[1:0]
(5) /DSACK[1:0], /STERM, /BERR, /HALT
(2) /BR, /BG
(3) /IPL[2:0]
(1) /IRQ
SDRAM (29)
--------
(4) RCLK[3:0]
(15) RBA[1:0], RA[12:0]
(2) /CS[1:0]
(4) DQM[3:0]
(4) CKE, /RAS, /CAS, /WE
SRAM (9)
--------
(6) /L2OE, /L2WE, /B[3:0]
(3) /GCOE, /GSTERM, /GSTERMEN, /GRDOE, /GRDOEEN
/DCOE
ROM (6)
--------
(4) FCK[1:0], /CS[1:0]
(2) MISO, MOSI
Fast CPU (84)
--------
(2) CPUCLK, FPUCLK
(35) FC[2:0], A[31:0]
(32) D[31:0]
(3) /BALOE
(6) /AS, SIZ[1:0], R/W, /RMC, /CBREQ
(5) /DSACK[1:0], /CBACK, /HALT, /BERR
(1) /FSTERMD
Link (10)
--------
(2) LCLK, /LSOF
(8) LD[7:0]
cpld/InitController.v
+489
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@@ -0,0 +1,489 @@
module InitController(
/* Clock signal */
input CLK,
/* Settings input and outputs */
input [3:1] SW,
output reg [1:0] SetSize,
output reg SetRamFactorEN,
output reg SetRestoreEN,
/* Initialization done and POR outputs */
output reg InitDone,
/* SDRAM command outputs */
output reg [2:0] RAMCmd,
output reg [24:0] RAMAddr,
/* SDRAM write data output */
output reg [7:0] WRD,
/* SPI flash bus */
inout nFCS,
output FCK,
inout MOSI,
input MISO);
/* RAM command definitions */
`define RC_NOP (3'h0)
`define RC_LDM (3'h1)
`define RC_ACT (3'h2)
`define RC_WR (3'h3)
`define RC_PC (3'h4)
`define RC_Ref (3'h5)
/* Init state */
reg [12:0] CS = 0;
reg [12:0] LS = 0;
reg [3:0] IS = 0;
/* /FCS output */
reg FOE = 0;
reg nFCSout;
wire nFCSin;
BB fcs_bb(.I(nFCSout), .T(FOE), .O(nFCSin), .B(nFCS));
/* FCK output */
reg FCKEN;
wire FCKout;
ODDRX1F fck_oddr(.D0(1'b0), .D1(FCKEN),
.SCLK(CLK), .RST(1'b0), .Q(FCKout));
OBZ fck_iobz(.I(FCKout), .T(FOE), .O(FCK));
/* MOSI output */
reg MOSIOE = 0;
reg MOSIout;
wire MOSIin;
BB mosi_bb(.I(MOSIout), .T(MOSIOE), .O(MOSIin), .B(MOSI));
/* Flash alternate master detect */
reg FlashProgDetected;
always @(posedge CLK) begin
if (IS==0) FlashProgDetected <= 0;
else if (!nFCSin) FlashProgDetected <= 1;
end
/* CS (command state) control -- lowest order */
wire CSTC = CS[12:0]==13'h103F;
always @(posedge CLK) begin
if (CSTC) CS[12:0] <= 0;
else CS[12:0] <= CS+13'h0001;
end
/* LS (long state) control -- medium order */
wire LSTC =
IS==0 ? LS[12:0]==13'h003F : // POR pause
IS==1 ? LS[12:0]==13'h01FF : // Check to see if flash programmer attached
IS==2 ? LS[12:0]==13'h0000 : // Issue flash command
IS==3 ? LS[12:0]==13'h0007 : // Load flash to RAM
IS==4 ? LS[12:0]==13'h0000 : // End flash command
IS==5 ? LS[12:0]==13'h0000 : // Issue flash command
IS==6 ? LS[12:0]==13'h1FFF : // Load flash to RAM
IS==7 ? LS[12:0]==13'h0000 : // End flash command
IS==8 ? LS[12:0]==13'h0000 : // Operation mode
IS==9 ? LS[12:0]==13'h0000 : // Inhibit mode
1; // Other
always @(posedge CLK) begin
if (CSTC) begin
if (LSTC) LS <= 0;
else LS <= LS+13'h0001;
end
end
/* IS (init state) control -- high order */
always @(posedge CLK) begin
if (LSTC && CSTC) case (IS)
4'h0: IS <= 4'h1;
4'h1: IS <= FlashProgDetected ? 4'h9 : 4'h2;
4'h2, 4'h3, 4'h4, 4'h5, 4'h6, 4'h7: IS <= IS+4'h1;
4'h8: IS <= 4'h8;
4'h9: IS <= 4'h9;
default: IS <= 4'h9;
endcase
end
/* Apple II reset output control */
always @(posedge CLK) InitDone <= IS==8;
/* RAM write address generation */
wire [24:0] RAMDriverAddr = 25'h1000000;
wire [24:0] RAMImageAddr = 25'h0000000;
always @(posedge CLK) RAMAddr[24:0] <=
IS==3 ? { RAMDriverAddr[24:13], LS[2:0], CS[11:2] } :
IS==6 ? { RAMImageAddr[24:23], LS[12:0], CS[11:2] } :
25'h1FFFFFF;
/* Flash driver address */
wire [23:0] FlashDriverRFAddr = 24'hFF8000;
wire [23:0] FlashDriverSlinkyAddr = 24'hFF0000;
wire [23:0] FlashDriverAddr =
SetRamFactorEN ? FlashDriverRFAddr : FlashDriverSlinkyAddr;
/* Flash image address */
wire [23:0] FlashImageRF1MBAddr = 24'h900000;
wire [23:0] FlashImageSlinky1MBAddr = 24'h800000;
wire [23:0] FlashImageRF8MBAddr = 24'h000000;
wire [23:0] FlashImageAddr =
(SetRamFactorEN && SetSize==2'b00) ? FlashImageRF1MBAddr :
(SetRamFactorEN && SetSize!=2'b00) ? FlashImageRF8MBAddr :
FlashImageSlinky1MBAddr;
/* Flash address */
wire [23:0] FlashAddr =
(IS==1) ? FlashDriverAddr[23:0] : FlashImageAddr[23:0];
/* Flash command */
wire [7:0] FlashCommand = 8'h3B;
/* Settings decode */
always @(posedge CLK) begin
if (IS==0 && LSTC && CSTC) case (SW[2:1])
2'b00: begin // 16 MB RamFactor
SetSize <= 2'b11;
SetRamFactorEN <= 1;
SetRestoreEN <= 0;
end 2'b01: begin // 8 MB RamFactor
SetSize <= 2'b01;
SetRamFactorEN <= 1;
SetRestoreEN <= /*!*/SW[3];
end 2'b10: begin // 1 MB RamFactor
SetSize <= 2'b00;
SetRamFactorEN <= 1;
SetRestoreEN <= /*!*/SW[3];
end 2'b11: begin // 1 MB Slinky
SetSize <= 2'b00;
SetRamFactorEN <= 0;
SetRestoreEN <= /*!*/SW[3];
end
endcase
end
/* SPI flash control */
always @(posedge CLK) begin
case (IS)
0, 1: begin // POR pause and flash check
FOE <= 0;
nFCSout <= 1;
FCKEN <= 0;
MOSIOE <= 0;
MOSIout <= 0;
RAMCmd <= `RC_NOP;
end 2, 5: begin
FOE <= 1;
case (CS[12:0]) // Send command
13'h0000: begin
nFCSout <= 1;
FCKEN <= 0;
MOSIout <= 0;
MOSIOE <= 1;
RAMCmd <= `RC_PC;
end 13'h0004: begin
nFCSout <= 1;
FCKEN <= 0;
MOSIout <= 0;
MOSIOE <= 1;
RAMCmd <= `RC_LDM;
end 13'h0008, 13'h000C,
13'h0010, 13'h0014, 13'h0018, 13'h001C,
13'h0020, 13'h0024, 13'h0028, 13'h002C,
13'h0030, 13'h0034, 13'h0038, 13'h003C,
13'h0040, 13'h0044, 13'h0048, 13'h004C,
13'h0050, 13'h0054, 13'h0058, 13'h005C,
13'h0060, 13'h0064, 13'h0068, 13'h006C,
13'h0070, 13'h0074, 13'h0078, 13'h007C: begin
nFCSout <= 1;
FCKEN <= 0;
MOSIout <= 0;
MOSIOE <= 1;
RAMCmd <= `RC_Ref;
end 13'h1010, 13'h1011, 13'h1012, 13'h1013,
13'h1014, 13'h1015, 13'h1016: begin // /CS low
nFCSout <= 0;
FCKEN <= 0;
MOSIout <= 0;
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1017: begin // Command bit 7 (0x3B)
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashCommand[7];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1018: begin // Command bit 6 (0x3B)
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashCommand[6];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1019: begin // Command bit 5 (0x3B)
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashCommand[5];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h101A: begin // Command bit 4 (0x3B)
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashCommand[4];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h101B: begin // Command bit 3 (0x3B)
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashCommand[3];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h101C: begin // Command bit 2 (0x3B)
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashCommand[2];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h101D: begin // Command bit 1 (0x3B)
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashCommand[1];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h101E: begin // Command bit 0 (0x3B)
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashCommand[0];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h101F: begin // Address bit 23
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[23];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1020: begin // Address bit 22
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[22];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1021: begin // Address bit 21
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[23];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1022: begin // Address bit 20
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[20];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1023: begin // Address bit 19
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[19];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1024: begin // Address bit 18
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[18];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1025: begin // Address bit 17
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[17];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1026: begin // Address bit 16
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[16];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1027: begin // Address bit 15
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[15];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1028: begin // Address bit 14
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[14];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1029: begin // Address bit 13
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[13];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h102A: begin // Address bit 12
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[12];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h102B: begin // Address bit 11
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[11];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h102C: begin // Address bit 10
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[10];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h102D: begin // Address bit 9
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[9];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h102E: begin // Address bit 8
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[8];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h102F: begin // Address bit 7
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[7];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1030: begin // Address bit 6
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[6];
MOSIOE <= 1;
RAMCmd <= `RC_Ref;
end 13'h1031: begin // Address bit 5
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[5];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1032: begin // Address bit 4
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[4];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1033: begin // Address bit 3
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[3];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1034: begin // Address bit 2
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[2];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1035: begin // Address bit 1
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[1];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1036: begin // Address bit 0
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= FlashAddr[0];
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end 13'h1037: begin // First dummy bit
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= 0;
MOSIOE <= 0;
RAMCmd <= `RC_NOP;
end 13'h1038, 13'h1039, 13'h103A, // Dummy bits 2-8
13'h103B, 13'h103C, 13'h103D, 13'h103E: begin
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= 0;
MOSIOE <= 0;
RAMCmd <= `RC_NOP;
end 13'h103F: begin // First data bit output
nFCSout <= 0;
FCKEN <= 1;
MOSIout <= 0;
MOSIOE <= 0;
RAMCmd <= `RC_NOP;
end default: begin
nFCSout <= 1;
FCKEN <= 0;
MOSIout <= 0;
MOSIOE <= 1;
RAMCmd <= `RC_NOP;
end
endcase
end 3, 6: begin // Load flash to RAM
FOE <= 1;
nFCSout <= 0;
MOSIout <= 0;
MOSIOE <= 0;
if (!CS[12]) begin
FCKEN <= 1;
if (CS[11:0]==0) RAMCmd <= `RC_ACT;
else if (CS[1:0]==2'b11) RAMCmd <= `RC_WR;
else RAMCmd <= `RC_NOP;
end else begin
FCKEN <= 0;
case (CS)
13'h1002: RAMCmd <= `RC_PC;
13'h1004, 13'h1008, 13'h100C,
13'h1010, 13'h1014, 13'h1018, 13'h101C,
13'h1020, 13'h1024, 13'h1028, 13'h102C,
13'h1030, 13'h1034, 13'h1038, 13'h103C: RAMCmd <= `RC_Ref;
default: RAMCmd <= `RC_NOP;
endcase
end
end 4, 7: begin // End flash command
FOE <= 1;
nFCSout <= 1;
FCKEN <= 0;
MOSIout <= 0;
MOSIOE <= 0;
case (CS)
13'h1002: RAMCmd <= `RC_PC;
13'h1004, 13'h1008, 13'h100C,
13'h1010, 13'h1014, 13'h1018, 13'h101C,
13'h1020, 13'h1024, 13'h1028, 13'h102C,
13'h1030, 13'h1034, 13'h1038, 13'h103C: RAMCmd <= `RC_Ref;
default: RAMCmd <= `RC_NOP;
endcase
end 8: begin // Operating mode
FOE <= 1;
nFCSout <= 1;
FCKEN <= 0;
MOSIout <= 0;
MOSIOE <= 0;
RAMCmd <= `RC_NOP;
end 9: begin // Flash sleep
FOE <= 0;
nFCSout <= 1;
FCKEN <= 0;
MOSIout <= 0;
MOSIOE <= 0;
RAMCmd <= `RC_NOP;
end default: begin // Else
FOE <= 1;
nFCSout <= 1;
FCKEN <= 0;
MOSIout <= 0;
MOSIOE <= 0;
RAMCmd <= `RC_NOP;
end
endcase
end
/* MISO and MOSI capture on falling edge */
reg MISOr, MOSIr;
always @(negedge CLK) MISOr <= MISO;
always @(negedge CLK) MOSIr <= MOSIin;
/* Input data shift register */
always @(posedge CLK) begin
WRD[7:0] <= SetRestoreEN ? { WRD[5:0], MISOr, MOSIr } : 8'h00;
end
endmodule
cpld/LCMXO2-1200HC/.run_manager.ini
+9
View File
@@ -0,0 +1,9 @@
[Runmanager]
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
[impl1%3CStrategy1%3E]
isChecked=false
isHidden=false
isExpanded=false
cpld/LCMXO2-1200HC/.setting.ini
+4
View File
@@ -0,0 +1,4 @@
[General]
Export.auto_tasks=Jedecgen
PAR.auto_tasks=@@empty()
AutoAssign=true
cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC.ldf
+14
View File
@@ -0,0 +1,14 @@
<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="GR8RAM_LCMXO2_1200HC" device="LCMXO2-1200HC-4TG100C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="GR8RAM"/>
<Source name="../GR8RAM.v" type="Verilog" type_short="Verilog">
<Options top_module="GR8RAM"/>
</Source>
<Source name="../GR8RAM-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="GR8RAM_LCMXO2_1200HC1.sty"/>
</BaliProject>
cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC1.sty
+203
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@@ -0,0 +1,203 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE strategy>
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
<Property name="PROP_PAR_parHold" value="On" time="0"/>
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
<Property name="PROP_SYN_LibPath" value="" time="0"/>
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
</Strategy>
cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC_tcl.html
+70
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<HTML>
<HEAD><TITLE>Lattice TCL Log</TITLE>
<STYLE TYPE="text/css">
<!--
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC_tcr.dir/pn240613003303.tcr
+5
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#Start recording tcl command: 6/13/2024 00:16:33
#Project Location: //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC; Project name: GR8RAM_LCMXO2_1200HC
prj_project open "//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC.ldf"
prj_run Export -impl impl1
#Stop recording: 6/13/2024 00:33:03
cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC_tcr.dir/pn240614200121.tcr
+6
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#Start recording tcl command: 6/13/2024 00:37:49
#Project Location: //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC; Project name: GR8RAM_LCMXO2_1200HC
prj_project open "//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
#Stop recording: 6/14/2024 20:01:21
cpld/LCMXO2-1200HC/REFB.ipx
+8
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@@ -0,0 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 09 21 04:34:51.977" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
<Package>
<File name="REFB.lpc" type="lpc" modified="2023 09 21 04:34:49.038"/>
<File name="REFB.v" type="top_level_verilog" modified="2023 09 21 04:34:49.107"/>
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 09 21 04:34:49.108"/>
</Package>
</DiamondModule>
cpld/LCMXO2-1200HC/impl1/.build_status
+38
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<?xml version="1.0" encoding="UTF-8"?>
<BuildStatus>
<Strategy name="Strategy1">
<Milestone name="Export" build_result="0" build_time="0">
<Task name="IBIS" build_result="0" update_result="3" update_time="0"/>
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
<Task name="Bitgen" build_result="0" update_result="3" update_time="0"/>
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1718253547"/>
</Milestone>
<Milestone name="Map" build_result="2" build_time="1718253533">
<Task name="Map" build_result="2" update_result="0" update_time="1718253533"/>
<Task name="MapTrace" build_result="0" update_result="3" update_time="0"/>
<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="PAR" build_result="2" build_time="1718253543">
<Task name="PAR" build_result="2" update_result="0" update_time="1718253543"/>
<Task name="PARTrace" build_result="0" update_result="3" update_time="0"/>
<Task name="IOTiming" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="Synthesis" build_result="2" build_time="1718253532">
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1718253532"/>
</Milestone>
<Milestone name="TOOL_Report" build_result="0" build_time="0">
<Task name="HDLE" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="Translate" build_result="2" build_time="1718253532">
<Task name="Translate" build_result="2" update_result="0" update_time="1718253532"/>
</Milestone>
<Report name="GR8RAM_LCMXO2_1200HC_impl1.bgn" last_build_time="1718253547" last_build_size="4416"/>
<Report name="GR8RAM_LCMXO2_1200HC_impl1.edi" last_build_time="1718253531" last_build_size="215733"/>
<Report name="GR8RAM_LCMXO2_1200HC_impl1.jed" last_build_time="1718253547" last_build_size="352059"/>
<Report name="GR8RAM_LCMXO2_1200HC_impl1.ncd" last_build_time="1718253543" last_build_size="323416"/>
<Report name="GR8RAM_LCMXO2_1200HC_impl1.ngd" last_build_time="1718253532" last_build_size="232595"/>
<Report name="GR8RAM_LCMXO2_1200HC_impl1_map.ncd" last_build_time="1718253533" last_build_size="229621"/>
</Strategy>
</BuildStatus>
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.alt
+81
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@@ -0,0 +1,81 @@
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Thu Jun 13 00:39:07 2024 *
NOTE DESIGN NAME: GR8RAM *
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *
NOTE PINS RD[0] : 65 : inout *
NOTE PINS nFCS : 88 : out *
NOTE PINS RCLKout : 39 : out *
NOTE PINS RCLK : 38 : in *
NOTE PINS MOSI : 97 : inout *
NOTE PINS MISO : 98 : in *
NOTE PINS FCK : 96 : out *
NOTE PINS SD[7] : 31 : inout *
NOTE PINS SD[6] : 30 : inout *
NOTE PINS SD[5] : 29 : inout *
NOTE PINS SD[4] : 28 : inout *
NOTE PINS SD[3] : 27 : inout *
NOTE PINS SD[2] : 21 : inout *
NOTE PINS SD[1] : 24 : inout *
NOTE PINS SD[0] : 25 : inout *
NOTE PINS RCKE : 40 : out *
NOTE PINS DQMH : 34 : out *
NOTE PINS DQML : 32 : out *
NOTE PINS nSWE : 35 : out *
NOTE PINS nCAS : 36 : out *
NOTE PINS nRAS : 37 : out *
NOTE PINS nRCS : 41 : out *
NOTE PINS SA[12] : 42 : out *
NOTE PINS SA[11] : 45 : out *
NOTE PINS SA[10] : 47 : out *
NOTE PINS SA[9] : 49 : out *
NOTE PINS SA[8] : 53 : out *
NOTE PINS SA[7] : 57 : out *
NOTE PINS SA[6] : 62 : out *
NOTE PINS SA[5] : 52 : out *
NOTE PINS SA[4] : 51 : out *
NOTE PINS SA[3] : 60 : out *
NOTE PINS SA[2] : 58 : out *
NOTE PINS SA[1] : 59 : out *
NOTE PINS SA[0] : 54 : out *
NOTE PINS SBA[1] : 48 : out *
NOTE PINS SBA[0] : 43 : out *
NOTE PINS nIOSTRB : 18 : in *
NOTE PINS nDEVSEL : 16 : in *
NOTE PINS nIOSEL : 15 : in *
NOTE PINS nDinOE : 77 : out *
NOTE PINS nDoutOE : 1 : out *
NOTE PINS RD[7] : 75 : inout *
NOTE PINS RD[6] : 71 : inout *
NOTE PINS RD[5] : 70 : inout *
NOTE PINS RD[4] : 69 : inout *
NOTE PINS RD[3] : 68 : inout *
NOTE PINS RD[2] : 67 : inout *
NOTE PINS RD[1] : 66 : inout *
NOTE PINS nWE : 19 : in *
NOTE PINS RA[15] : 14 : in *
NOTE PINS RA[14] : 13 : in *
NOTE PINS RA[13] : 10 : in *
NOTE PINS RA[12] : 9 : in *
NOTE PINS RA[11] : 8 : in *
NOTE PINS RA[10] : 3 : in *
NOTE PINS RA[9] : 2 : in *
NOTE PINS RA[8] : 99 : in *
NOTE PINS RA[7] : 87 : in *
NOTE PINS RA[6] : 86 : in *
NOTE PINS RA[5] : 85 : in *
NOTE PINS RA[4] : 4 : in *
NOTE PINS RA[3] : 84 : in *
NOTE PINS RA[2] : 83 : in *
NOTE PINS RA[1] : 78 : in *
NOTE PINS RA[0] : 74 : in *
NOTE PINS LED : 81 : out *
NOTE PINS SetFW[1] : 63 : in *
NOTE PINS SetFW[0] : 64 : in *
NOTE PINS nIRQout : 12 : out *
NOTE PINS nRESout : 7 : out *
NOTE PINS nRES : 20 : in *
NOTE PINS PHI0 : 17 : in *
NOTE CONFIGURATION MODE: NONE *
NOTE COMPRESSION: on *
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.areasrr
+31
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----------------------------------------------------------------------
Report for cell GR8RAM.verilog
Register bits: 118 of 1280 (9%)
PIC Latch: 0
I/O cells: 73
Cell usage:
cell count Res Usage(%)
BB 17 100.0
CCU2D 13 100.0
FD1P3AX 24 100.0
FD1S3AX 17 100.0
FD1S3DX 27 100.0
GSR 1 100.0
IB 26 100.0
IFS1P3DX 18 100.0
INV 7 100.0
OB 28 100.0
OBZ 2 100.0
ODDRXE 1 100.0
OFS1P3BX 7 100.0
OFS1P3DX 12 100.0
OFS1P3IX 10 100.0
OFS1P3JX 3 100.0
ORCALUT4 240 100.0
PFUMX 7 100.0
PUR 1 100.0
VHI 1 100.0
VLO 1 100.0
TOTAL 463
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.bgn
+86
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@@ -0,0 +1,86 @@
BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Jun 13 00:39:03 2024
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml GR8RAM_LCMXO2_1200HC_impl1.ncd GR8RAM_LCMXO2_1200HC_impl1.prf
Loading design for application Bitgen from file GR8RAM_LCMXO2_1200HC_impl1.ncd.
Design name: GR8RAM
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from GR8RAM_LCMXO2_1200HC_impl1.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| RamCfg | Reset** |
+---------------------------------+---------------------------------+
| MCCLK_FREQ | 2.08** |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| JTAG_PORT | ENABLE** |
+---------------------------------+---------------------------------+
| SDM_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| SLAVE_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MASTER_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| I2C_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MUX_CONFIGURATION_PORTS | DISABLE** |
+---------------------------------+---------------------------------+
| CONFIGURATION | CFG** |
+---------------------------------+---------------------------------+
| COMPRESS_CONFIG | ON** |
+---------------------------------+---------------------------------+
| MY_ASSP | OFF** |
+---------------------------------+---------------------------------+
| ONE_TIME_PROGRAM | OFF** |
+---------------------------------+---------------------------------+
| ENABLE_TRANSFR | DISABLE** |
+---------------------------------+---------------------------------+
| SHAREDEBRINIT | DISABLE** |
+---------------------------------+---------------------------------+
| BACKGROUND_RECONFIG | OFF** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "GR8RAM_LCMXO2_1200HC_impl1.jed".
===========
UFM Summary.
===========
UFM Size: 511 Pages (128*511 Bits).
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
Initialized UFM Pages: 0 Page.
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Peak Memory Usage: 275 MB
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd
BIN
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Binary file not shown.
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.pad
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PAD Specification File
***************************
PART TYPE: LCMXO2-1200HC
Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.42
Thu Jun 13 00:38:57 2024
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| DQMH | 34/2 | LVCMOS33_OUT | PB9A | | | DRIVE:4mA SLEW:SLOW |
| DQML | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
| FCK | 96/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| LED | 81/0 | LVCMOS33_OUT | PT15D | | | DRIVE:24mA SLEW:SLOW |
| MISO | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
| MOSI | 97/0 | LVCMOS33_BIDI | PT10A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| PHI0 | 17/3 | LVCMOS33_IN | PL8B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[0] | 74/1 | LVCMOS33_IN | PR2B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[10] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[11] | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[12] | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[13] | 10/3 | LVCMOS33_IN | PL4B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[14] | 13/3 | LVCMOS33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[15] | 14/3 | LVCMOS33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[1] | 78/0 | LVCMOS33_IN | PT16C | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[2] | 83/0 | LVCMOS33_IN | PT15B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[3] | 84/0 | LVCMOS33_IN | PT15A | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[4] | 4/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[5] | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[6] | 86/0 | LVCMOS33_IN | PT12C | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[8] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[9] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
| RCKE | 40/2 | LVCMOS33_OUT | PB15A | | | DRIVE:4mA SLEW:SLOW |
| RCLK | 38/2 | LVCMOS33_IN | PB11A | | | CLAMP:ON HYSTERESIS:SMALL |
| RCLKout | 39/2 | LVCMOS33_OUT | PB11B | | | DRIVE:24mA SLEW:FAST |
| RD[0] | 65/1 | LVCMOS33_BIDI | PR5A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 66/1 | LVCMOS33_BIDI | PR4D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 67/1 | LVCMOS33_BIDI | PR4C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 68/1 | LVCMOS33_BIDI | PR4B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 69/1 | LVCMOS33_BIDI | PR4A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 70/1 | LVCMOS33_BIDI | PR3B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 71/1 | LVCMOS33_BIDI | PR3A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 75/1 | LVCMOS33_BIDI | PR2A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SA[0] | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
| SA[10] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
| SA[11] | 45/2 | LVCMOS33_OUT | PB18C | | | DRIVE:4mA SLEW:SLOW |
| SA[12] | 42/2 | LVCMOS33_OUT | PB18A | | | DRIVE:4mA SLEW:SLOW |
| SA[1] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
| SA[2] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
| SA[3] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
| SA[4] | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| SA[5] | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
| SA[6] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
| SA[7] | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
| SA[8] | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| SA[9] | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
| SBA[0] | 43/2 | LVCMOS33_OUT | PB18B | | | DRIVE:4mA SLEW:SLOW |
| SBA[1] | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
| SD[0] | 25/3 | LVCMOS33_BIDI | PL10D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[1] | 24/3 | LVCMOS33_BIDI | PL10C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[2] | 21/3 | LVCMOS33_BIDI | PL9B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[3] | 27/2 | LVCMOS33_BIDI | PB4C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[4] | 28/2 | LVCMOS33_BIDI | PB4D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[5] | 29/2 | LVCMOS33_BIDI | PB6A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[6] | 30/2 | LVCMOS33_BIDI | PB6B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[7] | 31/2 | LVCMOS33_BIDI | PB6C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SetFW[0] | 64/1 | LVCMOS33_IN | PR5B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
| SetFW[1] | 63/1 | LVCMOS33_IN | PR5C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
| nCAS | 36/2 | LVCMOS33_OUT | PB11C | | | DRIVE:4mA SLEW:SLOW |
| nDEVSEL | 16/3 | LVCMOS33_IN | PL8A | | | CLAMP:ON HYSTERESIS:SMALL |
| nDinOE | 77/0 | LVCMOS33_OUT | PT17C | | | DRIVE:4mA SLEW:SLOW |
| nDoutOE | 1/3 | LVCMOS33_OUT | PL2C | | | DRIVE:4mA SLEW:SLOW |
| nFCS | 88/0 | LVCMOS33_OUT | PT12A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| nIOSEL | 15/3 | LVCMOS33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL |
| nIOSTRB | 18/3 | LVCMOS33_IN | PL8C | | | CLAMP:ON HYSTERESIS:SMALL |
| nIRQout | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
| nRAS | 37/2 | LVCMOS33_OUT | PB11D | | | DRIVE:4mA SLEW:SLOW |
| nRCS | 41/2 | LVCMOS33_OUT | PB15B | | | DRIVE:4mA SLEW:SLOW |
| nRES | 20/3 | LVCMOS33_IN | PL9A | | | CLAMP:ON HYSTERESIS:SMALL |
| nRESout | 7/3 | LVCMOS33_OUT | PL3C | | | DRIVE:4mA SLEW:SLOW |
| nSWE | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW |
| nWE | 19/3 | LVCMOS33_IN | PL8D | | | CLAMP:ON HYSTERESIS:SMALL |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
| 2 | 3.3V |
| 3 | 3.3V |
+------+-------+
Vref by Bank:
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
Pinout by Pin Number:
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | nDoutOE | LOCATED | LVCMOS33_OUT | PL2C | L_GPLLT_IN | | |
| 2/3 | RA[9] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
| 3/3 | RA[10] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
| 4/3 | RA[4] | LOCATED | LVCMOS33_IN | PL3B | PCLKC3_2 | | |
| 7/3 | nRESout | LOCATED | LVCMOS33_OUT | PL3C | | | |
| 8/3 | RA[11] | LOCATED | LVCMOS33_IN | PL3D | | | |
| 9/3 | RA[12] | LOCATED | LVCMOS33_IN | PL4A | | | |
| 10/3 | RA[13] | LOCATED | LVCMOS33_IN | PL4B | | | |
| 12/3 | nIRQout | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
| 13/3 | RA[14] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
| 14/3 | RA[15] | LOCATED | LVCMOS33_IN | PL5C | | | |
| 15/3 | nIOSEL | LOCATED | LVCMOS33_IN | PL5D | | | |
| 16/3 | nDEVSEL | LOCATED | LVCMOS33_IN | PL8A | | | |
| 17/3 | PHI0 | LOCATED | LVCMOS33_IN | PL8B | | | |
| 18/3 | nIOSTRB | LOCATED | LVCMOS33_IN | PL8C | | | |
| 19/3 | nWE | LOCATED | LVCMOS33_IN | PL8D | | | |
| 20/3 | nRES | LOCATED | LVCMOS33_IN | PL9A | PCLKT3_0 | | |
| 21/3 | SD[2] | LOCATED | LVCMOS33_BIDI | PL9B | PCLKC3_0 | | |
| 24/3 | SD[1] | LOCATED | LVCMOS33_BIDI | PL10C | | | |
| 25/3 | SD[0] | LOCATED | LVCMOS33_BIDI | PL10D | | | |
| 27/2 | SD[3] | LOCATED | LVCMOS33_BIDI | PB4C | CSSPIN | | |
| 28/2 | SD[4] | LOCATED | LVCMOS33_BIDI | PB4D | | | |
| 29/2 | SD[5] | LOCATED | LVCMOS33_BIDI | PB6A | | | |
| 30/2 | SD[6] | LOCATED | LVCMOS33_BIDI | PB6B | | | |
| 31/2 | SD[7] | LOCATED | LVCMOS33_BIDI | PB6C | MCLK/CCLK | | |
| 32/2 | DQML | LOCATED | LVCMOS33_OUT | PB6D | SO/SPISO | | |
| 34/2 | DQMH | LOCATED | LVCMOS33_OUT | PB9A | PCLKT2_0 | | |
| 35/2 | nSWE | LOCATED | LVCMOS33_OUT | PB9B | PCLKC2_0 | | |
| 36/2 | nCAS | LOCATED | LVCMOS33_OUT | PB11C | | | |
| 37/2 | nRAS | LOCATED | LVCMOS33_OUT | PB11D | | | |
| 38/2 | RCLK | LOCATED | LVCMOS33_IN | PB11A | PCLKT2_1 | | |
| 39/2 | RCLKout | LOCATED | LVCMOS33_OUT | PB11B | PCLKC2_1 | | |
| 40/2 | RCKE | LOCATED | LVCMOS33_OUT | PB15A | | | |
| 41/2 | nRCS | LOCATED | LVCMOS33_OUT | PB15B | | | |
| 42/2 | SA[12] | LOCATED | LVCMOS33_OUT | PB18A | | | |
| 43/2 | SBA[0] | LOCATED | LVCMOS33_OUT | PB18B | | | |
| 45/2 | SA[11] | LOCATED | LVCMOS33_OUT | PB18C | | | |
| 47/2 | SA[10] | LOCATED | LVCMOS33_OUT | PB18D | | | |
| 48/2 | SBA[1] | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
| 49/2 | SA[9] | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
| 51/1 | SA[4] | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
| 52/1 | SA[5] | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
| 53/1 | SA[8] | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
| 54/1 | SA[0] | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
| 57/1 | SA[7] | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
| 58/1 | SA[2] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
| 59/1 | SA[1] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 60/1 | SA[3] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
| 62/1 | SA[6] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
| 63/1 | SetFW[1] | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | SetFW[0] | LOCATED | LVCMOS33_IN | PR5B | DQS0N | | |
| 65/1 | RD[0] | LOCATED | LVCMOS33_BIDI | PR5A | DQS0 | | |
| 66/1 | RD[1] | LOCATED | LVCMOS33_BIDI | PR4D | DQ0 | | |
| 67/1 | RD[2] | LOCATED | LVCMOS33_BIDI | PR4C | DQ0 | | |
| 68/1 | RD[3] | LOCATED | LVCMOS33_BIDI | PR4B | DQ0 | | |
| 69/1 | RD[4] | LOCATED | LVCMOS33_BIDI | PR4A | DQ0 | | |
| 70/1 | RD[5] | LOCATED | LVCMOS33_BIDI | PR3B | DQ0 | | |
| 71/1 | RD[6] | LOCATED | LVCMOS33_BIDI | PR3A | DQ0 | | |
| 74/1 | RA[0] | LOCATED | LVCMOS33_IN | PR2B | DQ0 | | |
| 75/1 | RD[7] | LOCATED | LVCMOS33_BIDI | PR2A | DQ0 | | |
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
| 77/0 | nDinOE | LOCATED | LVCMOS33_OUT | PT17C | INITN | | |
| 78/0 | RA[1] | LOCATED | LVCMOS33_IN | PT16C | | | |
| 81/0 | LED | LOCATED | LVCMOS33_OUT | PT15D | PROGRAMN | | |
| 82/0 | unused, PULL:DOWN | | | PT15C | JTAGENB | | |
| 83/0 | RA[2] | LOCATED | LVCMOS33_IN | PT15B | | | |
| 84/0 | RA[3] | LOCATED | LVCMOS33_IN | PT15A | | | |
| 85/0 | RA[5] | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | |
| 86/0 | RA[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | |
| 87/0 | RA[7] | LOCATED | LVCMOS33_IN | PT12B | PCLKC0_1 | | |
| 88/0 | nFCS | LOCATED | LVCMOS33_OUT | PT12A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
| 96/0 | FCK | LOCATED | LVCMOS33_OUT | PT10B | | | |
| 97/0 | MOSI | LOCATED | LVCMOS33_BIDI | PT10A | | | |
| 98/0 | MISO | LOCATED | LVCMOS33_IN | PT9B | | | |
| 99/0 | RA[8] | LOCATED | LVCMOS33_IN | PT9A | | | |
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "DQMH" SITE "34";
LOCATE COMP "DQML" SITE "32";
LOCATE COMP "FCK" SITE "96";
LOCATE COMP "LED" SITE "81";
LOCATE COMP "MISO" SITE "98";
LOCATE COMP "MOSI" SITE "97";
LOCATE COMP "PHI0" SITE "17";
LOCATE COMP "RA[0]" SITE "74";
LOCATE COMP "RA[10]" SITE "3";
LOCATE COMP "RA[11]" SITE "8";
LOCATE COMP "RA[12]" SITE "9";
LOCATE COMP "RA[13]" SITE "10";
LOCATE COMP "RA[14]" SITE "13";
LOCATE COMP "RA[15]" SITE "14";
LOCATE COMP "RA[1]" SITE "78";
LOCATE COMP "RA[2]" SITE "83";
LOCATE COMP "RA[3]" SITE "84";
LOCATE COMP "RA[4]" SITE "4";
LOCATE COMP "RA[5]" SITE "85";
LOCATE COMP "RA[6]" SITE "86";
LOCATE COMP "RA[7]" SITE "87";
LOCATE COMP "RA[8]" SITE "99";
LOCATE COMP "RA[9]" SITE "2";
LOCATE COMP "RCKE" SITE "40";
LOCATE COMP "RCLK" SITE "38";
LOCATE COMP "RCLKout" SITE "39";
LOCATE COMP "RD[0]" SITE "65";
LOCATE COMP "RD[1]" SITE "66";
LOCATE COMP "RD[2]" SITE "67";
LOCATE COMP "RD[3]" SITE "68";
LOCATE COMP "RD[4]" SITE "69";
LOCATE COMP "RD[5]" SITE "70";
LOCATE COMP "RD[6]" SITE "71";
LOCATE COMP "RD[7]" SITE "75";
LOCATE COMP "SA[0]" SITE "54";
LOCATE COMP "SA[10]" SITE "47";
LOCATE COMP "SA[11]" SITE "45";
LOCATE COMP "SA[12]" SITE "42";
LOCATE COMP "SA[1]" SITE "59";
LOCATE COMP "SA[2]" SITE "58";
LOCATE COMP "SA[3]" SITE "60";
LOCATE COMP "SA[4]" SITE "51";
LOCATE COMP "SA[5]" SITE "52";
LOCATE COMP "SA[6]" SITE "62";
LOCATE COMP "SA[7]" SITE "57";
LOCATE COMP "SA[8]" SITE "53";
LOCATE COMP "SA[9]" SITE "49";
LOCATE COMP "SBA[0]" SITE "43";
LOCATE COMP "SBA[1]" SITE "48";
LOCATE COMP "SD[0]" SITE "25";
LOCATE COMP "SD[1]" SITE "24";
LOCATE COMP "SD[2]" SITE "21";
LOCATE COMP "SD[3]" SITE "27";
LOCATE COMP "SD[4]" SITE "28";
LOCATE COMP "SD[5]" SITE "29";
LOCATE COMP "SD[6]" SITE "30";
LOCATE COMP "SD[7]" SITE "31";
LOCATE COMP "SetFW[0]" SITE "64";
LOCATE COMP "SetFW[1]" SITE "63";
LOCATE COMP "nCAS" SITE "36";
LOCATE COMP "nDEVSEL" SITE "16";
LOCATE COMP "nDinOE" SITE "77";
LOCATE COMP "nDoutOE" SITE "1";
LOCATE COMP "nFCS" SITE "88";
LOCATE COMP "nIOSEL" SITE "15";
LOCATE COMP "nIOSTRB" SITE "18";
LOCATE COMP "nIRQout" SITE "12";
LOCATE COMP "nRAS" SITE "37";
LOCATE COMP "nRCS" SITE "41";
LOCATE COMP "nRES" SITE "20";
LOCATE COMP "nRESout" SITE "7";
LOCATE COMP "nSWE" SITE "35";
LOCATE COMP "nWE" SITE "19";
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Jun 13 00:39:01 2024
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.par
+205
View File
@@ -0,0 +1,205 @@
Lattice Place and Route Report for Design "GR8RAM_LCMXO2_1200HC_impl1_map.ncd"
Thu Jun 13 00:38:53 2024
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd GR8RAM_LCMXO2_1200HC_impl1.prf
Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file GR8RAM_LCMXO2_1200HC_impl1_map.ncd.
Design name: GR8RAM
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 73+4(JTAG)/108 71% used
73+4(JTAG)/80 96% bonded
IOLOGIC 51/108 47% used
SLICE 136/640 21% used
GSR 1/1 100% used
Number of Signals: 430
Number of Connections: 1211
Pin Constraint Summary:
73 out of 73 pins locked (100% locked).
The following 2 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 80)
PHI0_c (driver: PHI0, clk load #: 14)
WARNING - par: Signal "PHI0_c" is selected to use Primary clock resources. However, its driver comp "PHI0" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 1 signal is selected to use the secondary clock routing resources:
FCKout120 (driver: SLICE_54, clk load #: 0, sr load #: 13, ce load #: 0)
Signal nRESr is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
....................
Placer score = 87858.
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
.
Placer score = 86903
Finished Placer Phase 2. REAL time: 4 secs
------------------ Clock Report ------------------
Global Clock Resources:
CLK_PIN : 1 out of 8 (12%)
General PIO: 1 out of 108 (0%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "38 (PB11A)", clk load = 80
PRIMARY "PHI0_c" from comp "PHI0" on PIO site "17 (PL8B)", clk load = 14
SECONDARY "FCKout120" from F0 on comp "SLICE_54" on site "R7C12B", clk load = 0, ce load = 0, sr load = 13
PRIMARY : 2 out of 8 (25%)
SECONDARY: 1 out of 8 (12%)
Edge Clocks:
No edge clock selected.
--------------- End of Clock Report ---------------
I/O Usage Summary (final):
73 + 4(JTAG) out of 108 (71.3%) PIO sites used.
73 + 4(JTAG) out of 80 (96.3%) bonded PIO sites used.
Number of PIO comps: 73; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 13 / 19 ( 68%) | 3.3V | - |
| 1 | 20 / 21 ( 95%) | 3.3V | - |
| 2 | 20 / 20 (100%) | 3.3V | - |
| 3 | 20 / 20 (100%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 3 secs
Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
-----------------------------------------------------------------
INFO - par: ASE feature is off due to non timing-driven settings.
-----------------------------------------------------------------
0 connections routed; 1211 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 9 secs
Start NBR router at 00:39:02 06/13/24
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 00:39:02 06/13/24
Start NBR section for initial routing at 00:39:02 06/13/24
Level 4, iteration 1
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 00:39:02 06/13/24
Level 4, iteration 1
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Start NBR section for re-routing at 00:39:02 06/13/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Start NBR section for post-routing at 00:39:02 06/13/24
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : <n/a>
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 8 secs
Total REAL time: 9 secs
Completely routed.
End of route. 1211 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a>
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a>
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 9 secs
Total REAL time to completion: 10 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.dir/5_1_par.asd
+38
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@@ -0,0 +1,38 @@
[ActiveSupport PAR]
; Global primary clocks
GLOBAL_PRIMARY_USED = 2;
; Global primary clock #0
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
GLOBAL_PRIMARY_0_LOADNUM = 80;
; Global primary clock #1
GLOBAL_PRIMARY_1_SIGNALNAME = PHI0_c;
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_1_LOADNUM = 14;
; # of global secondary clocks
GLOBAL_SECONDARY_USED = 1;
; Global secondary clock #0
GLOBAL_SECONDARY_0_SIGNALNAME = FCKout120;
GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_0_LOADNUM = 18;
GLOBAL_SECONDARY_0_SIGTYPE = RST;
; I/O Bank 0 Usage
BANK_0_USED = 13;
BANK_0_AVAIL = 19;
BANK_0_VCCIO = 3.3V;
BANK_0_VREF1 = NA;
; I/O Bank 1 Usage
BANK_1_USED = 20;
BANK_1_AVAIL = 21;
BANK_1_VCCIO = 3.3V;
BANK_1_VREF1 = NA;
; I/O Bank 2 Usage
BANK_2_USED = 20;
BANK_2_AVAIL = 20;
BANK_2_VCCIO = 3.3V;
BANK_2_VREF1 = NA;
; I/O Bank 3 Usage
BANK_3_USED = 20;
BANK_3_AVAIL = 20;
BANK_3_VCCIO = 3.3V;
BANK_3_VREF1 = NA;
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.dir/GR8RAM_LCMXO2_1200HC_impl1.par
+28
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@@ -0,0 +1,28 @@
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Jun 13 00:38:53 2024
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f GR8RAM_LCMXO2_1200HC_impl1.p2t
GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir
GR8RAM_LCMXO2_1200HC_impl1.prf -gui -msgset
//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml
Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 - - - - 10 Completed
* : Design saved.
Total (real) run time for 1-seed: 10 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.drc
+1
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DRC detected 0 errors and 0 warnings.
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.edi
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cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.fse
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cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.htm
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<html>
<head>
<title>syntmp/GR8RAM_LCMXO2_1200HC_impl1_srr.htm log file</title>
</head>
<frameset cols="20%, 80%">
<frame src="syntmp/GR8RAM_LCMXO2_1200HC_impl1_toc.htm" name="tocFrame" />
<frame src="syntmp/GR8RAM_LCMXO2_1200HC_impl1_srr.htm" name="srrFrame"/>
</frameset>
</html>
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.jed
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cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.log
+4
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@@ -0,0 +1,4 @@
---- MParTrce Tool Log File ----
==== Par Standard Out ====
==== End of Par Standard Out ====
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.mrp
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Lattice Mapping Report File for Design Module 'GR8RAM'
Design Information
------------------
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
GR8RAM_LCMXO2_1200HC_impl1.ngd -o GR8RAM_LCMXO2_1200HC_impl1_map.ncd -pr
GR8RAM_LCMXO2_1200HC_impl1.prf -mp GR8RAM_LCMXO2_1200HC_impl1.mrp -lpf //Ma
c/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_s
ynplify.lpf -lpf //Mac/iCloud/Repos/GR8RAM/cpld/GR8RAM-LCMXO2.lpf -c 0 -gui
-msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
Mapped on: 06/13/24 00:38:52
Design Summary
--------------
Number of registers: 118 out of 1520 (8%)
PFU registers: 68 out of 1280 (5%)
PIO registers: 50 out of 240 (21%)
Number of SLICEs: 136 out of 640 (21%)
SLICEs as Logic/ROM: 136 out of 640 (21%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 13 out of 640 (2%)
Number of LUT4s: 268 out of 1280 (21%)
Number used as logic LUTs: 242
Number used as distributed RAM: 0
Number used as ripple logic: 26
Number used as shift registers: 0
Number of PIO sites used: 73 + 4(JTAG) out of 80 (96%)
Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
Number of IDDR cells: 0
Number of ODDR cells: 1
Number of TDDR cells: 0
Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
Number of PIO using IDDR only: 0 (0 differential)
Number of PIO using ODDR only: 1 (0 differential)
Number of PIO using TDDR only: 0 (0 differential)
Number of PIO using IDDR/ODDR: 0 (0 differential)
Number of PIO using IDDR/TDDR: 0 (0 differential)
Number of PIO using ODDR/TDDR: 0 (0 differential)
Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 1 out of 1 (100%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Page 1
Design: GR8RAM Date: 06/13/24 00:38:52
Design Summary (cont)
---------------------
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 2
Net RCLK_c: 80 loads, 72 rising, 8 falling (Driver: PIO RCLK )
Net PHI0_c: 14 loads, 14 rising, 0 falling (Driver: PIO PHI0 )
Number of Clock Enables: 6
Net un1_nRESout4_1_i_0: 2 loads, 2 LSLICEs
Net PS[0]: 5 loads, 3 LSLICEs
Net SetFWr3: 2 loads, 0 LSLICEs
Net N_254_i: 8 loads, 8 LSLICEs
Net Bank5: 1 loads, 0 LSLICEs
Net RDD37: 8 loads, 1 LSLICEs
Number of local set/reset loads for net nRESr merged into GSR: 28
Number of LSRs: 1
Net FCKout120: 13 loads, 0 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net PS[0]: 33 loads
Net SBA14: 31 loads
Net N_248: 29 loads
Net PS[3]: 28 loads
Net PS[2]: 24 loads
Net PS[1]: 23 loads
Net RAr[1]: 20 loads
Net RAMSpecSEL: 19 loads
Net FCKout120: 18 loads
Net un1_PS_6: 14 loads
Number of warnings: 1
Number of errors: 0
Design Errors/Warnings
----------------------
WARNING - map: Using local reset signal 'nRESr' to infer global GSR net.
IO (PIO) Attributes
-------------------
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
Page 2
Design: GR8RAM Date: 06/13/24 00:38:52
IO (PIO) Attributes (cont)
--------------------------
| nFCS | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RCLKout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RCLK | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MOSI | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MISO | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| FCK | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SD[7] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SD[6] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SD[5] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SD[4] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SD[3] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SD[2] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SD[1] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SD[0] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RCKE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQMH | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQML | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nSWE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRCS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[12] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[9] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[8] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[7] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[6] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
Page 3
Design: GR8RAM Date: 06/13/24 00:38:52
IO (PIO) Attributes (cont)
--------------------------
| SA[5] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[4] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[3] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[2] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SBA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SBA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nIOSTRB | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDEVSEL | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nIOSEL | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDinOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDoutOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[5] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[4] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nWE | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[15] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[14] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[13] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[12] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[11] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[10] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[9] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
Page 4
Design: GR8RAM Date: 06/13/24 00:38:52
IO (PIO) Attributes (cont)
--------------------------
| RA[8] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[7] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[6] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[5] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[4] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[3] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[2] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[1] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[0] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SetFW[1] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| SetFW[0] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| nIRQout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nRESout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nRES | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| PHI0 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
Removed logic
-------------
Signal SDOE_i was merged into signal SDOE
Signal MOSIOE_i was merged into signal MOSIOE
Signal FCKOE_i was merged into signal FCKOE
Signal nRESr_i was merged into signal nRESr
Signal PS_i[0] was merged into signal PS[0]
Signal RDD_0_.CN was merged into signal RCLK_c
Signal LS_s_0_S1[13] undriven or does not drive anything - clipped.
Signal LS_s_0_COUT[13] undriven or does not drive anything - clipped.
Signal un1_Addr_1_cry_0_0_S0 undriven or does not drive anything - clipped.
Signal N_2 undriven or does not drive anything - clipped.
Signal un1_Addr_1_s_7_0_S1 undriven or does not drive anything - clipped.
Signal un1_Addr_1_s_7_0_COUT undriven or does not drive anything - clipped.
Signal LS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block SDOE_RNIBPBD was optimized away.
Block MOSI_pad_RNO was optimized away.
Block FCKOE_RNI8HE1 was optimized away.
Block nRESr_RNIAPB9 was optimized away.
Block PS_RNIBBDD[0] was optimized away.
Block RDD_0_.CN was optimized away.
Page 5
Design: GR8RAM Date: 06/13/24 00:38:52
Removed logic (cont)
--------------------
GSR Usage
---------
GSR Component:
The local reset signal 'nRESr' of the design has been inferred as Global Set
Reset (GSR). The reset signal used for GSR control is 'nRESr'.
GSR Property:
The design components with GSR property set to ENABLED will respond to global
set reset while the components with GSR property set to DISABLED will
not.
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 64 MB
Page 6
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved.
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.ncd
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cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.ngd
BIN
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cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.ngo
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cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.p2t
+9
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@@ -0,0 +1,9 @@
-w
-l 5
-i 6
-n 1
-t 1
-s 1
-c 0
-e 0
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.p3t
+5
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@@ -0,0 +1,5 @@
-rem
-distrce
-log "GR8RAM_LCMXO2_1200HC_impl1.log"
-o "GR8RAM_LCMXO2_1200HC_impl1.csv"
-pr "GR8RAM_LCMXO2_1200HC_impl1.prf"
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.pad
+321
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@@ -0,0 +1,321 @@
PAD Specification File
***************************
PART TYPE: LCMXO2-1200HC
Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.42
Thu Jun 13 00:38:57 2024
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| DQMH | 34/2 | LVCMOS33_OUT | PB9A | | | DRIVE:4mA SLEW:SLOW |
| DQML | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
| FCK | 96/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| LED | 81/0 | LVCMOS33_OUT | PT15D | | | DRIVE:24mA SLEW:SLOW |
| MISO | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
| MOSI | 97/0 | LVCMOS33_BIDI | PT10A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| PHI0 | 17/3 | LVCMOS33_IN | PL8B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[0] | 74/1 | LVCMOS33_IN | PR2B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[10] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[11] | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[12] | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[13] | 10/3 | LVCMOS33_IN | PL4B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[14] | 13/3 | LVCMOS33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[15] | 14/3 | LVCMOS33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[1] | 78/0 | LVCMOS33_IN | PT16C | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[2] | 83/0 | LVCMOS33_IN | PT15B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[3] | 84/0 | LVCMOS33_IN | PT15A | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[4] | 4/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[5] | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[6] | 86/0 | LVCMOS33_IN | PT12C | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[8] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[9] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
| RCKE | 40/2 | LVCMOS33_OUT | PB15A | | | DRIVE:4mA SLEW:SLOW |
| RCLK | 38/2 | LVCMOS33_IN | PB11A | | | CLAMP:ON HYSTERESIS:SMALL |
| RCLKout | 39/2 | LVCMOS33_OUT | PB11B | | | DRIVE:24mA SLEW:FAST |
| RD[0] | 65/1 | LVCMOS33_BIDI | PR5A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 66/1 | LVCMOS33_BIDI | PR4D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 67/1 | LVCMOS33_BIDI | PR4C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 68/1 | LVCMOS33_BIDI | PR4B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 69/1 | LVCMOS33_BIDI | PR4A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 70/1 | LVCMOS33_BIDI | PR3B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 71/1 | LVCMOS33_BIDI | PR3A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 75/1 | LVCMOS33_BIDI | PR2A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SA[0] | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
| SA[10] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
| SA[11] | 45/2 | LVCMOS33_OUT | PB18C | | | DRIVE:4mA SLEW:SLOW |
| SA[12] | 42/2 | LVCMOS33_OUT | PB18A | | | DRIVE:4mA SLEW:SLOW |
| SA[1] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
| SA[2] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
| SA[3] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
| SA[4] | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| SA[5] | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
| SA[6] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
| SA[7] | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
| SA[8] | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| SA[9] | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
| SBA[0] | 43/2 | LVCMOS33_OUT | PB18B | | | DRIVE:4mA SLEW:SLOW |
| SBA[1] | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
| SD[0] | 25/3 | LVCMOS33_BIDI | PL10D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[1] | 24/3 | LVCMOS33_BIDI | PL10C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[2] | 21/3 | LVCMOS33_BIDI | PL9B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[3] | 27/2 | LVCMOS33_BIDI | PB4C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[4] | 28/2 | LVCMOS33_BIDI | PB4D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[5] | 29/2 | LVCMOS33_BIDI | PB6A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[6] | 30/2 | LVCMOS33_BIDI | PB6B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[7] | 31/2 | LVCMOS33_BIDI | PB6C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SetFW[0] | 64/1 | LVCMOS33_IN | PR5B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
| SetFW[1] | 63/1 | LVCMOS33_IN | PR5C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
| nCAS | 36/2 | LVCMOS33_OUT | PB11C | | | DRIVE:4mA SLEW:SLOW |
| nDEVSEL | 16/3 | LVCMOS33_IN | PL8A | | | CLAMP:ON HYSTERESIS:SMALL |
| nDinOE | 77/0 | LVCMOS33_OUT | PT17C | | | DRIVE:4mA SLEW:SLOW |
| nDoutOE | 1/3 | LVCMOS33_OUT | PL2C | | | DRIVE:4mA SLEW:SLOW |
| nFCS | 88/0 | LVCMOS33_OUT | PT12A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| nIOSEL | 15/3 | LVCMOS33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL |
| nIOSTRB | 18/3 | LVCMOS33_IN | PL8C | | | CLAMP:ON HYSTERESIS:SMALL |
| nIRQout | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
| nRAS | 37/2 | LVCMOS33_OUT | PB11D | | | DRIVE:4mA SLEW:SLOW |
| nRCS | 41/2 | LVCMOS33_OUT | PB15B | | | DRIVE:4mA SLEW:SLOW |
| nRES | 20/3 | LVCMOS33_IN | PL9A | | | CLAMP:ON HYSTERESIS:SMALL |
| nRESout | 7/3 | LVCMOS33_OUT | PL3C | | | DRIVE:4mA SLEW:SLOW |
| nSWE | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW |
| nWE | 19/3 | LVCMOS33_IN | PL8D | | | CLAMP:ON HYSTERESIS:SMALL |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
| 2 | 3.3V |
| 3 | 3.3V |
+------+-------+
Vref by Bank:
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
Pinout by Pin Number:
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | nDoutOE | LOCATED | LVCMOS33_OUT | PL2C | L_GPLLT_IN | | |
| 2/3 | RA[9] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
| 3/3 | RA[10] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
| 4/3 | RA[4] | LOCATED | LVCMOS33_IN | PL3B | PCLKC3_2 | | |
| 7/3 | nRESout | LOCATED | LVCMOS33_OUT | PL3C | | | |
| 8/3 | RA[11] | LOCATED | LVCMOS33_IN | PL3D | | | |
| 9/3 | RA[12] | LOCATED | LVCMOS33_IN | PL4A | | | |
| 10/3 | RA[13] | LOCATED | LVCMOS33_IN | PL4B | | | |
| 12/3 | nIRQout | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
| 13/3 | RA[14] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
| 14/3 | RA[15] | LOCATED | LVCMOS33_IN | PL5C | | | |
| 15/3 | nIOSEL | LOCATED | LVCMOS33_IN | PL5D | | | |
| 16/3 | nDEVSEL | LOCATED | LVCMOS33_IN | PL8A | | | |
| 17/3 | PHI0 | LOCATED | LVCMOS33_IN | PL8B | | | |
| 18/3 | nIOSTRB | LOCATED | LVCMOS33_IN | PL8C | | | |
| 19/3 | nWE | LOCATED | LVCMOS33_IN | PL8D | | | |
| 20/3 | nRES | LOCATED | LVCMOS33_IN | PL9A | PCLKT3_0 | | |
| 21/3 | SD[2] | LOCATED | LVCMOS33_BIDI | PL9B | PCLKC3_0 | | |
| 24/3 | SD[1] | LOCATED | LVCMOS33_BIDI | PL10C | | | |
| 25/3 | SD[0] | LOCATED | LVCMOS33_BIDI | PL10D | | | |
| 27/2 | SD[3] | LOCATED | LVCMOS33_BIDI | PB4C | CSSPIN | | |
| 28/2 | SD[4] | LOCATED | LVCMOS33_BIDI | PB4D | | | |
| 29/2 | SD[5] | LOCATED | LVCMOS33_BIDI | PB6A | | | |
| 30/2 | SD[6] | LOCATED | LVCMOS33_BIDI | PB6B | | | |
| 31/2 | SD[7] | LOCATED | LVCMOS33_BIDI | PB6C | MCLK/CCLK | | |
| 32/2 | DQML | LOCATED | LVCMOS33_OUT | PB6D | SO/SPISO | | |
| 34/2 | DQMH | LOCATED | LVCMOS33_OUT | PB9A | PCLKT2_0 | | |
| 35/2 | nSWE | LOCATED | LVCMOS33_OUT | PB9B | PCLKC2_0 | | |
| 36/2 | nCAS | LOCATED | LVCMOS33_OUT | PB11C | | | |
| 37/2 | nRAS | LOCATED | LVCMOS33_OUT | PB11D | | | |
| 38/2 | RCLK | LOCATED | LVCMOS33_IN | PB11A | PCLKT2_1 | | |
| 39/2 | RCLKout | LOCATED | LVCMOS33_OUT | PB11B | PCLKC2_1 | | |
| 40/2 | RCKE | LOCATED | LVCMOS33_OUT | PB15A | | | |
| 41/2 | nRCS | LOCATED | LVCMOS33_OUT | PB15B | | | |
| 42/2 | SA[12] | LOCATED | LVCMOS33_OUT | PB18A | | | |
| 43/2 | SBA[0] | LOCATED | LVCMOS33_OUT | PB18B | | | |
| 45/2 | SA[11] | LOCATED | LVCMOS33_OUT | PB18C | | | |
| 47/2 | SA[10] | LOCATED | LVCMOS33_OUT | PB18D | | | |
| 48/2 | SBA[1] | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
| 49/2 | SA[9] | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
| 51/1 | SA[4] | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
| 52/1 | SA[5] | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
| 53/1 | SA[8] | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
| 54/1 | SA[0] | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
| 57/1 | SA[7] | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
| 58/1 | SA[2] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
| 59/1 | SA[1] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 60/1 | SA[3] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
| 62/1 | SA[6] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
| 63/1 | SetFW[1] | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | SetFW[0] | LOCATED | LVCMOS33_IN | PR5B | DQS0N | | |
| 65/1 | RD[0] | LOCATED | LVCMOS33_BIDI | PR5A | DQS0 | | |
| 66/1 | RD[1] | LOCATED | LVCMOS33_BIDI | PR4D | DQ0 | | |
| 67/1 | RD[2] | LOCATED | LVCMOS33_BIDI | PR4C | DQ0 | | |
| 68/1 | RD[3] | LOCATED | LVCMOS33_BIDI | PR4B | DQ0 | | |
| 69/1 | RD[4] | LOCATED | LVCMOS33_BIDI | PR4A | DQ0 | | |
| 70/1 | RD[5] | LOCATED | LVCMOS33_BIDI | PR3B | DQ0 | | |
| 71/1 | RD[6] | LOCATED | LVCMOS33_BIDI | PR3A | DQ0 | | |
| 74/1 | RA[0] | LOCATED | LVCMOS33_IN | PR2B | DQ0 | | |
| 75/1 | RD[7] | LOCATED | LVCMOS33_BIDI | PR2A | DQ0 | | |
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
| 77/0 | nDinOE | LOCATED | LVCMOS33_OUT | PT17C | INITN | | |
| 78/0 | RA[1] | LOCATED | LVCMOS33_IN | PT16C | | | |
| 81/0 | LED | LOCATED | LVCMOS33_OUT | PT15D | PROGRAMN | | |
| 82/0 | unused, PULL:DOWN | | | PT15C | JTAGENB | | |
| 83/0 | RA[2] | LOCATED | LVCMOS33_IN | PT15B | | | |
| 84/0 | RA[3] | LOCATED | LVCMOS33_IN | PT15A | | | |
| 85/0 | RA[5] | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | |
| 86/0 | RA[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | |
| 87/0 | RA[7] | LOCATED | LVCMOS33_IN | PT12B | PCLKC0_1 | | |
| 88/0 | nFCS | LOCATED | LVCMOS33_OUT | PT12A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
| 96/0 | FCK | LOCATED | LVCMOS33_OUT | PT10B | | | |
| 97/0 | MOSI | LOCATED | LVCMOS33_BIDI | PT10A | | | |
| 98/0 | MISO | LOCATED | LVCMOS33_IN | PT9B | | | |
| 99/0 | RA[8] | LOCATED | LVCMOS33_IN | PT9A | | | |
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "DQMH" SITE "34";
LOCATE COMP "DQML" SITE "32";
LOCATE COMP "FCK" SITE "96";
LOCATE COMP "LED" SITE "81";
LOCATE COMP "MISO" SITE "98";
LOCATE COMP "MOSI" SITE "97";
LOCATE COMP "PHI0" SITE "17";
LOCATE COMP "RA[0]" SITE "74";
LOCATE COMP "RA[10]" SITE "3";
LOCATE COMP "RA[11]" SITE "8";
LOCATE COMP "RA[12]" SITE "9";
LOCATE COMP "RA[13]" SITE "10";
LOCATE COMP "RA[14]" SITE "13";
LOCATE COMP "RA[15]" SITE "14";
LOCATE COMP "RA[1]" SITE "78";
LOCATE COMP "RA[2]" SITE "83";
LOCATE COMP "RA[3]" SITE "84";
LOCATE COMP "RA[4]" SITE "4";
LOCATE COMP "RA[5]" SITE "85";
LOCATE COMP "RA[6]" SITE "86";
LOCATE COMP "RA[7]" SITE "87";
LOCATE COMP "RA[8]" SITE "99";
LOCATE COMP "RA[9]" SITE "2";
LOCATE COMP "RCKE" SITE "40";
LOCATE COMP "RCLK" SITE "38";
LOCATE COMP "RCLKout" SITE "39";
LOCATE COMP "RD[0]" SITE "65";
LOCATE COMP "RD[1]" SITE "66";
LOCATE COMP "RD[2]" SITE "67";
LOCATE COMP "RD[3]" SITE "68";
LOCATE COMP "RD[4]" SITE "69";
LOCATE COMP "RD[5]" SITE "70";
LOCATE COMP "RD[6]" SITE "71";
LOCATE COMP "RD[7]" SITE "75";
LOCATE COMP "SA[0]" SITE "54";
LOCATE COMP "SA[10]" SITE "47";
LOCATE COMP "SA[11]" SITE "45";
LOCATE COMP "SA[12]" SITE "42";
LOCATE COMP "SA[1]" SITE "59";
LOCATE COMP "SA[2]" SITE "58";
LOCATE COMP "SA[3]" SITE "60";
LOCATE COMP "SA[4]" SITE "51";
LOCATE COMP "SA[5]" SITE "52";
LOCATE COMP "SA[6]" SITE "62";
LOCATE COMP "SA[7]" SITE "57";
LOCATE COMP "SA[8]" SITE "53";
LOCATE COMP "SA[9]" SITE "49";
LOCATE COMP "SBA[0]" SITE "43";
LOCATE COMP "SBA[1]" SITE "48";
LOCATE COMP "SD[0]" SITE "25";
LOCATE COMP "SD[1]" SITE "24";
LOCATE COMP "SD[2]" SITE "21";
LOCATE COMP "SD[3]" SITE "27";
LOCATE COMP "SD[4]" SITE "28";
LOCATE COMP "SD[5]" SITE "29";
LOCATE COMP "SD[6]" SITE "30";
LOCATE COMP "SD[7]" SITE "31";
LOCATE COMP "SetFW[0]" SITE "64";
LOCATE COMP "SetFW[1]" SITE "63";
LOCATE COMP "nCAS" SITE "36";
LOCATE COMP "nDEVSEL" SITE "16";
LOCATE COMP "nDinOE" SITE "77";
LOCATE COMP "nDoutOE" SITE "1";
LOCATE COMP "nFCS" SITE "88";
LOCATE COMP "nIOSEL" SITE "15";
LOCATE COMP "nIOSTRB" SITE "18";
LOCATE COMP "nIRQout" SITE "12";
LOCATE COMP "nRAS" SITE "37";
LOCATE COMP "nRCS" SITE "41";
LOCATE COMP "nRES" SITE "20";
LOCATE COMP "nRESout" SITE "7";
LOCATE COMP "nSWE" SITE "35";
LOCATE COMP "nWE" SITE "19";
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Jun 13 00:39:01 2024
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.par
+233
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PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Jun 13 00:38:53 2024
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f GR8RAM_LCMXO2_1200HC_impl1.p2t
GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir
GR8RAM_LCMXO2_1200HC_impl1.prf -gui -msgset
//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml
Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 - - - - 10 Completed
* : Design saved.
Total (real) run time for 1-seed: 10 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Lattice Place and Route Report for Design "GR8RAM_LCMXO2_1200HC_impl1_map.ncd"
Thu Jun 13 00:38:53 2024
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd GR8RAM_LCMXO2_1200HC_impl1.prf
Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file GR8RAM_LCMXO2_1200HC_impl1_map.ncd.
Design name: GR8RAM
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 73+4(JTAG)/108 71% used
73+4(JTAG)/80 96% bonded
IOLOGIC 51/108 47% used
SLICE 136/640 21% used
GSR 1/1 100% used
Number of Signals: 430
Number of Connections: 1211
Pin Constraint Summary:
73 out of 73 pins locked (100% locked).
The following 2 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 80)
PHI0_c (driver: PHI0, clk load #: 14)
WARNING - par: Signal "PHI0_c" is selected to use Primary clock resources. However, its driver comp "PHI0" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 1 signal is selected to use the secondary clock routing resources:
FCKout120 (driver: SLICE_54, clk load #: 0, sr load #: 13, ce load #: 0)
Signal nRESr is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
....................
Placer score = 87858.
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
.
Placer score = 86903
Finished Placer Phase 2. REAL time: 4 secs
------------------ Clock Report ------------------
Global Clock Resources:
CLK_PIN : 1 out of 8 (12%)
General PIO: 1 out of 108 (0%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "38 (PB11A)", clk load = 80
PRIMARY "PHI0_c" from comp "PHI0" on PIO site "17 (PL8B)", clk load = 14
SECONDARY "FCKout120" from F0 on comp "SLICE_54" on site "R7C12B", clk load = 0, ce load = 0, sr load = 13
PRIMARY : 2 out of 8 (25%)
SECONDARY: 1 out of 8 (12%)
Edge Clocks:
No edge clock selected.
--------------- End of Clock Report ---------------
I/O Usage Summary (final):
73 + 4(JTAG) out of 108 (71.3%) PIO sites used.
73 + 4(JTAG) out of 80 (96.3%) bonded PIO sites used.
Number of PIO comps: 73; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 13 / 19 ( 68%) | 3.3V | - |
| 1 | 20 / 21 ( 95%) | 3.3V | - |
| 2 | 20 / 20 (100%) | 3.3V | - |
| 3 | 20 / 20 (100%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 3 secs
Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
-----------------------------------------------------------------
INFO - par: ASE feature is off due to non timing-driven settings.
-----------------------------------------------------------------
0 connections routed; 1211 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 9 secs
Start NBR router at 00:39:02 06/13/24
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 00:39:02 06/13/24
Start NBR section for initial routing at 00:39:02 06/13/24
Level 4, iteration 1
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 00:39:02 06/13/24
Level 4, iteration 1
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Start NBR section for re-routing at 00:39:02 06/13/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Start NBR section for post-routing at 00:39:02 06/13/24
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : <n/a>
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 8 secs
Total REAL time: 9 secs
Completely routed.
End of route. 1211 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a>
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a>
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 9 secs
Total REAL time to completion: 10 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.prf
+82
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@@ -0,0 +1,82 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Thu Jun 13 00:38:53 2024
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "65" ;
LOCATE COMP "nFCS" SITE "88" ;
LOCATE COMP "RCLKout" SITE "39" ;
LOCATE COMP "RCLK" SITE "38" ;
LOCATE COMP "MOSI" SITE "97" ;
LOCATE COMP "MISO" SITE "98" ;
LOCATE COMP "FCK" SITE "96" ;
LOCATE COMP "SD[7]" SITE "31" ;
LOCATE COMP "SD[6]" SITE "30" ;
LOCATE COMP "SD[5]" SITE "29" ;
LOCATE COMP "SD[4]" SITE "28" ;
LOCATE COMP "SD[3]" SITE "27" ;
LOCATE COMP "SD[2]" SITE "21" ;
LOCATE COMP "SD[1]" SITE "24" ;
LOCATE COMP "SD[0]" SITE "25" ;
LOCATE COMP "RCKE" SITE "40" ;
LOCATE COMP "DQMH" SITE "34" ;
LOCATE COMP "DQML" SITE "32" ;
LOCATE COMP "nSWE" SITE "35" ;
LOCATE COMP "nCAS" SITE "36" ;
LOCATE COMP "nRAS" SITE "37" ;
LOCATE COMP "nRCS" SITE "41" ;
LOCATE COMP "SA[12]" SITE "42" ;
LOCATE COMP "SA[11]" SITE "45" ;
LOCATE COMP "SA[10]" SITE "47" ;
LOCATE COMP "SA[9]" SITE "49" ;
LOCATE COMP "SA[8]" SITE "53" ;
LOCATE COMP "SA[7]" SITE "57" ;
LOCATE COMP "SA[6]" SITE "62" ;
LOCATE COMP "SA[5]" SITE "52" ;
LOCATE COMP "SA[4]" SITE "51" ;
LOCATE COMP "SA[3]" SITE "60" ;
LOCATE COMP "SA[2]" SITE "58" ;
LOCATE COMP "SA[1]" SITE "59" ;
LOCATE COMP "SA[0]" SITE "54" ;
LOCATE COMP "SBA[1]" SITE "48" ;
LOCATE COMP "SBA[0]" SITE "43" ;
LOCATE COMP "nIOSTRB" SITE "18" ;
LOCATE COMP "nDEVSEL" SITE "16" ;
LOCATE COMP "nIOSEL" SITE "15" ;
LOCATE COMP "nDinOE" SITE "77" ;
LOCATE COMP "nDoutOE" SITE "1" ;
LOCATE COMP "RD[7]" SITE "75" ;
LOCATE COMP "RD[6]" SITE "71" ;
LOCATE COMP "RD[5]" SITE "70" ;
LOCATE COMP "RD[4]" SITE "69" ;
LOCATE COMP "RD[3]" SITE "68" ;
LOCATE COMP "RD[2]" SITE "67" ;
LOCATE COMP "RD[1]" SITE "66" ;
LOCATE COMP "nWE" SITE "19" ;
LOCATE COMP "RA[15]" SITE "14" ;
LOCATE COMP "RA[14]" SITE "13" ;
LOCATE COMP "RA[13]" SITE "10" ;
LOCATE COMP "RA[12]" SITE "9" ;
LOCATE COMP "RA[11]" SITE "8" ;
LOCATE COMP "RA[10]" SITE "3" ;
LOCATE COMP "RA[9]" SITE "2" ;
LOCATE COMP "RA[8]" SITE "99" ;
LOCATE COMP "RA[7]" SITE "87" ;
LOCATE COMP "RA[6]" SITE "86" ;
LOCATE COMP "RA[5]" SITE "85" ;
LOCATE COMP "RA[4]" SITE "4" ;
LOCATE COMP "RA[3]" SITE "84" ;
LOCATE COMP "RA[2]" SITE "83" ;
LOCATE COMP "RA[1]" SITE "78" ;
LOCATE COMP "RA[0]" SITE "74" ;
LOCATE COMP "LED" SITE "81" ;
LOCATE COMP "SetFW[1]" SITE "63" ;
LOCATE COMP "SetFW[0]" SITE "64" ;
LOCATE COMP "nIRQout" SITE "12" ;
LOCATE COMP "nRESout" SITE "7" ;
LOCATE COMP "nRES" SITE "20" ;
LOCATE COMP "PHI0" SITE "17" ;
SCHEMATIC END ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
VOLTAGE 3.300 V;
COMMERCIAL ;
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.pt
+10
View File
@@ -0,0 +1,10 @@
-v
10
-gt
-sethld
-sp 4
-sphld m
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.srd
BIN
View File
Binary file not shown.
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.srf
+561
View File
@@ -0,0 +1,561 @@
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Thu Jun 13 00:38:45 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v" (library work)
Verilog syntax check successful!
File \\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v changed - recompiling
Selecting top level module GR8RAM
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
Running optimization stage 1 on ODDRXE .......
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":1:7:1:12|Synthesizing module GR8RAM in library work.
Running optimization stage 1 on GR8RAM .......
Running optimization stage 2 on GR8RAM .......
@N: CL201 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":49:1:49:6|Trying to extract state machine for register IS.
Running optimization stage 2 on ODDRXE .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:46 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:46 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:46 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:47 2024
###########################################################]
# Thu Jun 13 00:38:47 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
@A: MF827 |No constraint file specified.
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
@A: FX681 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":36:1:36:6|Initial value on register PS[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
syn_allowed_resources : blockrams=7 set on top level netlist GR8RAM
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
------------------------------------------------------------------------------------------------
0 - GR8RAM|RCLK 100.0 MHz 10.000 inferred Inferred_clkgroup_1 104
0 - GR8RAM|PHI0 100.0 MHz 10.000 inferred Inferred_clkgroup_0 18
================================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
------------------------------------------------------------------------------------------------
GR8RAM|RCLK 104 RCLK(port) PHI0r[4:1].C - un1_RCLK.I[0](inv)
GR8RAM|PHI0 18 PHI0(port) RAr[11:0].C PHI0r[4:1].D[0] nDoutOE.I[0](inv)
================================================================================================
@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":67:1:67:6|Found inferred clock GR8RAM|PHI0 which controls 18 sequential elements including CXXXr. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":20:16:20:21|Found inferred clock GR8RAM|RCLK which controls 104 sequential elements including nRESf. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 118 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 RCLK Unconstrained_port 104 nRESf
@KP:ckid0_1 PHI0 Unconstrained_port 14 CXXXr
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jun 13 00:38:48 2024
###########################################################]
# Thu Jun 13 00:38:48 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nRAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nCAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
@N: FX493 |Applying initial value "000" on instance IS[2:0].
@N: FX493 |Applying initial value "0000" on instance PS[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":44:1:44:6|Found counter in view:work.GR8RAM(verilog) instance LS[13:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 1.70ns 247 / 118
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 166MB)
Writing Analyst data base \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 167MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
@W: MT246 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":10:11:10:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock GR8RAM|PHI0 with period 10.00ns. Please declare a user-defined clock on port PHI0.
@W: MT420 |Found inferred clock GR8RAM|RCLK with period 10.00ns. Please declare a user-defined clock on port RCLK.
##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jun 13 00:38:51 2024
#
Top view: GR8RAM
Requested Frequency: 100.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 1.955
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------
GR8RAM|PHI0 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0
GR8RAM|RCLK 100.0 MHz 134.3 MHz 10.000 7.448 1.955 inferred Inferred_clkgroup_1
System 100.0 MHz NA 10.000 NA NA system system_clkgroup
=====================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
GR8RAM|PHI0 GR8RAM|RCLK | Diff grp - | No paths - | Diff grp - | No paths -
GR8RAM|RCLK GR8RAM|RCLK | 10.000 2.552 | No paths - | 5.000 1.955 | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: GR8RAM|RCLK
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------
PS[3] GR8RAM|RCLK FD1S3AX Q PS[3] 1.309 1.955
PS[0] GR8RAM|RCLK FD1S3AX Q PS[0] 1.305 1.958
PS[2] GR8RAM|RCLK FD1S3AX Q PS[2] 1.296 1.968
PS[1] GR8RAM|RCLK FD1S3AX Q PS[1] 1.288 1.976
Addr[1] GR8RAM|RCLK FD1S3DX Q Addr[1] 1.232 2.009
SetFWr_0io[1] GR8RAM|RCLK IFS1P3DX Q SetFWr[1] 1.232 2.009
Addr[2] GR8RAM|RCLK FD1S3DX Q Addr[2] 1.228 2.013
Addr[3] GR8RAM|RCLK FD1S3DX Q Addr[3] 1.220 2.021
Addr[10] GR8RAM|RCLK FD1S3DX Q Addr[10] 1.220 2.021
Addr[4] GR8RAM|RCLK FD1S3DX Q Addr[4] 1.204 2.037
======================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
RDD[0] GR8RAM|RCLK FD1P3AX SP RDD37 4.528 1.955
RDD_0io[1] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[2] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[3] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[4] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[5] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[6] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[7] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[1] GR8RAM|RCLK OFS1P3DX D RDD_8[1] 5.089 2.009
RDD_0io[4] GR8RAM|RCLK OFS1P3DX D RDD_8[4] 5.089 2.009
===================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 5.000
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 4.528
- Propagation time: 2.573
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 1.955
Number of logic level(s): 1
Starting point: PS[3] / Q
Ending point: RDD[0] / SP
The start point is clocked by GR8RAM|RCLK [rising] on pin CK
The end point is clocked by GR8RAM|RCLK [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
PS[3] FD1S3AX Q Out 1.309 1.309 -
PS[3] Net - - - - 28
RDD37_0_a2 ORCALUT4 D In 0.000 1.309 -
RDD37_0_a2 ORCALUT4 Z Out 1.265 2.573 -
RDD37 Net - - - - 8
RDD[0] FD1P3AX SP In 0.000 2.573 -
=================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
Register bits: 118 of 1280 (9%)
PIC Latch: 0
I/O cells: 73
Details:
BB: 17
CCU2D: 13
FD1P3AX: 24
FD1S3AX: 17
FD1S3DX: 27
GSR: 1
IB: 26
IFS1P3DX: 18
INV: 7
OB: 28
OBZ: 2
ODDRXE: 1
OFS1P3BX: 7
OFS1P3DX: 12
OFS1P3IX: 10
OFS1P3JX: 3
ORCALUT4: 240
PFUMX: 7
PUR: 1
VHI: 1
VLO: 1
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 171MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Thu Jun 13 00:38:51 2024
###########################################################]
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.srm
BIN
View File
Binary file not shown.
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.srr
+561
View File
@@ -0,0 +1,561 @@
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Thu Jun 13 00:38:45 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v" (library work)
Verilog syntax check successful!
File \\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v changed - recompiling
Selecting top level module GR8RAM
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
Running optimization stage 1 on ODDRXE .......
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":1:7:1:12|Synthesizing module GR8RAM in library work.
Running optimization stage 1 on GR8RAM .......
Running optimization stage 2 on GR8RAM .......
@N: CL201 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":49:1:49:6|Trying to extract state machine for register IS.
Running optimization stage 2 on ODDRXE .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:46 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:46 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:46 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:47 2024
###########################################################]
# Thu Jun 13 00:38:47 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
@A: MF827 |No constraint file specified.
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
@A: FX681 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":36:1:36:6|Initial value on register PS[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
syn_allowed_resources : blockrams=7 set on top level netlist GR8RAM
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
------------------------------------------------------------------------------------------------
0 - GR8RAM|RCLK 100.0 MHz 10.000 inferred Inferred_clkgroup_1 104
0 - GR8RAM|PHI0 100.0 MHz 10.000 inferred Inferred_clkgroup_0 18
================================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
------------------------------------------------------------------------------------------------
GR8RAM|RCLK 104 RCLK(port) PHI0r[4:1].C - un1_RCLK.I[0](inv)
GR8RAM|PHI0 18 PHI0(port) RAr[11:0].C PHI0r[4:1].D[0] nDoutOE.I[0](inv)
================================================================================================
@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":67:1:67:6|Found inferred clock GR8RAM|PHI0 which controls 18 sequential elements including CXXXr. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":20:16:20:21|Found inferred clock GR8RAM|RCLK which controls 104 sequential elements including nRESf. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 118 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 RCLK Unconstrained_port 104 nRESf
@KP:ckid0_1 PHI0 Unconstrained_port 14 CXXXr
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jun 13 00:38:48 2024
###########################################################]
# Thu Jun 13 00:38:48 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nRAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nCAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
@N: FX493 |Applying initial value "000" on instance IS[2:0].
@N: FX493 |Applying initial value "0000" on instance PS[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":44:1:44:6|Found counter in view:work.GR8RAM(verilog) instance LS[13:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 1.70ns 247 / 118
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 166MB)
Writing Analyst data base \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 167MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
@W: MT246 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":10:11:10:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock GR8RAM|PHI0 with period 10.00ns. Please declare a user-defined clock on port PHI0.
@W: MT420 |Found inferred clock GR8RAM|RCLK with period 10.00ns. Please declare a user-defined clock on port RCLK.
##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jun 13 00:38:51 2024
#
Top view: GR8RAM
Requested Frequency: 100.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 1.955
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------
GR8RAM|PHI0 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0
GR8RAM|RCLK 100.0 MHz 134.3 MHz 10.000 7.448 1.955 inferred Inferred_clkgroup_1
System 100.0 MHz NA 10.000 NA NA system system_clkgroup
=====================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
GR8RAM|PHI0 GR8RAM|RCLK | Diff grp - | No paths - | Diff grp - | No paths -
GR8RAM|RCLK GR8RAM|RCLK | 10.000 2.552 | No paths - | 5.000 1.955 | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: GR8RAM|RCLK
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------
PS[3] GR8RAM|RCLK FD1S3AX Q PS[3] 1.309 1.955
PS[0] GR8RAM|RCLK FD1S3AX Q PS[0] 1.305 1.958
PS[2] GR8RAM|RCLK FD1S3AX Q PS[2] 1.296 1.968
PS[1] GR8RAM|RCLK FD1S3AX Q PS[1] 1.288 1.976
Addr[1] GR8RAM|RCLK FD1S3DX Q Addr[1] 1.232 2.009
SetFWr_0io[1] GR8RAM|RCLK IFS1P3DX Q SetFWr[1] 1.232 2.009
Addr[2] GR8RAM|RCLK FD1S3DX Q Addr[2] 1.228 2.013
Addr[3] GR8RAM|RCLK FD1S3DX Q Addr[3] 1.220 2.021
Addr[10] GR8RAM|RCLK FD1S3DX Q Addr[10] 1.220 2.021
Addr[4] GR8RAM|RCLK FD1S3DX Q Addr[4] 1.204 2.037
======================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
RDD[0] GR8RAM|RCLK FD1P3AX SP RDD37 4.528 1.955
RDD_0io[1] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[2] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[3] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[4] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[5] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[6] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[7] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[1] GR8RAM|RCLK OFS1P3DX D RDD_8[1] 5.089 2.009
RDD_0io[4] GR8RAM|RCLK OFS1P3DX D RDD_8[4] 5.089 2.009
===================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 5.000
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 4.528
- Propagation time: 2.573
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 1.955
Number of logic level(s): 1
Starting point: PS[3] / Q
Ending point: RDD[0] / SP
The start point is clocked by GR8RAM|RCLK [rising] on pin CK
The end point is clocked by GR8RAM|RCLK [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
PS[3] FD1S3AX Q Out 1.309 1.309 -
PS[3] Net - - - - 28
RDD37_0_a2 ORCALUT4 D In 0.000 1.309 -
RDD37_0_a2 ORCALUT4 Z Out 1.265 2.573 -
RDD37 Net - - - - 8
RDD[0] FD1P3AX SP In 0.000 2.573 -
=================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
Register bits: 118 of 1280 (9%)
PIC Latch: 0
I/O cells: 73
Details:
BB: 17
CCU2D: 13
FD1P3AX: 24
FD1S3AX: 17
FD1S3DX: 27
GSR: 1
IB: 26
IFS1P3DX: 18
INV: 7
OB: 28
OBZ: 2
ODDRXE: 1
OFS1P3BX: 7
OFS1P3DX: 12
OFS1P3IX: 10
OFS1P3JX: 3
ORCALUT4: 240
PFUMX: 7
PUR: 1
VHI: 1
VLO: 1
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 171MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Thu Jun 13 00:38:51 2024
###########################################################]
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.srr.db
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cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.t2b
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-g RamCfg:Reset
-path "//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC"
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_bgn.html
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<HTML>
<HEAD><TITLE>Bitgen Report</TITLE>
<STYLE TYPE="text/css">
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<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Jun 13 00:38:22 2024
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml GR8RAM_LCMXO2_1200HC_impl1.ncd GR8RAM_LCMXO2_1200HC_impl1.prf
Loading design for application Bitgen from file GR8RAM_LCMXO2_1200HC_impl1.ncd.
Design name: GR8RAM
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from GR8RAM_LCMXO2_1200HC_impl1.prf.
<A name="bgn_ps"></A>
<B><U><big>Preference Summary:</big></U></B>
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| RamCfg | Reset** |
+---------------------------------+---------------------------------+
| MCCLK_FREQ | 2.08** |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| JTAG_PORT | ENABLE** |
+---------------------------------+---------------------------------+
| SDM_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| SLAVE_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MASTER_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| I2C_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MUX_CONFIGURATION_PORTS | DISABLE** |
+---------------------------------+---------------------------------+
| CONFIGURATION | CFG** |
+---------------------------------+---------------------------------+
| COMPRESS_CONFIG | ON** |
+---------------------------------+---------------------------------+
| MY_ASSP | OFF** |
+---------------------------------+---------------------------------+
| ONE_TIME_PROGRAM | OFF** |
+---------------------------------+---------------------------------+
| ENABLE_TRANSFR | DISABLE** |
+---------------------------------+---------------------------------+
| SHAREDEBRINIT | DISABLE** |
+---------------------------------+---------------------------------+
| BACKGROUND_RECONFIG | OFF** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "GR8RAM_LCMXO2_1200HC_impl1.jed".
===========
UFM Summary.
===========
UFM Size: 511 Pages (128*511 Bits).
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
Initialized UFM Pages: 0 Page.
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Peak Memory Usage: 275 MB
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cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_cck.rpt
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Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Thu Jun 13 00:38:48 2024
##### DESIGN INFO #######################################################
Top View: "GR8RAM"
Constraint File(s): (none)
##### SUMMARY ############################################################
Found 0 issues in 0 out of 0 constraints
##### DETAILS ############################################################
Clock Relationships
*******************
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------
GR8RAM|PHI0 GR8RAM|RCLK | Diff grp | No paths | Diff grp | No paths
GR8RAM|RCLK GR8RAM|RCLK | 10.000 | No paths | 5.000 | No paths
===========================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Unconstrained Start/End Points
******************************
p:DQMH
p:DQML
p:FCK
p:LED
p:MISO
p:MOSI (bidir end point)
p:MOSI (bidir start point)
p:RA[0]
p:RA[1]
p:RA[2]
p:RA[3]
p:RA[4]
p:RA[5]
p:RA[6]
p:RA[7]
p:RA[8]
p:RA[9]
p:RA[10]
p:RA[11]
p:RA[12]
p:RA[13]
p:RA[14]
p:RA[15]
p:RCKE
p:RCLKout
p:RD[0] (bidir end point)
p:RD[0] (bidir start point)
p:RD[1] (bidir end point)
p:RD[1] (bidir start point)
p:RD[2] (bidir end point)
p:RD[2] (bidir start point)
p:RD[3] (bidir end point)
p:RD[3] (bidir start point)
p:RD[4] (bidir end point)
p:RD[4] (bidir start point)
p:RD[5] (bidir end point)
p:RD[5] (bidir start point)
p:RD[6] (bidir end point)
p:RD[6] (bidir start point)
p:RD[7] (bidir end point)
p:RD[7] (bidir start point)
p:SA[0]
p:SA[1]
p:SA[2]
p:SA[3]
p:SA[4]
p:SA[5]
p:SA[6]
p:SA[7]
p:SA[8]
p:SA[9]
p:SA[10]
p:SA[11]
p:SA[12]
p:SBA[0]
p:SBA[1]
p:SD[0] (bidir end point)
p:SD[0] (bidir start point)
p:SD[1] (bidir end point)
p:SD[1] (bidir start point)
p:SD[2] (bidir end point)
p:SD[2] (bidir start point)
p:SD[3] (bidir end point)
p:SD[3] (bidir start point)
p:SD[4] (bidir end point)
p:SD[4] (bidir start point)
p:SD[5] (bidir end point)
p:SD[5] (bidir start point)
p:SD[6] (bidir end point)
p:SD[6] (bidir start point)
p:SD[7] (bidir end point)
p:SD[7] (bidir start point)
p:SetFW[0]
p:SetFW[1]
p:nCAS
p:nDEVSEL
p:nDinOE
p:nFCS
p:nIOSEL
p:nIOSTRB
p:nIRQout
p:nRAS
p:nRCS
p:nRES
p:nRESout
p:nSWE
p:nWE
Inapplicable constraints
************************
(none)
Applicable constraints with issues
**********************************
(none)
Constraints with matching wildcard expressions
**********************************************
(none)
Library Report
**************
# End of Constraint Checker Report
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_cck.rpt.db
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cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_map.asd
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[ActiveSupport MAP]
Device = LCMXO2-1200HC;
Package = TQFP100;
Performance = 4;
LUTS_avail = 1280;
LUTS_used = 268;
FF_avail = 1360;
FF_used = 118;
INPUT_LVCMOS33 = 26;
OUTPUT_LVCMOS33 = 30;
BIDI_LVCMOS33 = 17;
IO_avail = 80;
IO_used = 73;
EBR_avail = 7;
EBR_used = 0;
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_map.cam
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[ START MERGED ]
FCKOE_i FCKOE
nRESr_i nRESr
PS_i[0] PS[0]
RDD_0_.CN RCLK_c
MOSIOE_i MOSIOE
SDOE_i SDOE
[ END MERGED ]
[ START CLIPPED ]
LS_s_0_S1[13]
LS_s_0_COUT[13]
un1_Addr_1_cry_0_0_S0
N_2
un1_Addr_1_s_7_0_S1
un1_Addr_1_s_7_0_COUT
LS_cry_0_S0[0]
N_1
[ END CLIPPED ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Thu Jun 13 00:38:53 2024
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "65" ;
LOCATE COMP "nFCS" SITE "88" ;
LOCATE COMP "RCLKout" SITE "39" ;
LOCATE COMP "RCLK" SITE "38" ;
LOCATE COMP "MOSI" SITE "97" ;
LOCATE COMP "MISO" SITE "98" ;
LOCATE COMP "FCK" SITE "96" ;
LOCATE COMP "SD[7]" SITE "31" ;
LOCATE COMP "SD[6]" SITE "30" ;
LOCATE COMP "SD[5]" SITE "29" ;
LOCATE COMP "SD[4]" SITE "28" ;
LOCATE COMP "SD[3]" SITE "27" ;
LOCATE COMP "SD[2]" SITE "21" ;
LOCATE COMP "SD[1]" SITE "24" ;
LOCATE COMP "SD[0]" SITE "25" ;
LOCATE COMP "RCKE" SITE "40" ;
LOCATE COMP "DQMH" SITE "34" ;
LOCATE COMP "DQML" SITE "32" ;
LOCATE COMP "nSWE" SITE "35" ;
LOCATE COMP "nCAS" SITE "36" ;
LOCATE COMP "nRAS" SITE "37" ;
LOCATE COMP "nRCS" SITE "41" ;
LOCATE COMP "SA[12]" SITE "42" ;
LOCATE COMP "SA[11]" SITE "45" ;
LOCATE COMP "SA[10]" SITE "47" ;
LOCATE COMP "SA[9]" SITE "49" ;
LOCATE COMP "SA[8]" SITE "53" ;
LOCATE COMP "SA[7]" SITE "57" ;
LOCATE COMP "SA[6]" SITE "62" ;
LOCATE COMP "SA[5]" SITE "52" ;
LOCATE COMP "SA[4]" SITE "51" ;
LOCATE COMP "SA[3]" SITE "60" ;
LOCATE COMP "SA[2]" SITE "58" ;
LOCATE COMP "SA[1]" SITE "59" ;
LOCATE COMP "SA[0]" SITE "54" ;
LOCATE COMP "SBA[1]" SITE "48" ;
LOCATE COMP "SBA[0]" SITE "43" ;
LOCATE COMP "nIOSTRB" SITE "18" ;
LOCATE COMP "nDEVSEL" SITE "16" ;
LOCATE COMP "nIOSEL" SITE "15" ;
LOCATE COMP "nDinOE" SITE "77" ;
LOCATE COMP "nDoutOE" SITE "1" ;
LOCATE COMP "RD[7]" SITE "75" ;
LOCATE COMP "RD[6]" SITE "71" ;
LOCATE COMP "RD[5]" SITE "70" ;
LOCATE COMP "RD[4]" SITE "69" ;
LOCATE COMP "RD[3]" SITE "68" ;
LOCATE COMP "RD[2]" SITE "67" ;
LOCATE COMP "RD[1]" SITE "66" ;
LOCATE COMP "nWE" SITE "19" ;
LOCATE COMP "RA[15]" SITE "14" ;
LOCATE COMP "RA[14]" SITE "13" ;
LOCATE COMP "RA[13]" SITE "10" ;
LOCATE COMP "RA[12]" SITE "9" ;
LOCATE COMP "RA[11]" SITE "8" ;
LOCATE COMP "RA[10]" SITE "3" ;
LOCATE COMP "RA[9]" SITE "2" ;
LOCATE COMP "RA[8]" SITE "99" ;
LOCATE COMP "RA[7]" SITE "87" ;
LOCATE COMP "RA[6]" SITE "86" ;
LOCATE COMP "RA[5]" SITE "85" ;
LOCATE COMP "RA[4]" SITE "4" ;
LOCATE COMP "RA[3]" SITE "84" ;
LOCATE COMP "RA[2]" SITE "83" ;
LOCATE COMP "RA[1]" SITE "78" ;
LOCATE COMP "RA[0]" SITE "74" ;
LOCATE COMP "LED" SITE "81" ;
LOCATE COMP "SetFW[1]" SITE "63" ;
LOCATE COMP "SetFW[0]" SITE "64" ;
LOCATE COMP "nIRQout" SITE "12" ;
LOCATE COMP "nRESout" SITE "7" ;
LOCATE COMP "nRES" SITE "20" ;
LOCATE COMP "PHI0" SITE "17" ;
SCHEMATIC END ;
[ END DESIGN PREFS ]
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_map.hrr
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---------------------------------------------------
Report for cell GR8RAM
Instance path: GR8RAM
Cell usage:
cell count Res Usage(%)
SLIC 136.00 100.0
IOLGC 50.00 100.0
LUT4 242.00 100.0
IOREG 50 100.0
IOBUF 73 100.0
PFUREG 68 100.0
RIPPLE 13 100.0
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_map.ncd
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<HTML>
<HEAD><TITLE>Project Summary</TITLE>
<STYLE TYPE="text/css">
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body,pre{ font-family:'Courier New', monospace; color: #000000; font-size:88%; background-color: #ffffff; } h1 { font-weight: bold; margin-top: 24px; margin-bottom: 10px; border-bottom: 3px solid #000; font-size: 1em; } h2 { font-weight: bold; margin-top: 18px; margin-bottom: 5px; font-size: 0.90em; } h3 { font-weight: bold; margin-top: 12px; margin-bottom: 5px; font-size: 0.80em; } p { font-size:78%; } P.Table { margin-top: 4px; margin-bottom: 4px; margin-right: 4px; margin-left: 4px; } table { border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; border-collapse: collapse; } th { font-weight:bold; padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; text-align:left; font-size:78%; } td { padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; font-size:78%; } a { color:#013C9A; text-decoration:none; } a:visited { color:#013C9A; } a:hover, a:active { text-decoration:underline; color:#5BAFD4; } .pass { background-color: #00ff00; } .fail { background-color: #ff0000; } .comment { font-size: 90%; font-style: italic; }
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<PRE><A name="Mrp"></A>
Lattice Mapping Report File for Design Module 'GR8RAM'
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
GR8RAM_LCMXO2_1200HC_impl1.ngd -o GR8RAM_LCMXO2_1200HC_impl1_map.ncd -pr
GR8RAM_LCMXO2_1200HC_impl1.prf -mp GR8RAM_LCMXO2_1200HC_impl1.mrp -lpf //Ma
c/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_s
ynplify.lpf -lpf //Mac/iCloud/Repos/GR8RAM/cpld/GR8RAM-LCMXO2.lpf -c 0 -gui
-msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
Mapped on: 06/13/24 00:38:52
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
Number of registers: 118 out of 1520 (8%)
PFU registers: 68 out of 1280 (5%)
PIO registers: 50 out of 240 (21%)
Number of SLICEs: 136 out of 640 (21%)
SLICEs as Logic/ROM: 136 out of 640 (21%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 13 out of 640 (2%)
Number of LUT4s: 268 out of 1280 (21%)
Number used as logic LUTs: 242
Number used as distributed RAM: 0
Number used as ripple logic: 26
Number used as shift registers: 0
Number of PIO sites used: 73 + 4(JTAG) out of 80 (96%)
Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
Number of IDDR cells: 0
Number of ODDR cells: 1
Number of TDDR cells: 0
Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
Number of PIO using IDDR only: 0 (0 differential)
Number of PIO using ODDR only: 1 (0 differential)
Number of PIO using TDDR only: 0 (0 differential)
Number of PIO using IDDR/ODDR: 0 (0 differential)
Number of PIO using IDDR/TDDR: 0 (0 differential)
Number of PIO using ODDR/TDDR: 0 (0 differential)
Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 1 out of 1 (100%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 2
Net RCLK_c: 80 loads, 72 rising, 8 falling (Driver: PIO RCLK )
Net PHI0_c: 14 loads, 14 rising, 0 falling (Driver: PIO PHI0 )
Number of Clock Enables: 6
Net un1_nRESout4_1_i_0: 2 loads, 2 LSLICEs
Net PS[0]: 5 loads, 3 LSLICEs
Net SetFWr3: 2 loads, 0 LSLICEs
Net N_254_i: 8 loads, 8 LSLICEs
Net Bank5: 1 loads, 0 LSLICEs
Net RDD37: 8 loads, 1 LSLICEs
Number of local set/reset loads for net nRESr merged into GSR: 28
Number of LSRs: 1
Net FCKout120: 13 loads, 0 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net PS[0]: 33 loads
Net SBA14: 31 loads
Net N_248: 29 loads
Net PS[3]: 28 loads
Net PS[2]: 24 loads
Net PS[1]: 23 loads
Net RAr[1]: 20 loads
Net RAMSpecSEL: 19 loads
Net FCKout120: 18 loads
Net un1_PS_6: 14 loads
Number of warnings: 1
Number of errors: 0
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
WARNING - map: Using local reset signal 'nRESr' to infer global GSR net.
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| nFCS | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RCLKout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RCLK | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MOSI | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MISO | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| FCK | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SD[7] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SD[6] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SD[5] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SD[4] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SD[3] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SD[2] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SD[1] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SD[0] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RCKE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQMH | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQML | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nSWE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRCS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[12] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[9] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[8] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[7] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[6] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[5] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[4] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[3] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[2] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SBA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| SBA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nIOSTRB | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDEVSEL | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nIOSEL | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDinOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDoutOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[5] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[4] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nWE | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[15] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[14] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[13] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[12] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[11] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[10] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[9] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[8] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[7] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[6] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[5] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[4] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[3] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[2] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[1] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RA[0] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SetFW[1] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| SetFW[0] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| nIRQout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nRESout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nRES | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| PHI0 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
Signal SDOE_i was merged into signal SDOE
Signal MOSIOE_i was merged into signal MOSIOE
Signal FCKOE_i was merged into signal FCKOE
Signal nRESr_i was merged into signal nRESr
Signal PS_i[0] was merged into signal PS[0]
Signal RDD_0_.CN was merged into signal RCLK_c
Signal LS_s_0_S1[13] undriven or does not drive anything - clipped.
Signal LS_s_0_COUT[13] undriven or does not drive anything - clipped.
Signal un1_Addr_1_cry_0_0_S0 undriven or does not drive anything - clipped.
Signal N_2 undriven or does not drive anything - clipped.
Signal un1_Addr_1_s_7_0_S1 undriven or does not drive anything - clipped.
Signal un1_Addr_1_s_7_0_COUT undriven or does not drive anything - clipped.
Signal LS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block SDOE_RNIBPBD was optimized away.
Block MOSI_pad_RNO was optimized away.
Block FCKOE_RNI8HE1 was optimized away.
Block nRESr_RNIAPB9 was optimized away.
Block PS_RNIBBDD[0] was optimized away.
Block RDD_0_.CN was optimized away.
<A name="mrp_gsr"></A><B><U><big>GSR Usage</big></U></B>
---------
GSR Component:
The local reset signal 'nRESr' of the design has been inferred as Global Set
Reset (GSR). The reset signal used for GSR control is 'nRESr'.
GSR Property:
The design components with GSR property set to ENABLED will respond to global
set reset while the components with GSR property set to DISABLED will
not.
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 64 MB
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved.
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body,pre{ font-family:'Courier New', monospace; color: #000000; font-size:88%; background-color: #ffffff; } h1 { font-weight: bold; margin-top: 24px; margin-bottom: 10px; border-bottom: 3px solid #000; font-size: 1em; } h2 { font-weight: bold; margin-top: 18px; margin-bottom: 5px; font-size: 0.90em; } h3 { font-weight: bold; margin-top: 12px; margin-bottom: 5px; font-size: 0.80em; } p { font-size:78%; } P.Table { margin-top: 4px; margin-bottom: 4px; margin-right: 4px; margin-left: 4px; } table { border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; border-collapse: collapse; } th { font-weight:bold; padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; text-align:left; font-size:78%; } td { padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; font-size:78%; } a { color:#013C9A; text-decoration:none; } a:visited { color:#013C9A; } a:hover, a:active { text-decoration:underline; color:#5BAFD4; } .pass { background-color: #00ff00; } .fail { background-color: #ff0000; } .comment { font-size: 90%; font-style: italic; }
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<PRE><A name="Pad"></A>PAD Specification File
***************************
PART TYPE: LCMXO2-1200HC
Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.42
Thu Jun 13 00:38:57 2024
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| DQMH | 34/2 | LVCMOS33_OUT | PB9A | | | DRIVE:4mA SLEW:SLOW |
| DQML | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
| FCK | 96/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| LED | 81/0 | LVCMOS33_OUT | PT15D | | | DRIVE:24mA SLEW:SLOW |
| MISO | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
| MOSI | 97/0 | LVCMOS33_BIDI | PT10A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| PHI0 | 17/3 | LVCMOS33_IN | PL8B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[0] | 74/1 | LVCMOS33_IN | PR2B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[10] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[11] | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[12] | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[13] | 10/3 | LVCMOS33_IN | PL4B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[14] | 13/3 | LVCMOS33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[15] | 14/3 | LVCMOS33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[1] | 78/0 | LVCMOS33_IN | PT16C | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[2] | 83/0 | LVCMOS33_IN | PT15B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[3] | 84/0 | LVCMOS33_IN | PT15A | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[4] | 4/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[5] | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[6] | 86/0 | LVCMOS33_IN | PT12C | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[8] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[9] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
| RCKE | 40/2 | LVCMOS33_OUT | PB15A | | | DRIVE:4mA SLEW:SLOW |
| RCLK | 38/2 | LVCMOS33_IN | PB11A | | | CLAMP:ON HYSTERESIS:SMALL |
| RCLKout | 39/2 | LVCMOS33_OUT | PB11B | | | DRIVE:24mA SLEW:FAST |
| RD[0] | 65/1 | LVCMOS33_BIDI | PR5A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 66/1 | LVCMOS33_BIDI | PR4D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 67/1 | LVCMOS33_BIDI | PR4C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 68/1 | LVCMOS33_BIDI | PR4B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 69/1 | LVCMOS33_BIDI | PR4A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 70/1 | LVCMOS33_BIDI | PR3B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 71/1 | LVCMOS33_BIDI | PR3A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 75/1 | LVCMOS33_BIDI | PR2A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SA[0] | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
| SA[10] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
| SA[11] | 45/2 | LVCMOS33_OUT | PB18C | | | DRIVE:4mA SLEW:SLOW |
| SA[12] | 42/2 | LVCMOS33_OUT | PB18A | | | DRIVE:4mA SLEW:SLOW |
| SA[1] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
| SA[2] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
| SA[3] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
| SA[4] | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| SA[5] | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
| SA[6] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
| SA[7] | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
| SA[8] | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| SA[9] | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
| SBA[0] | 43/2 | LVCMOS33_OUT | PB18B | | | DRIVE:4mA SLEW:SLOW |
| SBA[1] | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
| SD[0] | 25/3 | LVCMOS33_BIDI | PL10D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[1] | 24/3 | LVCMOS33_BIDI | PL10C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[2] | 21/3 | LVCMOS33_BIDI | PL9B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[3] | 27/2 | LVCMOS33_BIDI | PB4C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[4] | 28/2 | LVCMOS33_BIDI | PB4D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[5] | 29/2 | LVCMOS33_BIDI | PB6A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[6] | 30/2 | LVCMOS33_BIDI | PB6B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SD[7] | 31/2 | LVCMOS33_BIDI | PB6C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| SetFW[0] | 64/1 | LVCMOS33_IN | PR5B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
| SetFW[1] | 63/1 | LVCMOS33_IN | PR5C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
| nCAS | 36/2 | LVCMOS33_OUT | PB11C | | | DRIVE:4mA SLEW:SLOW |
| nDEVSEL | 16/3 | LVCMOS33_IN | PL8A | | | CLAMP:ON HYSTERESIS:SMALL |
| nDinOE | 77/0 | LVCMOS33_OUT | PT17C | | | DRIVE:4mA SLEW:SLOW |
| nDoutOE | 1/3 | LVCMOS33_OUT | PL2C | | | DRIVE:4mA SLEW:SLOW |
| nFCS | 88/0 | LVCMOS33_OUT | PT12A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| nIOSEL | 15/3 | LVCMOS33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL |
| nIOSTRB | 18/3 | LVCMOS33_IN | PL8C | | | CLAMP:ON HYSTERESIS:SMALL |
| nIRQout | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
| nRAS | 37/2 | LVCMOS33_OUT | PB11D | | | DRIVE:4mA SLEW:SLOW |
| nRCS | 41/2 | LVCMOS33_OUT | PB15B | | | DRIVE:4mA SLEW:SLOW |
| nRES | 20/3 | LVCMOS33_IN | PL9A | | | CLAMP:ON HYSTERESIS:SMALL |
| nRESout | 7/3 | LVCMOS33_OUT | PL3C | | | DRIVE:4mA SLEW:SLOW |
| nSWE | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW |
| nWE | 19/3 | LVCMOS33_IN | PL8D | | | CLAMP:ON HYSTERESIS:SMALL |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
| 2 | 3.3V |
| 3 | 3.3V |
+------+-------+
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | nDoutOE | LOCATED | LVCMOS33_OUT | PL2C | L_GPLLT_IN | | |
| 2/3 | RA[9] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
| 3/3 | RA[10] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
| 4/3 | RA[4] | LOCATED | LVCMOS33_IN | PL3B | PCLKC3_2 | | |
| 7/3 | nRESout | LOCATED | LVCMOS33_OUT | PL3C | | | |
| 8/3 | RA[11] | LOCATED | LVCMOS33_IN | PL3D | | | |
| 9/3 | RA[12] | LOCATED | LVCMOS33_IN | PL4A | | | |
| 10/3 | RA[13] | LOCATED | LVCMOS33_IN | PL4B | | | |
| 12/3 | nIRQout | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
| 13/3 | RA[14] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
| 14/3 | RA[15] | LOCATED | LVCMOS33_IN | PL5C | | | |
| 15/3 | nIOSEL | LOCATED | LVCMOS33_IN | PL5D | | | |
| 16/3 | nDEVSEL | LOCATED | LVCMOS33_IN | PL8A | | | |
| 17/3 | PHI0 | LOCATED | LVCMOS33_IN | PL8B | | | |
| 18/3 | nIOSTRB | LOCATED | LVCMOS33_IN | PL8C | | | |
| 19/3 | nWE | LOCATED | LVCMOS33_IN | PL8D | | | |
| 20/3 | nRES | LOCATED | LVCMOS33_IN | PL9A | PCLKT3_0 | | |
| 21/3 | SD[2] | LOCATED | LVCMOS33_BIDI | PL9B | PCLKC3_0 | | |
| 24/3 | SD[1] | LOCATED | LVCMOS33_BIDI | PL10C | | | |
| 25/3 | SD[0] | LOCATED | LVCMOS33_BIDI | PL10D | | | |
| 27/2 | SD[3] | LOCATED | LVCMOS33_BIDI | PB4C | CSSPIN | | |
| 28/2 | SD[4] | LOCATED | LVCMOS33_BIDI | PB4D | | | |
| 29/2 | SD[5] | LOCATED | LVCMOS33_BIDI | PB6A | | | |
| 30/2 | SD[6] | LOCATED | LVCMOS33_BIDI | PB6B | | | |
| 31/2 | SD[7] | LOCATED | LVCMOS33_BIDI | PB6C | MCLK/CCLK | | |
| 32/2 | DQML | LOCATED | LVCMOS33_OUT | PB6D | SO/SPISO | | |
| 34/2 | DQMH | LOCATED | LVCMOS33_OUT | PB9A | PCLKT2_0 | | |
| 35/2 | nSWE | LOCATED | LVCMOS33_OUT | PB9B | PCLKC2_0 | | |
| 36/2 | nCAS | LOCATED | LVCMOS33_OUT | PB11C | | | |
| 37/2 | nRAS | LOCATED | LVCMOS33_OUT | PB11D | | | |
| 38/2 | RCLK | LOCATED | LVCMOS33_IN | PB11A | PCLKT2_1 | | |
| 39/2 | RCLKout | LOCATED | LVCMOS33_OUT | PB11B | PCLKC2_1 | | |
| 40/2 | RCKE | LOCATED | LVCMOS33_OUT | PB15A | | | |
| 41/2 | nRCS | LOCATED | LVCMOS33_OUT | PB15B | | | |
| 42/2 | SA[12] | LOCATED | LVCMOS33_OUT | PB18A | | | |
| 43/2 | SBA[0] | LOCATED | LVCMOS33_OUT | PB18B | | | |
| 45/2 | SA[11] | LOCATED | LVCMOS33_OUT | PB18C | | | |
| 47/2 | SA[10] | LOCATED | LVCMOS33_OUT | PB18D | | | |
| 48/2 | SBA[1] | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
| 49/2 | SA[9] | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
| 51/1 | SA[4] | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
| 52/1 | SA[5] | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
| 53/1 | SA[8] | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
| 54/1 | SA[0] | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
| 57/1 | SA[7] | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
| 58/1 | SA[2] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
| 59/1 | SA[1] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 60/1 | SA[3] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
| 62/1 | SA[6] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
| 63/1 | SetFW[1] | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | SetFW[0] | LOCATED | LVCMOS33_IN | PR5B | DQS0N | | |
| 65/1 | RD[0] | LOCATED | LVCMOS33_BIDI | PR5A | DQS0 | | |
| 66/1 | RD[1] | LOCATED | LVCMOS33_BIDI | PR4D | DQ0 | | |
| 67/1 | RD[2] | LOCATED | LVCMOS33_BIDI | PR4C | DQ0 | | |
| 68/1 | RD[3] | LOCATED | LVCMOS33_BIDI | PR4B | DQ0 | | |
| 69/1 | RD[4] | LOCATED | LVCMOS33_BIDI | PR4A | DQ0 | | |
| 70/1 | RD[5] | LOCATED | LVCMOS33_BIDI | PR3B | DQ0 | | |
| 71/1 | RD[6] | LOCATED | LVCMOS33_BIDI | PR3A | DQ0 | | |
| 74/1 | RA[0] | LOCATED | LVCMOS33_IN | PR2B | DQ0 | | |
| 75/1 | RD[7] | LOCATED | LVCMOS33_BIDI | PR2A | DQ0 | | |
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
| 77/0 | nDinOE | LOCATED | LVCMOS33_OUT | PT17C | INITN | | |
| 78/0 | RA[1] | LOCATED | LVCMOS33_IN | PT16C | | | |
| 81/0 | LED | LOCATED | LVCMOS33_OUT | PT15D | PROGRAMN | | |
| 82/0 | unused, PULL:DOWN | | | PT15C | JTAGENB | | |
| 83/0 | RA[2] | LOCATED | LVCMOS33_IN | PT15B | | | |
| 84/0 | RA[3] | LOCATED | LVCMOS33_IN | PT15A | | | |
| 85/0 | RA[5] | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | |
| 86/0 | RA[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | |
| 87/0 | RA[7] | LOCATED | LVCMOS33_IN | PT12B | PCLKC0_1 | | |
| 88/0 | nFCS | LOCATED | LVCMOS33_OUT | PT12A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
| 96/0 | FCK | LOCATED | LVCMOS33_OUT | PT10B | | | |
| 97/0 | MOSI | LOCATED | LVCMOS33_BIDI | PT10A | | | |
| 98/0 | MISO | LOCATED | LVCMOS33_IN | PT9B | | | |
| 99/0 | RA[8] | LOCATED | LVCMOS33_IN | PT9A | | | |
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "DQMH" SITE "34";
LOCATE COMP "DQML" SITE "32";
LOCATE COMP "FCK" SITE "96";
LOCATE COMP "LED" SITE "81";
LOCATE COMP "MISO" SITE "98";
LOCATE COMP "MOSI" SITE "97";
LOCATE COMP "PHI0" SITE "17";
LOCATE COMP "RA[0]" SITE "74";
LOCATE COMP "RA[10]" SITE "3";
LOCATE COMP "RA[11]" SITE "8";
LOCATE COMP "RA[12]" SITE "9";
LOCATE COMP "RA[13]" SITE "10";
LOCATE COMP "RA[14]" SITE "13";
LOCATE COMP "RA[15]" SITE "14";
LOCATE COMP "RA[1]" SITE "78";
LOCATE COMP "RA[2]" SITE "83";
LOCATE COMP "RA[3]" SITE "84";
LOCATE COMP "RA[4]" SITE "4";
LOCATE COMP "RA[5]" SITE "85";
LOCATE COMP "RA[6]" SITE "86";
LOCATE COMP "RA[7]" SITE "87";
LOCATE COMP "RA[8]" SITE "99";
LOCATE COMP "RA[9]" SITE "2";
LOCATE COMP "RCKE" SITE "40";
LOCATE COMP "RCLK" SITE "38";
LOCATE COMP "RCLKout" SITE "39";
LOCATE COMP "RD[0]" SITE "65";
LOCATE COMP "RD[1]" SITE "66";
LOCATE COMP "RD[2]" SITE "67";
LOCATE COMP "RD[3]" SITE "68";
LOCATE COMP "RD[4]" SITE "69";
LOCATE COMP "RD[5]" SITE "70";
LOCATE COMP "RD[6]" SITE "71";
LOCATE COMP "RD[7]" SITE "75";
LOCATE COMP "SA[0]" SITE "54";
LOCATE COMP "SA[10]" SITE "47";
LOCATE COMP "SA[11]" SITE "45";
LOCATE COMP "SA[12]" SITE "42";
LOCATE COMP "SA[1]" SITE "59";
LOCATE COMP "SA[2]" SITE "58";
LOCATE COMP "SA[3]" SITE "60";
LOCATE COMP "SA[4]" SITE "51";
LOCATE COMP "SA[5]" SITE "52";
LOCATE COMP "SA[6]" SITE "62";
LOCATE COMP "SA[7]" SITE "57";
LOCATE COMP "SA[8]" SITE "53";
LOCATE COMP "SA[9]" SITE "49";
LOCATE COMP "SBA[0]" SITE "43";
LOCATE COMP "SBA[1]" SITE "48";
LOCATE COMP "SD[0]" SITE "25";
LOCATE COMP "SD[1]" SITE "24";
LOCATE COMP "SD[2]" SITE "21";
LOCATE COMP "SD[3]" SITE "27";
LOCATE COMP "SD[4]" SITE "28";
LOCATE COMP "SD[5]" SITE "29";
LOCATE COMP "SD[6]" SITE "30";
LOCATE COMP "SD[7]" SITE "31";
LOCATE COMP "SetFW[0]" SITE "64";
LOCATE COMP "SetFW[1]" SITE "63";
LOCATE COMP "nCAS" SITE "36";
LOCATE COMP "nDEVSEL" SITE "16";
LOCATE COMP "nDinOE" SITE "77";
LOCATE COMP "nDoutOE" SITE "1";
LOCATE COMP "nFCS" SITE "88";
LOCATE COMP "nIOSEL" SITE "15";
LOCATE COMP "nIOSTRB" SITE "18";
LOCATE COMP "nIRQout" SITE "12";
LOCATE COMP "nRAS" SITE "37";
LOCATE COMP "nRCS" SITE "41";
LOCATE COMP "nRES" SITE "20";
LOCATE COMP "nRESout" SITE "7";
LOCATE COMP "nSWE" SITE "35";
LOCATE COMP "nWE" SITE "19";
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Jun 13 00:39:01 2024
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Jun 13 00:38:53 2024
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f GR8RAM_LCMXO2_1200HC_impl1.p2t
GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir
GR8RAM_LCMXO2_1200HC_impl1.prf -gui -msgset
//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml
Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 - - - - 10 Completed
* : Design saved.
Total (real) run time for 1-seed: 10 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Lattice Place and Route Report for Design &quot;GR8RAM_LCMXO2_1200HC_impl1_map.ncd&quot;
Thu Jun 13 00:38:53 2024
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd GR8RAM_LCMXO2_1200HC_impl1.prf
Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file GR8RAM_LCMXO2_1200HC_impl1_map.ncd.
Design name: GR8RAM
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application par from file &apos;xo2c1200.nph&apos; in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
PIO (prelim) 73+4(JTAG)/108 71% used
73+4(JTAG)/80 96% bonded
IOLOGIC 51/108 47% used
SLICE 136/640 21% used
GSR 1/1 100% used
Number of Signals: 430
Number of Connections: 1211
Pin Constraint Summary:
73 out of 73 pins locked (100% locked).
The following 2 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 80)
PHI0_c (driver: PHI0, clk load #: 14)
WARNING - par: Signal &quot;PHI0_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;PHI0&quot; is located at &quot;17&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 1 signal is selected to use the secondary clock routing resources:
FCKout120 (driver: SLICE_54, clk load #: 0, sr load #: 13, ce load #: 0)
Signal nRESr is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
....................
Placer score = 87858.
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
.
Placer score = 86903
Finished Placer Phase 2. REAL time: 4 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
CLK_PIN : 1 out of 8 (12%)
General PIO: 1 out of 108 (0%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY &quot;RCLK_c&quot; from comp &quot;RCLK&quot; on CLK_PIN site &quot;38 (PB11A)&quot;, clk load = 80
PRIMARY &quot;PHI0_c&quot; from comp &quot;PHI0&quot; on PIO site &quot;17 (PL8B)&quot;, clk load = 14
SECONDARY &quot;FCKout120&quot; from F0 on comp &quot;SLICE_54&quot; on site &quot;R7C12B&quot;, clk load = 0, ce load = 0, sr load = 13
PRIMARY : 2 out of 8 (25%)
SECONDARY: 1 out of 8 (12%)
Edge Clocks:
No edge clock selected.
I/O Usage Summary (final):
73 + 4(JTAG) out of 108 (71.3%) PIO sites used.
73 + 4(JTAG) out of 80 (96.3%) bonded PIO sites used.
Number of PIO comps: 73; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 13 / 19 ( 68%) | 3.3V | - |
| 1 | 20 / 21 ( 95%) | 3.3V | - |
| 2 | 20 / 20 (100%) | 3.3V | - |
| 3 | 20 / 20 (100%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 3 secs
Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
-----------------------------------------------------------------
INFO - par: ASE feature is off due to non timing-driven settings.
-----------------------------------------------------------------
0 connections routed; 1211 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 9 secs
Start NBR router at 00:39:02 06/13/24
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 00:39:02 06/13/24
Start NBR section for initial routing at 00:39:02 06/13/24
Level 4, iteration 1
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 00:39:02 06/13/24
Level 4, iteration 1
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Start NBR section for re-routing at 00:39:02 06/13/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Start NBR section for post-routing at 00:39:02 06/13/24
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack&lt;setup&gt; : &lt;n/a&gt;
Timing score&lt;setup&gt; : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 8 secs
Total REAL time: 9 secs
Completely routed.
End of route. 1211 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 9 secs
Total REAL time to completion: 10 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Thu Jun 13 00:38:47 2024
##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): (none)
#Run constraint checker to find more issues with constraints.
#########################################################################
No issues found in constraint syntax.
Clock Summary
*************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
------------------------------------------------------------------------------------------------
0 - GR8RAM|RCLK 100.0 MHz 10.000 inferred Inferred_clkgroup_1 104
0 - GR8RAM|PHI0 100.0 MHz 10.000 inferred Inferred_clkgroup_0 18
================================================================================================
Clock Load Summary
******************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
------------------------------------------------------------------------------------------------
GR8RAM|RCLK 104 RCLK(port) PHI0r[4:1].C - un1_RCLK.I[0](inv)
GR8RAM|PHI0 18 PHI0(port) RAr[11:0].C PHI0r[4:1].D[0] nDoutOE.I[0](inv)
================================================================================================
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_scck.rpt.db
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<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
<TR>
<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>GR8RAM_LCMXO2_1200HC project summary</B></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">GR8RAM_LCMXO2_1200HC</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">SynplifyPro</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC-4TG100C</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO2</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">4</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">GR8RAM-LCMXO2.lpf</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/GR8RAM_LCMXO2_1200HC_impl1.prf</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.11.3.469</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/06/13 00:39:07</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/impl1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC.ldf</SPAN></TD>
</TR>
</small></TABLE>
<BR>
<BR>
<BR>
<BR>
<BR>
</PRE></FONT>
</BODY>
</HTML>
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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Thu Jun 13 00:38:45 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v" (library work)
Verilog syntax check successful!
File \\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v changed - recompiling
Selecting top level module GR8RAM
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
Running optimization stage 1 on ODDRXE .......
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":1:7:1:12|Synthesizing module GR8RAM in library work.
Running optimization stage 1 on GR8RAM .......
Running optimization stage 2 on GR8RAM .......
@N: CL201 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":49:1:49:6|Trying to extract state machine for register IS.
Running optimization stage 2 on ODDRXE .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:46 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:46 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:46 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:47 2024
###########################################################]
# Thu Jun 13 00:38:47 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
@A: MF827 |No constraint file specified.
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
@A: FX681 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":36:1:36:6|Initial value on register PS[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
syn_allowed_resources : blockrams=7 set on top level netlist GR8RAM
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
------------------------------------------------------------------------------------------------
0 - GR8RAM|RCLK 100.0 MHz 10.000 inferred Inferred_clkgroup_1 104
0 - GR8RAM|PHI0 100.0 MHz 10.000 inferred Inferred_clkgroup_0 18
================================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
------------------------------------------------------------------------------------------------
GR8RAM|RCLK 104 RCLK(port) PHI0r[4:1].C - un1_RCLK.I[0](inv)
GR8RAM|PHI0 18 PHI0(port) RAr[11:0].C PHI0r[4:1].D[0] nDoutOE.I[0](inv)
================================================================================================
@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":67:1:67:6|Found inferred clock GR8RAM|PHI0 which controls 18 sequential elements including CXXXr. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":20:16:20:21|Found inferred clock GR8RAM|RCLK which controls 104 sequential elements including nRESf. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 118 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 RCLK Unconstrained_port 104 nRESf
@KP:ckid0_1 PHI0 Unconstrained_port 14 CXXXr
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jun 13 00:38:48 2024
###########################################################]
# Thu Jun 13 00:38:48 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nRAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nCAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
@N: FX493 |Applying initial value "000" on instance IS[2:0].
@N: FX493 |Applying initial value "0000" on instance PS[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":44:1:44:6|Found counter in view:work.GR8RAM(verilog) instance LS[13:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 1.70ns 247 / 118
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 166MB)
Writing Analyst data base \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 167MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
@W: MT246 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":10:11:10:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock GR8RAM|PHI0 with period 10.00ns. Please declare a user-defined clock on port PHI0.
@W: MT420 |Found inferred clock GR8RAM|RCLK with period 10.00ns. Please declare a user-defined clock on port RCLK.
##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jun 13 00:38:51 2024
#
Top view: GR8RAM
Requested Frequency: 100.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 1.955
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------
GR8RAM|PHI0 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0
GR8RAM|RCLK 100.0 MHz 134.3 MHz 10.000 7.448 1.955 inferred Inferred_clkgroup_1
System 100.0 MHz NA 10.000 NA NA system system_clkgroup
=====================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
GR8RAM|PHI0 GR8RAM|RCLK | Diff grp - | No paths - | Diff grp - | No paths -
GR8RAM|RCLK GR8RAM|RCLK | 10.000 2.552 | No paths - | 5.000 1.955 | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: GR8RAM|RCLK
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------
PS[3] GR8RAM|RCLK FD1S3AX Q PS[3] 1.309 1.955
PS[0] GR8RAM|RCLK FD1S3AX Q PS[0] 1.305 1.958
PS[2] GR8RAM|RCLK FD1S3AX Q PS[2] 1.296 1.968
PS[1] GR8RAM|RCLK FD1S3AX Q PS[1] 1.288 1.976
Addr[1] GR8RAM|RCLK FD1S3DX Q Addr[1] 1.232 2.009
SetFWr_0io[1] GR8RAM|RCLK IFS1P3DX Q SetFWr[1] 1.232 2.009
Addr[2] GR8RAM|RCLK FD1S3DX Q Addr[2] 1.228 2.013
Addr[3] GR8RAM|RCLK FD1S3DX Q Addr[3] 1.220 2.021
Addr[10] GR8RAM|RCLK FD1S3DX Q Addr[10] 1.220 2.021
Addr[4] GR8RAM|RCLK FD1S3DX Q Addr[4] 1.204 2.037
======================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
RDD[0] GR8RAM|RCLK FD1P3AX SP RDD37 4.528 1.955
RDD_0io[1] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[2] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[3] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[4] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[5] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[6] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[7] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[1] GR8RAM|RCLK OFS1P3DX D RDD_8[1] 5.089 2.009
RDD_0io[4] GR8RAM|RCLK OFS1P3DX D RDD_8[4] 5.089 2.009
===================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 5.000
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 4.528
- Propagation time: 2.573
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 1.955
Number of logic level(s): 1
Starting point: PS[3] / Q
Ending point: RDD[0] / SP
The start point is clocked by GR8RAM|RCLK [rising] on pin CK
The end point is clocked by GR8RAM|RCLK [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
PS[3] FD1S3AX Q Out 1.309 1.309 -
PS[3] Net - - - - 28
RDD37_0_a2 ORCALUT4 D In 0.000 1.309 -
RDD37_0_a2 ORCALUT4 Z Out 1.265 2.573 -
RDD37 Net - - - - 8
RDD[0] FD1P3AX SP In 0.000 2.573 -
=================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
Register bits: 118 of 1280 (9%)
PIC Latch: 0
I/O cells: 73
Details:
BB: 17
CCU2D: 13
FD1P3AX: 24
FD1S3AX: 17
FD1S3DX: 27
GSR: 1
IB: 26
IFS1P3DX: 18
INV: 7
OB: 28
OBZ: 2
ODDRXE: 1
OFS1P3BX: 7
OFS1P3DX: 12
OFS1P3IX: 10
OFS1P3JX: 3
ORCALUT4: 240
PFUMX: 7
PUR: 1
VHI: 1
VLO: 1
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 171MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Thu Jun 13 00:38:51 2024
###########################################################]
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cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_synplify.lpf
+24
View File
@@ -0,0 +1,24 @@
#
# Logical Preferences generated for Lattice by Synplify maplat2018q2p1, Build 055R.
#
# Period Constraints
#FREQUENCY PORT "PHI0" 100.0 MHz;
#FREQUENCY PORT "RCLK" 100.0 MHz;
# Output Constraints
# Input Constraints
# Point-to-point Delay Constraints
# Block Path Constraints
#BLOCK PATH FROM CLKNET "RCLK_c" TO CLKNET "PHI0_c";
#BLOCK PATH FROM CLKNET "PHI0_c" TO CLKNET "RCLK_c";
BLOCK ASYNCPATHS;
# End of generated Logical Preferences.
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_synplify.tcl
+63
View File
@@ -0,0 +1,63 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file
#device options
set_option -technology MACHXO2
set_option -part LCMXO2_1200HC
set_option -package TG100C
set_option -speed_grade -4
#compilation/mapping options
set_option -symbolic_fsm_compiler true
set_option -resource_sharing true
#use verilog 2001 standard option
set_option -vlog_std v2001
#map options
set_option -frequency 100
set_option -maxfan 1000
set_option -auto_constrain_io 0
set_option -disable_io_insertion false
set_option -retiming false; set_option -pipe true
set_option -force_gsr false
set_option -compiler_compatible 0
set_option -dup false
set_option -default_enum_encoding default
#simulation options
#timing analysis options
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#synplifyPro options
set_option -fix_gated_and_generated_clocks 1
set_option -update_models_cp 0
set_option -resolve_multiple_driver 0
#-- add_file options
set_option -include_path {//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC}
add_file -verilog {//Mac/iCloud/Repos/GR8RAM/cpld/GR8RAM.v}
#-- top module name
set_option -top_module GR8RAM
#-- set result format/file last
project -result_file {//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.edi}
#-- error message log file
project -log_file {GR8RAM_LCMXO2_1200HC_impl1.srf}
#-- set any command lines input by customer
#-- run Synplify with 'arrange HDL file'
project -run -clean
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_synplify_tmp2.lpf
View File
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_synplify_tmp4.lpf
View File
cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_synplify_tmp8.lpf
View File
cpld/LCMXO2-1200HC/impl1/automake.log
+1035
View File
File diff suppressed because it is too large Load Diff
cpld/LCMXO2-1200HC/impl1/backup/GR8RAM_LCMXO2_1200HC_impl1.srr
+581
View File
@@ -0,0 +1,581 @@
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Thu Jun 13 00:16:40 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v" (library work)
Verilog syntax check successful!
Selecting top level module GR8RAM
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
Running optimization stage 1 on ODDRXE .......
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":1:7:1:12|Synthesizing module GR8RAM in library work.
Running optimization stage 1 on GR8RAM .......
Running optimization stage 2 on GR8RAM .......
@N: CL201 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":53:1:53:6|Trying to extract state machine for register IS.
Running optimization stage 2 on ODDRXE .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:16:40 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:16:40 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:16:40 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:16:41 2024
###########################################################]
Premap Report
# Thu Jun 13 00:16:42 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
@A: MF827 |No constraint file specified.
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
@A: FX681 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":40:1:40:6|Initial value on register PS[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
syn_allowed_resources : blockrams=7 set on top level netlist GR8RAM
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
------------------------------------------------------------------------------------------------
0 - GR8RAM|RCLK 100.0 MHz 10.000 inferred Inferred_clkgroup_1 105
0 - GR8RAM|PHI0 100.0 MHz 10.000 inferred Inferred_clkgroup_0 18
================================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
-------------------------------------------------------------------------------------------------
GR8RAM|RCLK 105 RCLK(port) SetFWr[1:0].C - un1_RCLK.I[0](inv)
GR8RAM|PHI0 18 PHI0(port) RAr[11:0].C PHI0r[4:1].D[0] nDoutOE.I[0](inv)
=================================================================================================
@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":71:1:71:6|Found inferred clock GR8RAM|PHI0 which controls 18 sequential elements including CXXXr. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":20:16:20:21|Found inferred clock GR8RAM|RCLK which controls 105 sequential elements including nRESf. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 119 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 RCLK Unconstrained_port 105 nRESf
@KP:ckid0_1 PHI0 Unconstrained_port 14 CXXXr
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jun 13 00:16:42 2024
###########################################################]
Map & Optimize Report
# Thu Jun 13 00:16:42 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":352:2:352:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":352:2:352:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":352:2:352:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":352:2:352:5|Found ROM nRAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":352:2:352:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":352:2:352:5|Found ROM nCAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
@N: FX493 |Applying initial value "000" on instance IS[2:0].
@N: FX493 |Applying initial value "0000" on instance PS[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":48:1:48:6|Found counter in view:work.GR8RAM(verilog) instance LS[13:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 162MB peak: 163MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 1.79ns 257 / 119
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 162MB peak: 163MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 162MB peak: 163MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 127MB peak: 163MB)
Writing Analyst data base \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 162MB peak: 164MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 166MB peak: 168MB)
Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 168MB)
@W: MT246 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":10:11:10:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock GR8RAM|PHI0 with period 10.00ns. Please declare a user-defined clock on port PHI0.
@W: MT420 |Found inferred clock GR8RAM|RCLK with period 10.00ns. Please declare a user-defined clock on port RCLK.
##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jun 13 00:16:45 2024
#
Top view: GR8RAM
Requested Frequency: 100.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 1.547
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------
GR8RAM|PHI0 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0
GR8RAM|RCLK 100.0 MHz 118.3 MHz 10.000 8.453 1.547 inferred Inferred_clkgroup_1
System 100.0 MHz NA 10.000 NA NA system system_clkgroup
=====================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
GR8RAM|PHI0 GR8RAM|RCLK | Diff grp - | No paths - | Diff grp - | No paths -
GR8RAM|RCLK GR8RAM|RCLK | 10.000 1.547 | No paths - | 5.000 1.944 | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: GR8RAM|RCLK
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------
REGEN GR8RAM|RCLK FD1S3AX Q REGEN 1.180 1.547
PS[0] GR8RAM|RCLK FD1S3AX Q PS[0] 1.312 1.944
PS[3] GR8RAM|RCLK FD1S3AX Q PS[3] 1.312 1.944
PS[1] GR8RAM|RCLK FD1S3AX Q PS[1] 1.309 1.947
PS[2] GR8RAM|RCLK FD1S3AX Q PS[2] 1.292 1.964
SetFWr_0io[1] GR8RAM|RCLK IFS1P3DX Q SetFWr[1] 1.232 2.009
Addr[2] GR8RAM|RCLK FD1S3DX Q Addr[2] 1.204 2.037
Addr[10] GR8RAM|RCLK FD1S3DX Q Addr[10] 1.204 2.037
Addr[0] GR8RAM|RCLK FD1S3DX Q Addr[0] 1.188 2.053
Addr[6] GR8RAM|RCLK FD1S3DX Q Addr[6] 1.188 2.053
======================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------
RCKE_0io GR8RAM|RCLK OFS1P3BX D N_284_i 10.089 1.547
nRCS_0io GR8RAM|RCLK OFS1P3BX D N_224_i 10.089 1.547
RDD[0] GR8RAM|RCLK FD1P3AX SP RDD37 4.528 1.944
RDD_0io[1] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.944
RDD_0io[2] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.944
RDD_0io[3] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.944
RDD_0io[4] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.944
RDD_0io[5] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.944
RDD_0io[6] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.944
RDD_0io[7] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.944
==================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: -0.089
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 10.089
- Propagation time: 8.541
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 1.547
Number of logic level(s): 7
Starting point: REGEN / Q
Ending point: RCKE_0io / D
The start point is clocked by GR8RAM|RCLK [rising] on pin CK
The end point is clocked by GR8RAM|RCLK [rising] on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
REGEN FD1S3AX Q Out 1.180 1.180 -
REGEN Net - - - - 5
RAMRegSpecSEL_0_o2 ORCALUT4 D In 0.000 1.180 -
RAMRegSpecSEL_0_o2 ORCALUT4 Z Out 1.193 2.373 -
N_296 Net - - - - 4
RAMSpecSEL_0_o2_0 ORCALUT4 B In 0.000 2.373 -
RAMSpecSEL_0_o2_0 ORCALUT4 Z Out 1.089 3.461 -
N_297 Net - - - - 2
RAMSpecSEL_0_o2 ORCALUT4 A In 0.000 3.461 -
RAMSpecSEL_0_o2 ORCALUT4 Z Out 1.341 4.802 -
N_72 Net - - - - 24
RCKE_10_4_0_o2 ORCALUT4 B In 0.000 4.802 -
RCKE_10_4_0_o2 ORCALUT4 Z Out 1.017 5.819 -
N_75 Net - - - - 1
RCKE_10_4_0_a3 ORCALUT4 A In 0.000 5.819 -
RCKE_10_4_0_a3 ORCALUT4 Z Out 1.089 6.908 -
N_171_3 Net - - - - 2
RCKE_10_9_i_a2_1 ORCALUT4 A In 0.000 6.908 -
RCKE_10_9_i_a2_1 ORCALUT4 Z Out 1.017 7.925 -
N_318 Net - - - - 1
RCKE_0io_RNO ORCALUT4 B In 0.000 7.925 -
RCKE_0io_RNO ORCALUT4 Z Out 0.617 8.541 -
N_284_i Net - - - - 1
RCKE_0io OFS1P3BX D In 0.000 8.541 -
=====================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 166MB peak: 168MB)
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 166MB peak: 168MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
Register bits: 119 of 1280 (9%)
PIC Latch: 0
I/O cells: 73
Details:
BB: 17
CCU2D: 13
FD1P3AX: 24
FD1S3AX: 18
FD1S3DX: 27
GSR: 1
IB: 26
IFS1P3DX: 18
INV: 8
OB: 28
OBZ: 2
ODDRXE: 1
OFS1P3BX: 7
OFS1P3DX: 12
OFS1P3IX: 10
OFS1P3JX: 3
ORCALUT4: 245
PFUMX: 7
PUR: 1
VHI: 1
VLO: 1
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 168MB)
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Thu Jun 13 00:16:45 2024
###########################################################]
cpld/LCMXO2-1200HC/impl1/dm/layer0.xdm
+65
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@@ -0,0 +1,65 @@
%%% protect protected_file
@EG<?lPDRCHs#F"M=4"3jROCMFM8Hok="0UV-"
?>
-<!-7R]pHR]CssNORE$7HCVMHH0FwMRHRDCwlFsN-0R-<>
]17p0Osk0CksRsPC#MHF=3"4j
">
!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S>
<k1Fs#OC>S
S<k1FsROCbB=":#\DO8O\HFNlMd8\3_44G\nc#b$MLCN#\LDH\ODkC\M0lENOG3F.PN"R=""jR"D=PHCsD"FoRHOD#"0=-R4"b#DH0-="4>"/
<SS1sFkObCR=:"B\OD#OH\8NMlF83\d4G4_n#c\$LMbN\#CD\HLDCkOMb0\l8H_CPV3"=RN"R4"DP="CDsHFRo"O#DH0-="4b"RD0H#=4"-"
/>S1S<FOksC=Rb"\B:DO#O\N8Hl8FM\4d34n_Gc$\#MNbL#DC\HPL\D\FoEC$bs8lF#"3PR"N=.D"R=C"PsFHDoO"RD0H#=4"-"DRbH=#0""-4/S>
SF<1kCsOR"b=BD:\#\OO8lHNF\M8d434_cGn\M#$b#LNCH\DLD\PFko\lOs_NlbH3RP"Nd=""=RD"sPCHoDF"DROH=#0""-4RHbD#"0=-/4">S
S<k1FsROCbB=":#\DO8O\HFNlMd8\3_44G\nc#b$MLCN#\LDH\FPDoO\#C_lHFCL[O30#PN"R=""cR"D=PHCsD"FoRHOD#"0=-R4"b#DH0-="4>"/
<SS1sFkObCR=:"B\OD#OH\8NMlF83\d4G4_n#c\$LMbN\#CD\HLPoDF\C#OlbH_H#bC3E#P"=RN"R6"DP="CDsHFRo"O#DH0-="4b"RD0H#=4"-"
/>S1S<FOksC=Rb"v\\NHO\BkDF8C\)b\F#t))UqOv\b\D8t))UqPv3"=RN"Rn"DP="CDsHFRo"O#DH0-="4b"RD0H#=4"-"
/>S1</FOksC
#>
!S<-v-RFD8kCFRsF-0R-S>
<F)F0=RM"sIF )3tUv)q3sPCHoDF"
/>
<
S!R--vkF8D7CRCMVHHF0HM-R-><
S7RCVMI="F3s m)77XP 3CDsHFRo"DP="CDsHF>o"
<SSW=RN"Rj"L"D=44nj"ORL=""(R=CD"j4n4C"RO4="./"R>S
S<MqR=C"3Gs0CM"NDR"P=4>"/
<SSq=RM"s3FHNohlRC"PI="F3s m)77X/ ">S
S<MqR=D"3NuMoNlsN#P"R=1"t)>"/
<SSu=RM")t1"=RP"k&JF 0;hpqA J7&k;F0"
/>SqS<R"M=3M#$_Ck#s"LLR"P=4>"/
<SSq=RM"C3bNl _C#lkN"oCR"P=((c36((dj>"/
<SSq=RM"D3OCkNMb0_#C_b.lkCl#CNo"=RP"jj3jjjjj>"/
<SSq=RM"D3OCkNMb0_#C_b.0CHl"=RP"jj3jjjjj>"/
<SSq=RM"D3OCkNMb0_#C_b4lkCl#CNo"=RP"jj3ng.c.>"/
<SSq=RM"D3OCkNMb0_#C_b40CHl"=RP"jj3jjjjj>"/
<SSq=RM"$3#MH_DLC_ODRD"P4=""
/>SqS<R"M=3M#$_C0sNN0_#D_LNLO FRG"P4=""
/>SqS<R"M=#_$MD_HLODCD"=RP"/4">
/S<7>CV
<
S!R--vkF8D7CRCMVHHF0HM-R-><
S7RCVMI="F3s t))UqPv3CDsHFRo"DP="CDsHF>o"
<SSW=RN"Rn"L"D=4L"RO(=""DRC=""4R=CO""4.R
/>SqS<R"M=38lFkVDCH"DCR"P=n>"/
<SSq=RM"s3FHNohlRC"PI="F3s t))Uq/v">S
S<MqR=b"3C_N lkCl#CNo"=RP"3(c(d6((/j">S
S<MqR=O"3DMCNk#b_0.Cb_llCko#NCP"R=3"..nd6n/c">S
S<MqR=O"3DMCNk#b_0.Cb_l0HCP"R=3"j46U(j/j">S
S<MqR=O"3DMCNk#b_04Cb_llCko#NCP"R=3"j(4jd4/(">S
S<MqR=O"3DMCNk#b_04Cb_l0HCP"R=3"jj4(U./6">S
S<MqR=#"30Dl0Hl#0C#lkN"oCR"P=jc3g6n.j"
/>SqS<R"M=3l#00#DH0l0HCP"R=3"jjn46./6">
<SS!R--vkF8D)CRCsVCCCMO#QR5MN#0MN0H0MHF#-2R-S>
SC<)V=RM"sIF 73m7 )X3sPCHoDF"=RH"DsO 8_F8>s"
SSS<NWR=""nR=LD""4jR=LO""44R=CD""4jR=CO""4gR
/>S/S<)>CV
/S<7>CV
]</70p1s0kOk>sC
@
cpld/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html
+26
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cpld/LCMXO2-1200HC/impl1/message.xml
+132
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@@ -0,0 +1,132 @@
<?xml version="1.0" encoding="UTF-8"?>
<BaliMessageLog>
<Task name="Map">
<Message>
<ID>51001030</ID>
<Severity>Warning</Severity>
<Dynamic>nRESr</Dynamic>
</Message>
</Task>
<Task name="PAR">
<Message>
<ID>61061008</ID>
<Severity>Warning</Severity>
<Dynamic>PHI0_c</Dynamic>
<Dynamic>Primary</Dynamic>
<Dynamic>PHI0</Dynamic>
<Dynamic>17</Dynamic>
<Dynamic>Primary</Dynamic>
</Message>
</Task>
<Task name="Synplify_Synthesis">
<Message>
<ID>2011000</ID>
<Severity>Info</Severity>
</Message>
<Message>
<ID>2019993</ID>
<Severity>Warning</Severity>
<Dynamic>FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.</Dynamic>
<Navigation>FX474</Navigation>
<Navigation>User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. </Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>MT529 :&quot;\\mac\icloud\repos\gr8ram\cpld\gr8ram.v&quot;:67:1:67:6|Found inferred clock GR8RAM|PHI0 which controls 18 sequential elements including CXXXr. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.</Dynamic>
<Navigation>MT529</Navigation>
<Navigation>\\mac\icloud\repos\gr8ram\cpld\gr8ram.v</Navigation>
<Navigation>67</Navigation>
<Navigation>1</Navigation>
<Navigation>67</Navigation>
<Navigation>6</Navigation>
<Navigation>Found inferred clock GR8RAM|PHI0 which controls 18 sequential elements including CXXXr. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>MT529 :&quot;\\mac\icloud\repos\gr8ram\cpld\gr8ram.v&quot;:20:16:20:21|Found inferred clock GR8RAM|RCLK which controls 104 sequential elements including nRESf. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.</Dynamic>
<Navigation>MT529</Navigation>
<Navigation>\\mac\icloud\repos\gr8ram\cpld\gr8ram.v</Navigation>
<Navigation>20</Navigation>
<Navigation>16</Navigation>
<Navigation>20</Navigation>
<Navigation>21</Navigation>
<Navigation>Found inferred clock GR8RAM|RCLK which controls 104 sequential elements including nRESf. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>FA239 :&quot;\\mac\icloud\repos\gr8ram\cpld\gr8ram.v&quot;:348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.</Dynamic>
<Navigation>FA239</Navigation>
<Navigation>\\mac\icloud\repos\gr8ram\cpld\gr8ram.v</Navigation>
<Navigation>348</Navigation>
<Navigation>2</Navigation>
<Navigation>348</Navigation>
<Navigation>5</Navigation>
<Navigation>ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.</Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>FA239 :&quot;\\mac\icloud\repos\gr8ram\cpld\gr8ram.v&quot;:348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.</Dynamic>
<Navigation>FA239</Navigation>
<Navigation>\\mac\icloud\repos\gr8ram\cpld\gr8ram.v</Navigation>
<Navigation>348</Navigation>
<Navigation>2</Navigation>
<Navigation>348</Navigation>
<Navigation>5</Navigation>
<Navigation>ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.</Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>FA239 :&quot;\\mac\icloud\repos\gr8ram\cpld\gr8ram.v&quot;:348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.</Dynamic>
<Navigation>FA239</Navigation>
<Navigation>\\mac\icloud\repos\gr8ram\cpld\gr8ram.v</Navigation>
<Navigation>348</Navigation>
<Navigation>2</Navigation>
<Navigation>348</Navigation>
<Navigation>5</Navigation>
<Navigation>ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.</Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>FA239 :&quot;\\mac\icloud\repos\gr8ram\cpld\gr8ram.v&quot;:348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.</Dynamic>
<Navigation>FA239</Navigation>
<Navigation>\\mac\icloud\repos\gr8ram\cpld\gr8ram.v</Navigation>
<Navigation>348</Navigation>
<Navigation>2</Navigation>
<Navigation>348</Navigation>
<Navigation>5</Navigation>
<Navigation>ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.</Navigation>
</Message>
<Message>
<ID>2019991</ID>
<Severity>Warning</Severity>
<Dynamic>MT246 :&quot;\\mac\icloud\repos\gr8ram\cpld\gr8ram.v&quot;:10:11:10:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)</Dynamic>
<Navigation>MT246</Navigation>
<Navigation>\\mac\icloud\repos\gr8ram\cpld\gr8ram.v</Navigation>
<Navigation>10</Navigation>
<Navigation>11</Navigation>
<Navigation>10</Navigation>
<Navigation>19</Navigation>
<Navigation>Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)</Navigation>
</Message>
<Message>
<ID>2019993</ID>
<Severity>Warning</Severity>
<Dynamic>MT420 |Found inferred clock GR8RAM|PHI0 with period 10.00ns. Please declare a user-defined clock on port PHI0.</Dynamic>
<Navigation>MT420</Navigation>
<Navigation>Found inferred clock GR8RAM|PHI0 with period 10.00ns. Please declare a user-defined clock on port PHI0.</Navigation>
</Message>
<Message>
<ID>2019993</ID>
<Severity>Warning</Severity>
<Dynamic>MT420 |Found inferred clock GR8RAM|RCLK with period 10.00ns. Please declare a user-defined clock on port RCLK.</Dynamic>
<Navigation>MT420</Navigation>
<Navigation>Found inferred clock GR8RAM|RCLK with period 10.00ns. Please declare a user-defined clock on port RCLK.</Navigation>
</Message>
</Task>
</BaliMessageLog>
cpld/LCMXO2-1200HC/impl1/run_options.txt
+77
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@@ -0,0 +1,77 @@
#-- Synopsys, Inc.
#-- Version N-2018.03L-SP1-1
#-- Project file \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\run_options.txt
#-- Written on Thu Jun 13 00:38:45 2024
#project files
add_file -verilog "//Mac/iCloud/Repos/GR8RAM/cpld/GR8RAM.v"
#implementation: "impl1"
impl -add impl1 -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -project_relative_includes 1
set_option -include_path {//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC}
#device options
set_option -technology MACHXO2
set_option -part LCMXO2_1200HC
set_option -package TG100C
set_option -speed_grade -4
set_option -part_companion ""
#compilation/mapping options
set_option -top_module "GR8RAM"
# hdl_compiler_options
set_option -distributed_compile 0
# mapper_without_write_options
set_option -frequency 100
set_option -srs_instrumentation 1
# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0
# Lattice XP
set_option -maxfan 1000
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 1
set_option -forcegsr false
set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1
set_option -update_models_cp 0
set_option -syn_edif_array_rename 1
set_option -Write_declared_clocks_only 1
# NFilter
set_option -no_sequential_opt 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./GR8RAM_LCMXO2_1200HC_impl1.edi"
#set log file
set_option log_file "//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.srf"
impl -active "impl1"
cpld/LCMXO2-1200HC/impl1/scratchproject.prs
+76
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@@ -0,0 +1,76 @@
#-- Synopsys, Inc.
#-- Version N-2018.03L-SP1-1
#-- Project file \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\scratchproject.prs
#project files
add_file -verilog "//Mac/iCloud/Repos/GR8RAM/cpld/GR8RAM.v"
#implementation: "impl1"
impl -add \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1 -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -project_relative_includes 1
set_option -include_path {//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/impl1/}
set_option -include_path {//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC}
#device options
set_option -technology MACHXO2
set_option -part LCMXO2_1200HC
set_option -package TG100C
set_option -speed_grade -4
set_option -part_companion ""
#compilation/mapping options
set_option -top_module "GR8RAM"
# hdl_compiler_options
set_option -distributed_compile 0
# mapper_without_write_options
set_option -frequency 100
set_option -srs_instrumentation 1
# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0
# Lattice XP
set_option -maxfan 1000
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 1
set_option -forcegsr false
set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1
set_option -update_models_cp 0
set_option -syn_edif_array_rename 1
set_option -Write_declared_clocks_only 1
# NFilter
set_option -no_sequential_opt 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.edi"
#set log file
set_option log_file "//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.srf"
impl -active "impl1"
cpld/LCMXO2-1200HC/impl1/stdout.log
+79
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@@ -0,0 +1,79 @@
Running in Lattice mode
Starting: C:\lscc\diamond\3.11_x64\synpbase\bin64\mbin\synbatch.exe
Install: C:\lscc\diamond\3.11_x64\synpbase
Hostname: ZANEMACWIN11
Date: Thu Jun 13 00:38:45 2024
Version: N-2018.03L-SP1-1
Arguments: -product synplify_pro -batch GR8RAM_LCMXO2_1200HC_impl1_synplify.tcl
ProductType: synplify_pro
log file: "\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srr"
Running: impl1 in foreground
Running proj_1|impl1
Running Flow: compile (Compile) on proj_1|impl1
# Thu Jun 13 00:38:45 2024
Running Flow: compile_flow (Compile Process) on proj_1|impl1
# Thu Jun 13 00:38:45 2024
Running: compiler (Compile Input) on proj_1|impl1
# Thu Jun 13 00:38:45 2024
Copied \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.srs to \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srs
compiler completed
# Thu Jun 13 00:38:47 2024
Return Code: 0
Run Time:00h:00m:02s
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
# Thu Jun 13 00:38:47 2024
multi_srs_gen completed
# Thu Jun 13 00:38:47 2024
Return Code: 0
Run Time:00h:00m:00s
Copied \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_mult.srs to \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srs
Copied \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srr to \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srf
Complete: Compile Process on proj_1|impl1
Running: premap (Premap) on proj_1|impl1
# Thu Jun 13 00:38:47 2024
premap completed with warnings
# Thu Jun 13 00:38:48 2024
Return Code: 1
Run Time:00h:00m:01s
Complete: Compile on proj_1|impl1
Running Flow: map (Map) on proj_1|impl1
# Thu Jun 13 00:38:48 2024
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
# Thu Jun 13 00:38:48 2024
Copied \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_m.srm to \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srm
fpga_mapper completed with warnings
# Thu Jun 13 00:38:51 2024
Return Code: 1
Run Time:00h:00m:03s
Complete: Map on proj_1|impl1
Copied \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srr to \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srf
Complete: Logic Synthesis on proj_1|impl1
TCL script complete: "GR8RAM_LCMXO2_1200HC_impl1_synplify.tcl"
exit status=0
exit status=0
Save changes for project:
\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\proj_1.prj
batch mode default:no
cpld/LCMXO2-1200HC/impl1/stdout.log.bak.1
+79
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@@ -0,0 +1,79 @@
Running in Lattice mode
Starting: C:\lscc\diamond\3.11_x64\synpbase\bin64\mbin\synbatch.exe
Install: C:\lscc\diamond\3.11_x64\synpbase
Hostname: ZANEMACWIN11
Date: Thu Jun 13 00:16:39 2024
Version: N-2018.03L-SP1-1
Arguments: -product synplify_pro -batch GR8RAM_LCMXO2_1200HC_impl1_synplify.tcl
ProductType: synplify_pro
log file: "\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srr"
Running: impl1 in foreground
Running proj_1|impl1
Running Flow: compile (Compile) on proj_1|impl1
# Thu Jun 13 00:16:40 2024
Running Flow: compile_flow (Compile Process) on proj_1|impl1
# Thu Jun 13 00:16:40 2024
Running: compiler (Compile Input) on proj_1|impl1
# Thu Jun 13 00:16:40 2024
Copied \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.srs to \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srs
compiler completed
# Thu Jun 13 00:16:41 2024
Return Code: 0
Run Time:00h:00m:01s
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
# Thu Jun 13 00:16:41 2024
multi_srs_gen completed
# Thu Jun 13 00:16:42 2024
Return Code: 0
Run Time:00h:00m:01s
Copied \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_mult.srs to \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srs
Copied \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srr to \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srf
Complete: Compile Process on proj_1|impl1
Running: premap (Premap) on proj_1|impl1
# Thu Jun 13 00:16:42 2024
premap completed with warnings
# Thu Jun 13 00:16:42 2024
Return Code: 1
Run Time:00h:00m:00s
Complete: Compile on proj_1|impl1
Running Flow: map (Map) on proj_1|impl1
# Thu Jun 13 00:16:42 2024
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
# Thu Jun 13 00:16:42 2024
Copied \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_m.srm to \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srm
fpga_mapper completed with warnings
# Thu Jun 13 00:16:45 2024
Return Code: 1
Run Time:00h:00m:03s
Complete: Map on proj_1|impl1
Copied \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srr to \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.srf
Complete: Logic Synthesis on proj_1|impl1
TCL script complete: "GR8RAM_LCMXO2_1200HC_impl1_synplify.tcl"
exit status=0
exit status=0
Save changes for project:
\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\proj_1.prj
batch mode default:no
cpld/LCMXO2-1200HC/impl1/synlog.tcl
+1
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@@ -0,0 +1 @@
run_tcl -fg GR8RAM_LCMXO2_1200HC_impl1_synplify.tcl
cpld/LCMXO2-1200HC/impl1/synlog/GR8RAM_LCMXO2_1200HC_impl1_compiler.srr
+101
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@@ -0,0 +1,101 @@
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v" (library work)
Verilog syntax check successful!
File \\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v changed - recompiling
Selecting top level module GR8RAM
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
Running optimization stage 1 on ODDRXE .......
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":1:7:1:12|Synthesizing module GR8RAM in library work.
Running optimization stage 1 on GR8RAM .......
Running optimization stage 2 on GR8RAM .......
@N: CL201 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":49:1:49:6|Trying to extract state machine for register IS.
Running optimization stage 2 on ODDRXE .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:46 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:46 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:46 2024
###########################################################]
cpld/LCMXO2-1200HC/impl1/synlog/GR8RAM_LCMXO2_1200HC_impl1_compiler.srr.db
BIN
View File
Binary file not shown.
cpld/LCMXO2-1200HC/impl1/synlog/GR8RAM_LCMXO2_1200HC_impl1_compiler.srr.rptmap
+1
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@@ -0,0 +1 @@
./synlog/GR8RAM_LCMXO2_1200HC_impl1_compiler.srr,GR8RAM_LCMXO2_1200HC_impl1_compiler.srr,Compile Log
cpld/LCMXO2-1200HC/impl1/synlog/GR8RAM_LCMXO2_1200HC_impl1_fpga_mapper.srr
+300
View File
@@ -0,0 +1,300 @@
# Thu Jun 13 00:38:48 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nRAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nCAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
@N: FX493 |Applying initial value "000" on instance IS[2:0].
@N: FX493 |Applying initial value "0000" on instance PS[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":44:1:44:6|Found counter in view:work.GR8RAM(verilog) instance LS[13:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 1.70ns 247 / 118
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 166MB)
Writing Analyst data base \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 167MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
@W: MT246 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":10:11:10:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock GR8RAM|PHI0 with period 10.00ns. Please declare a user-defined clock on port PHI0.
@W: MT420 |Found inferred clock GR8RAM|RCLK with period 10.00ns. Please declare a user-defined clock on port RCLK.
##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jun 13 00:38:51 2024
#
Top view: GR8RAM
Requested Frequency: 100.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 1.955
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------
GR8RAM|PHI0 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0
GR8RAM|RCLK 100.0 MHz 134.3 MHz 10.000 7.448 1.955 inferred Inferred_clkgroup_1
System 100.0 MHz NA 10.000 NA NA system system_clkgroup
=====================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
GR8RAM|PHI0 GR8RAM|RCLK | Diff grp - | No paths - | Diff grp - | No paths -
GR8RAM|RCLK GR8RAM|RCLK | 10.000 2.552 | No paths - | 5.000 1.955 | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: GR8RAM|RCLK
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------
PS[3] GR8RAM|RCLK FD1S3AX Q PS[3] 1.309 1.955
PS[0] GR8RAM|RCLK FD1S3AX Q PS[0] 1.305 1.958
PS[2] GR8RAM|RCLK FD1S3AX Q PS[2] 1.296 1.968
PS[1] GR8RAM|RCLK FD1S3AX Q PS[1] 1.288 1.976
Addr[1] GR8RAM|RCLK FD1S3DX Q Addr[1] 1.232 2.009
SetFWr_0io[1] GR8RAM|RCLK IFS1P3DX Q SetFWr[1] 1.232 2.009
Addr[2] GR8RAM|RCLK FD1S3DX Q Addr[2] 1.228 2.013
Addr[3] GR8RAM|RCLK FD1S3DX Q Addr[3] 1.220 2.021
Addr[10] GR8RAM|RCLK FD1S3DX Q Addr[10] 1.220 2.021
Addr[4] GR8RAM|RCLK FD1S3DX Q Addr[4] 1.204 2.037
======================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
RDD[0] GR8RAM|RCLK FD1P3AX SP RDD37 4.528 1.955
RDD_0io[1] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[2] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[3] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[4] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[5] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[6] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[7] GR8RAM|RCLK OFS1P3DX SP RDD37 4.528 1.955
RDD_0io[1] GR8RAM|RCLK OFS1P3DX D RDD_8[1] 5.089 2.009
RDD_0io[4] GR8RAM|RCLK OFS1P3DX D RDD_8[4] 5.089 2.009
===================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 5.000
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 4.528
- Propagation time: 2.573
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 1.955
Number of logic level(s): 1
Starting point: PS[3] / Q
Ending point: RDD[0] / SP
The start point is clocked by GR8RAM|RCLK [rising] on pin CK
The end point is clocked by GR8RAM|RCLK [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
PS[3] FD1S3AX Q Out 1.309 1.309 -
PS[3] Net - - - - 28
RDD37_0_a2 ORCALUT4 D In 0.000 1.309 -
RDD37_0_a2 ORCALUT4 Z Out 1.265 2.573 -
RDD37 Net - - - - 8
RDD[0] FD1P3AX SP In 0.000 2.573 -
=================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
Register bits: 118 of 1280 (9%)
PIC Latch: 0
I/O cells: 73
Details:
BB: 17
CCU2D: 13
FD1P3AX: 24
FD1S3AX: 17
FD1S3DX: 27
GSR: 1
IB: 26
IFS1P3DX: 18
INV: 7
OB: 28
OBZ: 2
ODDRXE: 1
OFS1P3BX: 7
OFS1P3DX: 12
OFS1P3IX: 10
OFS1P3JX: 3
ORCALUT4: 240
PFUMX: 7
PUR: 1
VHI: 1
VLO: 1
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 171MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Thu Jun 13 00:38:51 2024
###########################################################]
cpld/LCMXO2-1200HC/impl1/synlog/GR8RAM_LCMXO2_1200HC_impl1_fpga_mapper.srr.db
BIN
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cpld/LCMXO2-1200HC/impl1/synlog/GR8RAM_LCMXO2_1200HC_impl1_fpga_mapper.szr
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cpld/LCMXO2-1200HC/impl1/synlog/GR8RAM_LCMXO2_1200HC_impl1_multi_srs_gen.srr
+27
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Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Jun 13 00:38:47 2024
###########################################################]
cpld/LCMXO2-1200HC/impl1/synlog/GR8RAM_LCMXO2_1200HC_impl1_multi_srs_gen.srr.db
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cpld/LCMXO2-1200HC/impl1/synlog/GR8RAM_LCMXO2_1200HC_impl1_premap.srr
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# Thu Jun 13 00:38:47 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
@A: MF827 |No constraint file specified.
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
@A: FX681 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":36:1:36:6|Initial value on register PS[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
syn_allowed_resources : blockrams=7 set on top level netlist GR8RAM
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
------------------------------------------------------------------------------------------------
0 - GR8RAM|RCLK 100.0 MHz 10.000 inferred Inferred_clkgroup_1 104
0 - GR8RAM|PHI0 100.0 MHz 10.000 inferred Inferred_clkgroup_0 18
================================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
------------------------------------------------------------------------------------------------
GR8RAM|RCLK 104 RCLK(port) PHI0r[4:1].C - un1_RCLK.I[0](inv)
GR8RAM|PHI0 18 PHI0(port) RAr[11:0].C PHI0r[4:1].D[0] nDoutOE.I[0](inv)
================================================================================================
@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":67:1:67:6|Found inferred clock GR8RAM|PHI0 which controls 18 sequential elements including CXXXr. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":20:16:20:21|Found inferred clock GR8RAM|RCLK which controls 104 sequential elements including nRESf. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 118 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 RCLK Unconstrained_port 104 nRESf
@KP:ckid0_1 PHI0 Unconstrained_port 14 CXXXr
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jun 13 00:38:48 2024
###########################################################]
cpld/LCMXO2-1200HC/impl1/synlog/GR8RAM_LCMXO2_1200HC_impl1_premap.srr.db
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cpld/LCMXO2-1200HC/impl1/synlog/GR8RAM_LCMXO2_1200HC_impl1_premap.szr
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cpld/LCMXO2-1200HC/impl1/synlog/GR8RAM_LCMXO2_1200HC_impl1_premap.xck
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ckid0_0:@|S:RCLK@|E:nRESf@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0
ckid0_1:@|S:PHI0@|E:CXXXr@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1
cpld/LCMXO2-1200HC/impl1/synlog/incr_compile.rpt.rptmap
+1
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@@ -0,0 +1 @@
./synwork/incr_compile.rpt,incr_compile.rpt,Incremental Compile Report
cpld/LCMXO2-1200HC/impl1/synlog/layer0.tlg.rptmap
+1
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@@ -0,0 +1 @@
./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
cpld/LCMXO2-1200HC/impl1/synlog/report/GR8RAM_LCMXO2_1200HC_impl1_compiler_notes.txt
+7
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@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":1:7:1:12|Synthesizing module GR8RAM in library work.
@N: CL201 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":49:1:49:6|Trying to extract state machine for register IS.
@N|Running in 64-bit mode
cpld/LCMXO2-1200HC/impl1/synlog/report/GR8RAM_LCMXO2_1200HC_impl1_compiler_runstatus.xml
+41
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<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
The file contains the job information from compiler to be displayed as part of the summary report.
*******************************************************************************************-->
<job_run_status name="compiler">
<report_link name="Detailed report">
<data>\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synlog\GR8RAM_LCMXO2_1200HC_impl1_compiler.srr</data>
<title>Synopsys HDL Compiler</title>
</report_link>
<job_status>
<data>Completed </data>
</job_status>
<job_info>
<info name="Notes">
<data>6</data>
<report_link name="more"><data>\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synlog\report\GR8RAM_LCMXO2_1200HC_impl1_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>0</data>
<report_link name="more"><data>\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synlog\report\GR8RAM_LCMXO2_1200HC_impl1_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
<data>0</data>
<report_link name="more"><data>\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synlog\report\GR8RAM_LCMXO2_1200HC_impl1_compiler_errors.txt</data></report_link>
</info>
<info name="CPU Time">
<data>-</data>
</info>
<info name="Real Time">
<data>00h:00m:01s</data>
</info>
<info name="Peak Memory">
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1718253526</data>
</info>
</job_info>
</job_run_status>
cpld/LCMXO2-1200HC/impl1/synlog/report/GR8RAM_LCMXO2_1200HC_impl1_compiler_warnings.txt
+2
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@@ -0,0 +1,2 @@
@W: CL169 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":27:1:27:6|Pruning unused register SetFWLoaded. Make sure that there are no unused intermediate registers.
cpld/LCMXO2-1200HC/impl1/synlog/report/GR8RAM_LCMXO2_1200HC_impl1_fpga_mapper_area_report.xml
+26
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@@ -0,0 +1,26 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
The file contains the area information from mapper to be displayed as part of the summary report.
*******************************************************************************************-->
<report_table display_priority="1" name="Area Summary">
<report_link name="Detailed report">
<data>\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synlog\report\GR8RAM_LCMXO2_1200HC_impl1_fpga_mapper_resourceusage.rpt</data>
<title>Resource Usage</title>
</report_link>
<parameter tooltip="Total Register bits used" name="Register bits">
<data>118</data>
</parameter>
<parameter tooltip="Total I/O cells used" name="I/O cells">
<data>73</data>
</parameter>
<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
<data>0</data>
</parameter>
<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
<data>0</data>
</parameter>
<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
<data>240</data>
</parameter>
</report_table>
cpld/LCMXO2-1200HC/impl1/synlog/report/GR8RAM_LCMXO2_1200HC_impl1_fpga_mapper_errors.txt
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cpld/LCMXO2-1200HC/impl1/synlog/report/GR8RAM_LCMXO2_1200HC_impl1_fpga_mapper_notes.txt
+15
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@@ -0,0 +1,15 @@
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nRAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nCAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
@N: FX493 |Applying initial value "000" on instance IS[2:0].
@N: FX493 |Applying initial value "0000" on instance PS[3:0].
@N: MO231 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":44:1:44:6|Found counter in view:work.GR8RAM(verilog) instance LS[13:0]
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
cpld/LCMXO2-1200HC/impl1/synlog/report/GR8RAM_LCMXO2_1200HC_impl1_fpga_mapper_opt_report.xml
+6
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@@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
The file contains the optimization information from mapper to be displayed as part of the summary report.
*******************************************************************************************-->
<report_table display_priority="3" name="Optimizations Summary"></report_table>

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