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https://github.com/garrettsworkshop/GR8RAM.git
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This commit is contained in:
Zane Kaminski
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PAD Specification File
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***************************
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PART TYPE: LCMXO2-640HC
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Performance Grade: 4
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PACKAGE: TQFP100
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Package Status: Final Version 1.39
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Sun Jul 14 06:18:58 2024
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Pinout by Port Name:
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+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
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| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
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+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
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| BA[0] | 74/1 | LVCMOS33_IN | PR2B | | | CLAMP:ON HYSTERESIS:SMALL |
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| BA[10] | 3/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
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| BA[1] | 78/0 | LVCMOS33_IN | PT11A | | | CLAMP:ON HYSTERESIS:SMALL |
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| BA[2] | 83/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
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| BA[3] | 84/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
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| BA[4] | 4/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
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| BA[5] | 85/0 | LVCMOS33_IN | PT9D | | | CLAMP:ON HYSTERESIS:SMALL |
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| BA[6] | 86/0 | LVCMOS33_IN | PT9C | | | CLAMP:ON HYSTERESIS:SMALL |
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| BA[7] | 87/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
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| BA[8] | 99/0 | LVCMOS33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL |
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| BA[9] | 2/3 | LVCMOS33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL |
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| BD[0] | 65/1 | LVCMOS33_BIDI | PR5A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| BD[1] | 66/1 | LVCMOS33_BIDI | PR3D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| BD[2] | 67/1 | LVCMOS33_BIDI | PR3C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| BD[3] | 68/1 | LVCMOS33_BIDI | PR3B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| BD[4] | 69/1 | LVCMOS33_BIDI | PR3A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| BD[5] | 70/1 | LVCMOS33_BIDI | PR2D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| BD[6] | 71/1 | LVCMOS33_BIDI | PR2C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| BD[7] | 75/1 | LVCMOS33_BIDI | PR2A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| DQMH | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:SLOW |
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| DQML | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
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| FCK | 96/0 | LVCMOS33_OUT | PT6D | | | DRIVE:24mA PULL:KEEPER SLEW:FAST |
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| LED | 81/0 | LVCMOS33_OUT | PT10D | | | DRIVE:24mA SLEW:SLOW |
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| MISO | 98/0 | LVCMOS33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL |
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| MOSI | 97/0 | LVCMOS33_BIDI | PT6C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| PHI0 | 17/3 | LVCMOS33_IN | PL6B | | | CLAMP:ON HYSTERESIS:SMALL |
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| RA[0] | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
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| RA[10] | 47/2 | LVCMOS33_OUT | PB14B | | | DRIVE:4mA SLEW:SLOW |
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| RA[11] | 45/2 | LVCMOS33_OUT | PB14A | | | DRIVE:4mA SLEW:SLOW |
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| RA[12] | 42/2 | LVCMOS33_OUT | PB12C | | | DRIVE:4mA SLEW:SLOW |
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| RA[1] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
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| RA[2] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
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| RA[3] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
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| RA[4] | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
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| RA[5] | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
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| RA[6] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
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| RA[7] | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
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| RA[8] | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
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| RA[9] | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW |
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| RBA[0] | 43/2 | LVCMOS33_OUT | PB12D | | | DRIVE:4mA SLEW:SLOW |
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| RBA[1] | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
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| RCKE | 40/2 | LVCMOS33_OUT | PB12A | | | DRIVE:4mA SLEW:SLOW |
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| RCLK | 39/2 | LVCMOS33_OUT | PB10D | | | DRIVE:24mA SLEW:FAST |
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| RD[0] | 25/3 | LVCMOS33_BIDI | PL7D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| RD[1] | 24/3 | LVCMOS33_BIDI | PL7C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| RD[2] | 21/3 | LVCMOS33_BIDI | PL7B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| RD[3] | 27/2 | LVCMOS33_BIDI | PB4A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| RD[4] | 28/2 | LVCMOS33_BIDI | PB4B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| RD[5] | 29/2 | LVCMOS33_BIDI | PB4C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| RD[6] | 30/2 | LVCMOS33_BIDI | PB4D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| RD[7] | 31/2 | LVCMOS33_BIDI | PB6A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| SW[1] | 64/1 | LVCMOS33_IN | PR5B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
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| SW[2] | 63/1 | LVCMOS33_IN | PR5C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
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| nCAS | 36/2 | LVCMOS33_OUT | PB10A | | | DRIVE:4mA SLEW:SLOW |
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| nDEVSEL | 16/3 | LVCMOS33_IN | PL6A | | | CLAMP:ON HYSTERESIS:SMALL |
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| nDinOE | 77/0 | LVCMOS33_OUT | PT11C | | | DRIVE:4mA SLEW:SLOW |
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| nDoutOE | 1/3 | LVCMOS33_OUT | PL2A | | | DRIVE:4mA SLEW:SLOW |
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| nFCS | 88/0 | LVCMOS33_BIDI | PT9A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
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| nIOSEL | 15/3 | LVCMOS33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL |
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| nIOSTRB | 18/3 | LVCMOS33_IN | PL6C | | | CLAMP:ON HYSTERESIS:SMALL |
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| nIRQout | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
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| nRAS | 37/2 | LVCMOS33_OUT | PB10B | | | DRIVE:4mA SLEW:SLOW |
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| nRCS | 41/2 | LVCMOS33_OUT | PB12B | | | DRIVE:4mA SLEW:SLOW |
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| nRESin | 20/3 | LVCMOS33_IN | PL7A | | | CLAMP:ON HYSTERESIS:SMALL |
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| nRESout | 7/3 | LVCMOS33_OUT | PL3A | | | DRIVE:4mA SLEW:SLOW |
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| nRWE | 35/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
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| nWE | 19/3 | LVCMOS33_IN | PL6D | | | CLAMP:ON HYSTERESIS:SMALL |
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+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
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Vccio by Bank:
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+------+-------+
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| Bank | Vccio |
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+------+-------+
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| 0 | 3.3V |
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| 1 | 3.3V |
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| 2 | 3.3V |
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| 3 | 3.3V |
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+------+-------+
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Vref by Bank:
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+------+-----+-----------------+---------+
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| Vref | Pin | Bank # / Vref # | Load(s) |
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+------+-----+-----------------+---------+
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+------+-----+-----------------+---------+
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Pinout by Pin Number:
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+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
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| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
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+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
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| 1/3 | nDoutOE | LOCATED | LVCMOS33_OUT | PL2A | | | |
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| 2/3 | BA[9] | LOCATED | LVCMOS33_IN | PL2B | | | |
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| 3/3 | BA[10] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
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| 4/3 | BA[4] | LOCATED | LVCMOS33_IN | PL2D | PCLKC3_2 | | |
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| 7/3 | nRESout | LOCATED | LVCMOS33_OUT | PL3A | | | |
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| 8/3 | unused, PULL:DOWN | | | PL3B | | | |
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| 9/3 | unused, PULL:DOWN | | | PL3C | | | |
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| 10/3 | unused, PULL:DOWN | | | PL3D | | | |
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| 12/3 | nIRQout | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
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| 13/3 | unused, PULL:DOWN | | | PL5B | PCLKC3_1 | | |
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| 14/3 | unused, PULL:DOWN | | | PL5C | | | |
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| 15/3 | nIOSEL | LOCATED | LVCMOS33_IN | PL5D | | | |
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| 16/3 | nDEVSEL | LOCATED | LVCMOS33_IN | PL6A | | | |
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| 17/3 | PHI0 | LOCATED | LVCMOS33_IN | PL6B | | | |
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| 18/3 | nIOSTRB | LOCATED | LVCMOS33_IN | PL6C | | | |
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| 19/3 | nWE | LOCATED | LVCMOS33_IN | PL6D | | | |
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| 20/3 | nRESin | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | |
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| 21/3 | RD[2] | LOCATED | LVCMOS33_BIDI | PL7B | PCLKC3_0 | | |
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| 24/3 | RD[1] | LOCATED | LVCMOS33_BIDI | PL7C | | | |
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| 25/3 | RD[0] | LOCATED | LVCMOS33_BIDI | PL7D | | | |
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| 27/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB4A | CSSPIN | | |
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| 28/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB4B | | | |
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| 29/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB4C | | | |
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| 30/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB4D | | | |
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| 31/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB6A | MCLK/CCLK | | |
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| 32/2 | DQML | LOCATED | LVCMOS33_OUT | PB6B | SO/SPISO | | |
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| 34/2 | DQMH | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | |
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| 35/2 | nRWE | LOCATED | LVCMOS33_OUT | PB6D | PCLKC2_0 | | |
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| 36/2 | nCAS | LOCATED | LVCMOS33_OUT | PB10A | | | |
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| 37/2 | nRAS | LOCATED | LVCMOS33_OUT | PB10B | | | |
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| 38/2 | unused, PULL:DOWN | | | PB10C | PCLKT2_1 | | |
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| 39/2 | RCLK | LOCATED | LVCMOS33_OUT | PB10D | PCLKC2_1 | | |
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| 40/2 | RCKE | LOCATED | LVCMOS33_OUT | PB12A | | | |
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| 41/2 | nRCS | LOCATED | LVCMOS33_OUT | PB12B | | | |
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| 42/2 | RA[12] | LOCATED | LVCMOS33_OUT | PB12C | | | |
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| 43/2 | RBA[0] | LOCATED | LVCMOS33_OUT | PB12D | | | |
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| 45/2 | RA[11] | LOCATED | LVCMOS33_OUT | PB14A | | | |
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| 47/2 | RA[10] | LOCATED | LVCMOS33_OUT | PB14B | | | |
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| 48/2 | RBA[1] | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
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| 49/2 | RA[9] | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
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| 51/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR7D | | | |
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| 52/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR7C | | | |
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| 53/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR7B | | | |
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| 54/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR7A | | | |
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| 57/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR6D | | | |
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| 58/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR6C | | | |
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| 59/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR6B | | | |
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| 60/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR6A | | | |
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| 62/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0 | | |
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| 63/1 | SW[2] | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0 | | |
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| 64/1 | SW[1] | LOCATED | LVCMOS33_IN | PR5B | | | |
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| 65/1 | BD[0] | LOCATED | LVCMOS33_BIDI | PR5A | | | |
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| 66/1 | BD[1] | LOCATED | LVCMOS33_BIDI | PR3D | | | |
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| 67/1 | BD[2] | LOCATED | LVCMOS33_BIDI | PR3C | | | |
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| 68/1 | BD[3] | LOCATED | LVCMOS33_BIDI | PR3B | | | |
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| 69/1 | BD[4] | LOCATED | LVCMOS33_BIDI | PR3A | | | |
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| 70/1 | BD[5] | LOCATED | LVCMOS33_BIDI | PR2D | | | |
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| 71/1 | BD[6] | LOCATED | LVCMOS33_BIDI | PR2C | | | |
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| 74/1 | BA[0] | LOCATED | LVCMOS33_IN | PR2B | | | |
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| 75/1 | BD[7] | LOCATED | LVCMOS33_BIDI | PR2A | | | |
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| 76/0 | unused, PULL:DOWN | | | PT11D | DONE | | |
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| 77/0 | nDinOE | LOCATED | LVCMOS33_OUT | PT11C | INITN | | |
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| 78/0 | BA[1] | LOCATED | LVCMOS33_IN | PT11A | | | |
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| 81/0 | LED | LOCATED | LVCMOS33_OUT | PT10D | PROGRAMN | | |
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| 82/0 | unused, PULL:DOWN | | | PT10C | JTAGENB | | |
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| 83/0 | BA[2] | LOCATED | LVCMOS33_IN | PT10B | | | |
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| 84/0 | BA[3] | LOCATED | LVCMOS33_IN | PT10A | | | |
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| 85/0 | BA[5] | LOCATED | LVCMOS33_IN | PT9D | SDA/PCLKC0_0 | | |
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| 86/0 | BA[6] | LOCATED | LVCMOS33_IN | PT9C | SCL/PCLKT0_0 | | |
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| 87/0 | BA[7] | LOCATED | LVCMOS33_IN | PT9B | PCLKC0_1 | | |
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| 88/0 | nFCS | LOCATED | LVCMOS33_BIDI | PT9A | PCLKT0_1 | | |
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| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
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| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
|
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| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
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| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
|
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| 96/0 | FCK | LOCATED | LVCMOS33_OUT | PT6D | | | |
|
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| 97/0 | MOSI | LOCATED | LVCMOS33_BIDI | PT6C | | | |
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| 98/0 | MISO | LOCATED | LVCMOS33_IN | PT6B | | | |
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| 99/0 | BA[8] | LOCATED | LVCMOS33_IN | PT6A | | | |
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| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
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+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
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sysCONFIG Pins:
|
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+----------+--------------------+--------------------+----------+-------------+-------------------+
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||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
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| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
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| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
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| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
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+----------+--------------------+--------------------+----------+-------------+-------------------+
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Dedicated sysCONFIG Pins:
|
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|
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|
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List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
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|
||||
LOCATE COMP "BA[0]" SITE "74";
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LOCATE COMP "BA[10]" SITE "3";
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LOCATE COMP "BA[1]" SITE "78";
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||||
LOCATE COMP "BA[2]" SITE "83";
|
||||
LOCATE COMP "BA[3]" SITE "84";
|
||||
LOCATE COMP "BA[4]" SITE "4";
|
||||
LOCATE COMP "BA[5]" SITE "85";
|
||||
LOCATE COMP "BA[6]" SITE "86";
|
||||
LOCATE COMP "BA[7]" SITE "87";
|
||||
LOCATE COMP "BA[8]" SITE "99";
|
||||
LOCATE COMP "BA[9]" SITE "2";
|
||||
LOCATE COMP "BD[0]" SITE "65";
|
||||
LOCATE COMP "BD[1]" SITE "66";
|
||||
LOCATE COMP "BD[2]" SITE "67";
|
||||
LOCATE COMP "BD[3]" SITE "68";
|
||||
LOCATE COMP "BD[4]" SITE "69";
|
||||
LOCATE COMP "BD[5]" SITE "70";
|
||||
LOCATE COMP "BD[6]" SITE "71";
|
||||
LOCATE COMP "BD[7]" SITE "75";
|
||||
LOCATE COMP "DQMH" SITE "34";
|
||||
LOCATE COMP "DQML" SITE "32";
|
||||
LOCATE COMP "FCK" SITE "96";
|
||||
LOCATE COMP "LED" SITE "81";
|
||||
LOCATE COMP "MISO" SITE "98";
|
||||
LOCATE COMP "MOSI" SITE "97";
|
||||
LOCATE COMP "PHI0" SITE "17";
|
||||
LOCATE COMP "RA[0]" SITE "54";
|
||||
LOCATE COMP "RA[10]" SITE "47";
|
||||
LOCATE COMP "RA[11]" SITE "45";
|
||||
LOCATE COMP "RA[12]" SITE "42";
|
||||
LOCATE COMP "RA[1]" SITE "59";
|
||||
LOCATE COMP "RA[2]" SITE "58";
|
||||
LOCATE COMP "RA[3]" SITE "60";
|
||||
LOCATE COMP "RA[4]" SITE "51";
|
||||
LOCATE COMP "RA[5]" SITE "52";
|
||||
LOCATE COMP "RA[6]" SITE "62";
|
||||
LOCATE COMP "RA[7]" SITE "57";
|
||||
LOCATE COMP "RA[8]" SITE "53";
|
||||
LOCATE COMP "RA[9]" SITE "49";
|
||||
LOCATE COMP "RBA[0]" SITE "43";
|
||||
LOCATE COMP "RBA[1]" SITE "48";
|
||||
LOCATE COMP "RCKE" SITE "40";
|
||||
LOCATE COMP "RCLK" SITE "39";
|
||||
LOCATE COMP "RD[0]" SITE "25";
|
||||
LOCATE COMP "RD[1]" SITE "24";
|
||||
LOCATE COMP "RD[2]" SITE "21";
|
||||
LOCATE COMP "RD[3]" SITE "27";
|
||||
LOCATE COMP "RD[4]" SITE "28";
|
||||
LOCATE COMP "RD[5]" SITE "29";
|
||||
LOCATE COMP "RD[6]" SITE "30";
|
||||
LOCATE COMP "RD[7]" SITE "31";
|
||||
LOCATE COMP "SW[1]" SITE "64";
|
||||
LOCATE COMP "SW[2]" SITE "63";
|
||||
LOCATE COMP "nCAS" SITE "36";
|
||||
LOCATE COMP "nDEVSEL" SITE "16";
|
||||
LOCATE COMP "nDinOE" SITE "77";
|
||||
LOCATE COMP "nDoutOE" SITE "1";
|
||||
LOCATE COMP "nFCS" SITE "88";
|
||||
LOCATE COMP "nIOSEL" SITE "15";
|
||||
LOCATE COMP "nIOSTRB" SITE "18";
|
||||
LOCATE COMP "nIRQout" SITE "12";
|
||||
LOCATE COMP "nRAS" SITE "37";
|
||||
LOCATE COMP "nRCS" SITE "41";
|
||||
LOCATE COMP "nRESin" SITE "20";
|
||||
LOCATE COMP "nRESout" SITE "7";
|
||||
LOCATE COMP "nRWE" SITE "35";
|
||||
LOCATE COMP "nWE" SITE "19";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sun Jul 14 06:19:01 2024
|
||||
|
||||
@@ -0,0 +1,214 @@
|
||||
|
||||
Lattice Place and Route Report for Design "GR8RAM_LCMXO2_640HC_impl1_map.ncd"
|
||||
Sun Jul 14 06:18:50 2024
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF GR8RAM_LCMXO2_640HC_impl1_map.ncd GR8RAM_LCMXO2_640HC_impl1.dir/5_1.ncd GR8RAM_LCMXO2_640HC_impl1.prf
|
||||
Preference file: GR8RAM_LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file GR8RAM_LCMXO2_640HC_impl1_map.ncd.
|
||||
Design name: GR8RAM
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 67+4(JTAG)/80 89% used
|
||||
67+4(JTAG)/79 90% bonded
|
||||
IOLOGIC 32/80 40% used
|
||||
|
||||
SLICE 189/320 59% used
|
||||
|
||||
OSC 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 585
|
||||
Number of Connections: 1624
|
||||
|
||||
Pin Constraint Summary:
|
||||
67 out of 67 pins locked (100% locked).
|
||||
|
||||
The following 1 signal is selected to use the primary clock routing resources:
|
||||
CLK (driver: OSCH_inst, clk load #: 127)
|
||||
|
||||
|
||||
The following 3 signals are selected to use the secondary clock routing resources:
|
||||
ram.RA_0_sqmuxa (driver: ram/SLICE_172, clk load #: 0, sr load #: 13, ce load #: 0)
|
||||
RegReset (driver: bi/SLICE_81, clk load #: 0, sr load #: 12, ce load #: 0)
|
||||
PHI0_c (driver: PHI0, clk load #: 5, sr load #: 0, ce load #: 0)
|
||||
|
||||
WARNING - par: Signal "PHI0_c" is selected to use Secondary clock resources. However, its driver comp "PHI0" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
.............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 80114.
|
||||
Finished Placer Phase 1. REAL time: 8 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 79942
|
||||
Finished Placer Phase 2. REAL time: 8 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 1 out of 80 (1%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "CLK" from OSC on comp "OSCH_inst" on site "OSC", clk load = 127
|
||||
SECONDARY "ram.RA_0_sqmuxa" from F1 on comp "ram/SLICE_172" on site "R6C8B", clk load = 0, ce load = 0, sr load = 13
|
||||
SECONDARY "RegReset" from Q0 on comp "bi/SLICE_81" on site "R2C9A", clk load = 0, ce load = 0, sr load = 12
|
||||
SECONDARY "PHI0_c" from comp "PHI0" on PIO site "17 (PL6B)", clk load = 5, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 1 out of 8 (12%)
|
||||
SECONDARY: 3 out of 8 (37%)
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
67 + 4(JTAG) out of 80 (88.8%) PIO sites used.
|
||||
67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used.
|
||||
Number of PIO comps: 67; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
||||
| 1 | 20 / 20 (100%) | 3.3V | - |
|
||||
| 2 | 19 / 20 ( 95%) | 3.3V | - |
|
||||
| 3 | 15 / 20 ( 75%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 7 secs
|
||||
|
||||
Dumping design to file GR8RAM_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1624 unrouted.
|
||||
Starting router resource preassignment
|
||||
|
||||
Completed router resource preassignment. Real time: 11 secs
|
||||
|
||||
Start NBR router at 06:19:02 07/14/24
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 06:19:02 07/14/24
|
||||
|
||||
Start NBR section for initial routing at 06:19:02 07/14/24
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 1279(78.76%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 8.730ns/0.000ns; real time: 12 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 1276(78.57%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 8.874ns/0.000ns; real time: 12 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 1274(78.45%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 9.028ns/0.000ns; real time: 12 secs
|
||||
Level 4, iteration 1
|
||||
12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 8.306ns/0.000ns; real time: 12 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 06:19:02 07/14/24
|
||||
Level 4, iteration 1
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 8.306ns/0.000ns; real time: 12 secs
|
||||
Level 4, iteration 2
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.674ns/0.000ns; real time: 12 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.674ns/0.000ns; real time: 12 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 06:19:02 07/14/24
|
||||
|
||||
Start NBR section for re-routing at 06:19:02 07/14/24
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.674ns/0.000ns; real time: 12 secs
|
||||
|
||||
Start NBR section for post-routing at 06:19:02 07/14/24
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 7.674ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 12 secs
|
||||
Total REAL time: 13 secs
|
||||
Completely routed.
|
||||
End of route. 1624 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file GR8RAM_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 7.674
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.260
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 12 secs
|
||||
Total REAL time to completion: 13 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
@@ -0,0 +1,44 @@
|
||||
[ActiveSupport PAR]
|
||||
; Global primary clocks
|
||||
GLOBAL_PRIMARY_USED = 1;
|
||||
; Global primary clock #0
|
||||
GLOBAL_PRIMARY_0_SIGNALNAME = CLK;
|
||||
GLOBAL_PRIMARY_0_DRIVERTYPE = OSC;
|
||||
GLOBAL_PRIMARY_0_LOADNUM = 127;
|
||||
; # of global secondary clocks
|
||||
GLOBAL_SECONDARY_USED = 3;
|
||||
; Global secondary clock #0
|
||||
GLOBAL_SECONDARY_0_SIGNALNAME = ram.RA_0_sqmuxa;
|
||||
GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE;
|
||||
GLOBAL_SECONDARY_0_LOADNUM = 13;
|
||||
GLOBAL_SECONDARY_0_SIGTYPE = RST;
|
||||
; Global secondary clock #1
|
||||
GLOBAL_SECONDARY_1_SIGNALNAME = PHI0_c;
|
||||
GLOBAL_SECONDARY_1_DRIVERTYPE = PIO;
|
||||
GLOBAL_SECONDARY_1_LOADNUM = 8;
|
||||
GLOBAL_SECONDARY_1_SIGTYPE = CLK;
|
||||
; Global secondary clock #2
|
||||
GLOBAL_SECONDARY_2_SIGNALNAME = RegReset;
|
||||
GLOBAL_SECONDARY_2_DRIVERTYPE = SLICE;
|
||||
GLOBAL_SECONDARY_2_LOADNUM = 24;
|
||||
GLOBAL_SECONDARY_2_SIGTYPE = RST;
|
||||
; I/O Bank 0 Usage
|
||||
BANK_0_USED = 13;
|
||||
BANK_0_AVAIL = 19;
|
||||
BANK_0_VCCIO = 3.3V;
|
||||
BANK_0_VREF1 = NA;
|
||||
; I/O Bank 1 Usage
|
||||
BANK_1_USED = 20;
|
||||
BANK_1_AVAIL = 20;
|
||||
BANK_1_VCCIO = 3.3V;
|
||||
BANK_1_VREF1 = NA;
|
||||
; I/O Bank 2 Usage
|
||||
BANK_2_USED = 19;
|
||||
BANK_2_AVAIL = 20;
|
||||
BANK_2_VCCIO = 3.3V;
|
||||
BANK_2_VREF1 = NA;
|
||||
; I/O Bank 3 Usage
|
||||
BANK_3_USED = 15;
|
||||
BANK_3_AVAIL = 20;
|
||||
BANK_3_VCCIO = 3.3V;
|
||||
BANK_3_VREF1 = NA;
|
||||
@@ -0,0 +1,28 @@
|
||||
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sun Jul 14 06:18:50 2024
|
||||
|
||||
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f GR8RAM_LCMXO2_640HC_impl1.p2t
|
||||
GR8RAM_LCMXO2_640HC_impl1_map.ncd GR8RAM_LCMXO2_640HC_impl1.dir
|
||||
GR8RAM_LCMXO2_640HC_impl1.prf -gui -msgset
|
||||
//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
||||
Preference file: GR8RAM_LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 7.674 0 0.260 0 13 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 13 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
Reference in New Issue
Block a user