mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-12-13 15:30:05 +00:00
Migrate to KiCAD 6
This commit is contained in:
parent
abfe1cc597
commit
d8c5413d3c
1
.gitignore
vendored
1
.gitignore
vendored
@ -14,6 +14,7 @@ _autosave-*
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*-save.pro
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*-save.kicad_pcb
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fp-info-cache
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GR8RAM-backups/*
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# Netlist files (exported from Eeschema)
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*.net
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||||
|
2750
Docs.kicad_sch
Normal file
2750
Docs.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
4345
Documentation/Assembly.html
Normal file
4345
Documentation/Assembly.html
Normal file
File diff suppressed because one or more lines are too long
131922
GR8RAM.kicad_pcb
131922
GR8RAM.kicad_pcb
File diff suppressed because it is too large
Load Diff
75
GR8RAM.kicad_prl
Normal file
75
GR8RAM.kicad_prl
Normal file
@ -0,0 +1,75 @@
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{
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"board": {
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"active_layer": 0,
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"active_layer_preset": "All Layers",
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"auto_track_width": true,
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"hidden_nets": [],
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"high_contrast_mode": 0,
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||||
"net_color_mode": 1,
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||||
"opacity": {
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||||
"pads": 1.0,
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||||
"tracks": 1.0,
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"vias": 1.0,
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"zones": 0.6
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},
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"ratsnest_display_mode": 0,
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"selection_filter": {
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"dimensions": true,
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"footprints": true,
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"graphics": true,
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"keepouts": true,
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"lockedItems": true,
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"otherItems": true,
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"pads": true,
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"text": true,
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"tracks": true,
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"vias": true,
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||||
"zones": true
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},
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"visible_items": [
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0,
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1,
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2,
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||||
3,
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4,
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||||
5,
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||||
8,
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9,
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||||
10,
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11,
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12,
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13,
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||||
14,
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||||
15,
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16,
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17,
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18,
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||||
19,
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||||
20,
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||||
21,
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||||
22,
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||||
23,
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||||
24,
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25,
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26,
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27,
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28,
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29,
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30,
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32,
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33,
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34,
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35,
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36
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],
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"visible_layers": "fffffff_ffffffff",
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"zone_display_mode": 0
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},
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"meta": {
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"filename": "GR8RAM.kicad_prl",
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"version": 3
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},
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"project": {
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"files": []
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}
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}
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461
GR8RAM.kicad_pro
Normal file
461
GR8RAM.kicad_pro
Normal file
@ -0,0 +1,461 @@
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{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.15,
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"copper_line_width": 0.15,
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||||
"copper_text_italic": false,
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||||
"copper_text_size_h": 1.5,
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||||
"copper_text_size_v": 1.5,
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||||
"copper_text_thickness": 0.3,
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||||
"copper_text_upright": false,
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||||
"courtyard_line_width": 0.049999999999999996,
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||||
"dimension_precision": 4,
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||||
"dimension_units": 3,
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||||
"dimensions": {
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||||
"arrow_length": 1270000,
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"extension_offset": 500000,
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||||
"keep_text_aligned": true,
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||||
"suppress_zeroes": false,
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||||
"text_position": 0,
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||||
"units_format": 1
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||||
},
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||||
"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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||||
"fab_text_size_h": 1.0,
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||||
"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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||||
"fab_text_upright": false,
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||||
"other_line_width": 0.09999999999999999,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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||||
"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 0.0,
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||||
"height": 0.4,
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"width": 0.65
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},
|
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"silk_line_width": 0.15,
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||||
"silk_text_italic": false,
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||||
"silk_text_size_h": 1.0,
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||||
"silk_text_size_v": 1.0,
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||||
"silk_text_thickness": 0.15,
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||||
"silk_text_upright": false,
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||||
"zones": {
|
||||
"45_degree_only": false,
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||||
"min_clearance": 0.15239999999999998
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}
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},
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"diff_pair_dimensions": [],
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||||
"drc_exclusions": [],
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"meta": {
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||||
"filename": "board_design_settings.json",
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"version": 2
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||||
},
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"rule_severities": {
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"annular_width": "error",
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||||
"clearance": "error",
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"copper_edge_clearance": "error",
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"courtyards_overlap": "error",
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||||
"diff_pair_gap_out_of_range": "error",
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||||
"diff_pair_uncoupled_length_too_long": "error",
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||||
"drill_out_of_range": "error",
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||||
"duplicate_footprints": "warning",
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||||
"extra_footprint": "warning",
|
||||
"footprint_type_mismatch": "error",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
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||||
"item_on_disabled_layer": "error",
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||||
"items_not_allowed": "error",
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||||
"length_out_of_range": "error",
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||||
"malformed_courtyard": "error",
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||||
"microvia_drill_out_of_range": "error",
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||||
"missing_courtyard": "ignore",
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||||
"missing_footprint": "warning",
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||||
"net_conflict": "warning",
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||||
"npth_inside_courtyard": "ignore",
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||||
"padstack": "error",
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||||
"pth_inside_courtyard": "ignore",
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||||
"shorting_items": "error",
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"silk_over_copper": "warning",
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||||
"silk_overlap": "warning",
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||||
"skew_out_of_range": "error",
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||||
"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
|
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"track_dangling": "warning",
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||||
"track_width": "error",
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"tracks_crossing": "error",
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||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zone_has_empty_net": "error",
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||||
"zones_intersect": "error"
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},
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||||
"rule_severitieslegacy_courtyards_overlap": true,
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||||
"rule_severitieslegacy_no_courtyard_defined": false,
|
||||
"rules": {
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_copper_edge_clearance": 0.075,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.19999999999999998,
|
||||
"min_track_width": 0.15,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.5,
|
||||
"use_height_for_length_calcs": true
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||||
},
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||||
"track_widths": [
|
||||
0.0,
|
||||
0.2,
|
||||
0.25,
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||||
0.3,
|
||||
0.35,
|
||||
0.4,
|
||||
0.45,
|
||||
0.5,
|
||||
0.6,
|
||||
0.762,
|
||||
0.8,
|
||||
1.0,
|
||||
1.27,
|
||||
1.524
|
||||
],
|
||||
"via_dimensions": [
|
||||
{
|
||||
"diameter": 0.0,
|
||||
"drill": 0.0
|
||||
},
|
||||
{
|
||||
"diameter": 0.6,
|
||||
"drill": 0.3
|
||||
},
|
||||
{
|
||||
"diameter": 0.8,
|
||||
"drill": 0.4
|
||||
},
|
||||
{
|
||||
"diameter": 1.0,
|
||||
"drill": 0.5
|
||||
},
|
||||
{
|
||||
"diameter": 1.524,
|
||||
"drill": 0.762
|
||||
}
|
||||
],
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_label_syntax": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "GR8RAM.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.15,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.15,
|
||||
"via_diameter": 0.5,
|
||||
"via_drill": 0.2,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "GR8RAM.net",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.25,
|
||||
"pin_symbol_size": 0.0,
|
||||
"text_offset_ratio": 0.08
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "Pcbnew",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"fix_passive_vals": false,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 0,
|
||||
"workbook_filename": ""
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"a29f8df0-3fae-4edf-8d9c-bd5a875b13e3",
|
||||
""
|
||||
],
|
||||
[
|
||||
"00000000-0000-0000-0000-00005d4d21a0",
|
||||
"Docs"
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
8028
GR8RAM.kicad_sch
Normal file
8028
GR8RAM.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
269
GR8RAM.pro
269
GR8RAM.pro
@ -1,269 +0,0 @@
|
||||
update=Tuesday, April 20, 2021 at 01:48:51 AM
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=GR8RAM.net
|
||||
CopperLayerCount=4
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.15
|
||||
MinViaDiameter=0.5
|
||||
MinViaDrill=0.2
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.15
|
||||
TrackWidth2=0.2
|
||||
TrackWidth3=0.25
|
||||
TrackWidth4=0.3
|
||||
TrackWidth5=0.35
|
||||
TrackWidth6=0.4
|
||||
TrackWidth7=0.45
|
||||
TrackWidth8=0.5
|
||||
TrackWidth9=0.6
|
||||
TrackWidth10=0.762
|
||||
TrackWidth11=0.8
|
||||
TrackWidth12=1
|
||||
TrackWidth13=1.27
|
||||
TrackWidth14=1.524
|
||||
ViaDiameter1=0.5
|
||||
ViaDrill1=0.2
|
||||
ViaDiameter2=0.6
|
||||
ViaDrill2=0.3
|
||||
ViaDiameter3=0.8
|
||||
ViaDrill3=0.4
|
||||
ViaDiameter4=1
|
||||
ViaDrill4=0.5
|
||||
ViaDiameter5=1.524
|
||||
ViaDrill5=0.762
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.15
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.15
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.15
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.07619999999999999
|
||||
SolderMaskMinWidth=0.127
|
||||
SolderPasteClearance=-0.03809999999999999
|
||||
SolderPasteRatio=0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=1
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=1
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.15
|
||||
TrackWidth=0.15
|
||||
ViaDiameter=0.5
|
||||
ViaDrill=0.2
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
2707
GR8RAM.sch
2707
GR8RAM.sch
File diff suppressed because it is too large
Load Diff
1999
GR8RAM.xml
1999
GR8RAM.xml
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user