Apple-2-HW/GR8RAM
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Added separate configuration section

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Zane Kaminski 2020-02-26 03:31:20 -05:00
parent 490fcfb8e7
commit fe0a092924
1 changed files with 5 additions and 2 deletions
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cpld/GR8RAM.v
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@ -5,8 +5,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
/* Clock, Reset, Mode */ /* Clock, Reset, Mode */
input C7M, C7M_2, Q3, PHI0in, PHI1in; // Clock inputs input C7M, C7M_2, Q3, PHI0in, PHI1in; // Clock inputs
input nRES, Mode; input nRES;
input Mode;
/* PHI1 Delay */ /* PHI1 Delay */
wire [8:0] PHI1b; wire [8:0] PHI1b;
@ -88,6 +87,9 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
reg DBEN = 0; // Data bus driver gating reg DBEN = 0; // Data bus driver gating
reg CSEN = 0; // ROM CS enable gating reg CSEN = 0; // ROM CS enable gating
/* Configuration */
input Mode;
// Apple II Bus Compatibiltiy Rules: // Apple II Bus Compatibiltiy Rules:
// Synchronize to PHI0 or PHI1. (PHI1 here) // Synchronize to PHI0 or PHI1. (PHI1 here)
// PHI1's edge may be -20ns,+10ns relative to C7M. // PHI1's edge may be -20ns,+10ns relative to C7M.
@ -148,6 +150,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
end end
end end
/* Set registers */
always @(negedge C7M, negedge nRES) begin always @(negedge C7M, negedge nRES) begin
if (~nRES) begin if (~nRES) begin
Addr <= 0; Addr <= 0;