6 Commits

Author	SHA1	Message	Date
Zane Kaminski	5437b524cc	Register Apple address bus on PHI0 rising edge	2021-04-21 20:06:56 -04:00
Zane Kaminski	3e06d30382	Fixed bugs in new PLD stuff	2019-10-20 22:41:24 -04:00
Zane Kaminski	79dd794f45	New PLD revision ... For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.	2019-10-18 15:07:38 -04:00
Zane Kaminski	2382fdfda6	Made AddrH high bit variable with mode input	2019-09-07 21:16:23 -04:00
Zane Kaminski	b0a001aa58	Clarified assignments	2019-09-06 17:26:42 -04:00
Zane Kaminski	47a4c012d7	Pipelined addition	2019-09-04 21:45:56 -04:00