Change ~ to ! where appropriate in GR8RAM.v

Recompile
Untrack and delete .qws files
2024-02-16 20:54:16 -05:00 · 2024-02-16 20:48:50 -05:00 · 2024-02-16 20:46:40 -05:00 · 2024-02-16 20:43:29 -05:00 · 2024-02-16 20:41:52 -05:00 · 2024-02-16 20:41:33 -05:00
60 changed files with 249 additions and 10384 deletions
--- a/.gitignore
+++ b/.gitignore
@ -24,8 +24,7 @@ GR8RAM-backups/*
 *.ses

 *.DS_Store
-cpld/db/GR8RAM.db_info
-cpld/db/GR8RAM.tmw_info
-cpld/GR8RAM.qws
-Documentation/~$4205AManual.docx
 *.kicad_prl
+cpld/db/*
+cpld/incremental_db/*
+cpld/GR8RAM.qws
--- a/cpld/GR8RAM.qpf
+++ b/cpld/GR8RAM.qpf
@ -1,6 +1,6 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 2022  Intel Corporation. All rights reserved.
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
 # Your use of Intel Corporation's design tools, logic functions 
 # and other software and tools, and any partner logic 
 # functions, and any output files from any of the foregoing 
@ -18,13 +18,13 @@
 # -------------------------------------------------------------------------- #
 #
 # Quartus Prime
-# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
-# Date created = 11:15:44  February 28, 2023
+# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+# Date created = 20:42:53  February 16, 2024
 #
 # -------------------------------------------------------------------------- #

-QUARTUS_VERSION = "22.1"
-DATE = "11:15:44  February 28, 2023"
+QUARTUS_VERSION = "19.1"
+DATE = "20:42:53  February 16, 2024"

 # Revisions

--- a/cpld/GR8RAM.qsf
+++ b/cpld/GR8RAM.qsf
@ -1,24 +1,25 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
 # functions, and any output files from any of the foregoing 
 # (including device programming or simulation files), and any 
 # associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
 #
 # -------------------------------------------------------------------------- #
 #
-# Quartus II 32-bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-# Date created = 13:41:40  March 15, 2021
+# Quartus Prime
+# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+# Date created = 20:36:06  February 16, 2024
 #
 # -------------------------------------------------------------------------- #
 #
@ -30,7 +31,7 @@
 #		assignment_defaults.qdf
 #
 # 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
+#    file is updated automatically by the Quartus Prime software
 #    and any changes you make may be lost or overwritten.
 #
 # -------------------------------------------------------------------------- #
@ -39,9 +40,11 @@
 set_global_assignment -name FAMILY "MAX II"
 set_global_assignment -name DEVICE EPM240T100C5
 set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:15:44  FEBRUARY 28, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:36:06  FEBRUARY 16, 2024"
+set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
+set_global_assignment -name SDC_FILE GR8RAM.sdc
+set_global_assignment -name VERILOG_FILE GR8RAM.v
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@ -50,14 +53,7 @@ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
 set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
-set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
-set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/questa -section_id eda_simulation
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+
 set_location_assignment PIN_2 -to RA[5]
 set_location_assignment PIN_3 -to RA[6]
 set_location_assignment PIN_4 -to RA[3]
@ -253,5 +249,4 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD
 set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SD
 set_instance_assignment -name SLOW_SLEW_RATE ON -to SD
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD
-set_global_assignment -name SDC_FILE GR8RAM.sdc
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD
--- a/cpld/GR8RAM.v
+++ b/cpld/GR8RAM.v
@ -24,7 +24,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 	reg [1:0] SetFWr;
 	reg SetFWLoaded = 0;
 	always @(posedge C25M) begin
-		if (~SetFWLoaded) begin
+		if (!SetFWLoaded) begin
 			SetFWLoaded <= 1;
 			SetFWr[1:0] <= SetFW[1:0];
 		end
@ -35,7 +35,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,

 	/* State counter from PHI0 rising edge */
 	reg [3:0] PS = 0;
-	wire PSStart = PS==0 && PHI0r1 && ~PHI0r2;
+	wire PSStart = PS==0 && PHI0r1 && !PHI0r2;
 	always @(posedge C25M) begin
 		if (PSStart) PS <= 1;
 		else if (PS==0) PS <= 0;
@ -74,43 +74,43 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 	end

 	/* Apple select signals */
-	wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11]));
+	wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (!RAr[11]));
 	wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
 	wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
 	wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
-	wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]);
+	wire RAMSpecSEL = RAMRegSpecSEL && (!SetEN24bit || SetEN16MB || !Addr[23]);
 	wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
 	wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
 	wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
-	wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL;
-	wire RAMRegSEL = ~nDEVSEL && RAMRegSpecSEL;
-	wire RAMSEL = ~nDEVSEL && RAMSpecSEL;
-	wire RAMWR = RAMSEL && ~nWEr;
-	wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL;
-	wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL;
-	wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL;
+	wire BankSEL = REGEN && !nDEVSEL && BankSpecSEL;
+	wire RAMRegSEL = !nDEVSEL && RAMRegSpecSEL;
+	wire RAMSEL = !nDEVSEL && RAMSpecSEL;
+	wire RAMWR = RAMSEL && !nWEr;
+	wire AddrHSEL = REGEN && !nDEVSEL && AddrHSpecSEL;
+	wire AddrMSEL = REGEN && !nDEVSEL && AddrMSpecSEL;
+	wire AddrLSEL = REGEN && !nDEVSEL && AddrLSpecSEL;
 	
 	/* IOROMEN and REGEN control */
 	reg IOROMEN = 0;
 	reg REGEN = 0;
 	reg nIOSTRBr;
-	wire IOROMRES = RAr[10:0]==11'h7FF && ~nIOSTRB && ~nIOSTRBr;
+	wire IOROMRES = RAr[10:0]==11'h7FF && !nIOSTRB && !nIOSTRBr;
 	always @(posedge C25M, negedge nRESr) begin
-		if (~nRESr) REGEN <= 0;
-		else if (PS==8 && ~nIOSEL) REGEN <= 1;
+		if (!nRESr) REGEN <= 0;
+		else if (PS==8 && !nIOSEL) REGEN <= 1;
 	end
 	always @(posedge C25M) begin
 		nIOSTRBr <= nIOSTRB;
-		if (~nRESr) IOROMEN <= 0;
+		if (!nRESr) IOROMEN <= 0;
 		else if (PS==8 && IOROMRES) IOROMEN <= 0;
-		else if (PS==8 && ~nIOSEL) IOROMEN <= 1;
+		else if (PS==8 && !nIOSEL) IOROMEN <= 1;
 	end

 	/* Apple data bus */
 	inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
 	reg [7:0] RDD;
-	output RDdir = ~(PHI0r2 && nWE && PHI0 &&
-		(~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));
+	output RDdir = !(PHI0r2 && nWE && PHI0 &&
+		(!nDEVSEL || !nIOSEL || (!nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));

 	/* Slinky address registers */
 	reg [23:0] Addr = 0;
@ -118,7 +118,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 	reg AddrIncM = 0;
 	reg AddrIncH = 0;
 	always @(posedge C25M, negedge nRESr) begin
-		if (~nRESr) begin
+		if (!nRESr) begin
 			Addr[23:0] <= 24'h000000;
 			AddrIncL <= 0;
 			AddrIncM <= 0;
@ -127,23 +127,23 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 			if (PS==8 && RAMRegSEL) AddrIncL <= 1;
 			else AddrIncL <= 0;

-			if (PS==8 && AddrLSEL && ~nWEr) begin
+			if (PS==8 && AddrLSEL && !nWEr) begin
 				Addr[7:0] <= RD[7:0];
-				AddrIncM <= Addr[7] && ~RD[7];
+				AddrIncM <= Addr[7] && !RD[7];
 			end else if (AddrIncL) begin
 				Addr[7:0] <= Addr[7:0]+1;
 				AddrIncM <= Addr[7:0]==8'hFF;
 			end else AddrIncM <= 0;

-			if (PS==8 && AddrMSEL && ~nWEr) begin
+			if (PS==8 && AddrMSEL && !nWEr) begin
 				Addr[15:8] <= RD[7:0];
-				AddrIncH <= Addr[15] && ~RD[7];
+				AddrIncH <= Addr[15] && !RD[7];
 			end else if (AddrIncM) begin
 				Addr[15:8] <= Addr[15:8]+1;
 				AddrIncH <= Addr[15:8]==8'hFF;
 			end else AddrIncH <= 0;

-			if (PS==8 && AddrHSEL && ~nWEr) begin
+			if (PS==8 && AddrHSEL && !nWEr) begin
 				Addr[23:16] <= RD[7:0];
 			end else if (AddrIncH) begin
 				Addr[23:16] <= Addr[23:16]+1;
@ -154,14 +154,14 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 	/* ROM bank register */
 	reg Bank = 0;
 	always @(posedge C25M, negedge nRESr) begin
-		if (~nRESr) Bank <= 0;
-		else if (PS==8 && BankSEL && ~nWEr) begin
+		if (!nRESr) Bank <= 0;
+		else if (PS==8 && BankSEL && !nWEr) begin
 			Bank <= RD[0];
 		end
 	end

 	/* SPI flash control signals */
-	output nFCS = FCKOE ? ~FCS : 1'bZ;
+	output nFCS = FCKOE ? !FCS : 1'bZ;
 	reg FCS = 0;
 	output FCK = FCKOE ? FCKout : 1'bZ;
 	reg FCKOE = 0;
@ -174,35 +174,35 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 			0: begin // NOP CKE
 				FCKout <= 1'b1;
 			end 1: begin // ACT
-				FCKout <= ~(IS==5 || IS==6);
+				FCKout <= !(IS==5 || IS==6);
 			end 2: begin // RD
 				FCKout <= 1'b1;
 			end 3: begin // NOP CKE
-				FCKout <= ~(IS==5 || IS==6);
+				FCKout <= !(IS==5 || IS==6);
 			end 4: begin // NOP CKE
 				FCKout <= 1'b1;
 			end 5: begin // NOP CKE
-				FCKout <= ~(IS==5 || IS==6);
+				FCKout <= !(IS==5 || IS==6);
 			end 6: begin // NOP CKE
 				FCKout <= 1'b1;
 			end 7: begin // NOP CKE
-				FCKout <= ~(IS==5 || IS==6);
+				FCKout <= !(IS==5 || IS==6);
 			end 8: begin // WR AP
 				FCKout <= 1'b1;
 			end 9: begin // NOP CKE
-				FCKout <= ~(IS==5);
+				FCKout <= !(IS==5);
 			end 10: begin // PC all
 				FCKout <= 1'b1;
 			end 11: begin // AREF
-				FCKout <= ~(IS==5);
+				FCKout <= !(IS==5);
 			end 12: begin // NOP CKE
 				FCKout <= 1'b1;
 			end 13: begin // NOP CKE
-				FCKout <= ~(IS==5);
+				FCKout <= !(IS==5);
 			end 14: begin // NOP CKE
 				FCKout <= 1'b1;
 			end 15: begin // NOP CKE
-				FCKout <= ~(IS==5);
+				FCKout <= !(IS==5);
 			end
 		endcase
 		FCS <= IS==4 || IS==5 || IS==6;
@ -352,14 +352,14 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 				SDOE <= 0;
 			end 1: begin // ACT CKE / NOP CKD (ACT)
 				RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
-				nRCS <= ~(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
+				nRCS <= !(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
 				nRAS <= 0;
 				nCAS <= 1;
 				nSWE <= 1;
 				SDOE <= 0;
 			end 2: begin // RD CKE / NOP CKD (RD)
 				RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
-				nRCS <= ~(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
+				nRCS <= !(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
 				nRAS <= 1;
 				nCAS <= 0;
 				nSWE <= 1;
@ -401,7 +401,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 				SDOE <= 0;
 			end 8: begin // WR AP CKE / NOP CKD (WR AP)
 				RCKE <= IS==6 || (RAMWR && IS==7);
-				nRCS <= ~(IS==6 || (RAMWR && IS==7));
+				nRCS <= !(IS==6 || (RAMWR && IS==7));
 				nRAS <= 1;
 				nCAS <= 0;
 				nSWE <= 0;
@ -422,10 +422,10 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 				SDOE <= 0;
 			end 11: begin // LDM CKE / AREF CKE / NOP CKD
 				RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
-				nRCS <= ~(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
+				nRCS <= !(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
 				nRAS <= 0;
 				nCAS <= 0;
-				nSWE <= ~(IS==1);
+				nSWE <= !(IS==1);
 				SDOE <= 0;
 			end default: begin // NOP CKD
 				RCKE <= 0;
@ -469,12 +469,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
 					SA[12:0] <= { 4'b0011, Addr[9:1] };
 					DQML <= Addr[0];
-					DQMH <= ~Addr[0];
+					DQMH <= !Addr[0];
 				end else begin
 					SBA[1:0] <= 2'b10;
 					SA[12:0] <= { 4'b0011, RAr[9:1]};
 					DQML <= RAr[0];
-					DQMH <= ~RAr[0];
+					DQMH <= !RAr[0];
 				end
 			end 3: begin // NOP CKE
 				DQML <= 1'b1;
@ -506,12 +506,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 					SBA[1:0] <= 2'b10;
 					SA[12:0] <= { 4'b0011, LS[9:1] };
 					DQML <= LS[0];
-					DQMH <= ~LS[0];
+					DQMH <= !LS[0];
 				end else begin
 					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
 					SA[12:0] <= { 4'b0011, Addr[9:1] };
 					DQML <= Addr[0];
-					DQMH <= ~Addr[0];
+					DQMH <= !Addr[0];
 				end
 			end 9: begin // NOP CKE
 				DQML <= 1'b1;
--- a/cpld/db/.cmp.kpt
+++ b/cpld/db/.cmp.kpt
--- a/cpld/db/GR8RAM.(0).cnf.cdb
+++ b/cpld/db/GR8RAM.(0).cnf.cdb
--- a/cpld/db/GR8RAM.(0).cnf.hdb
+++ b/cpld/db/GR8RAM.(0).cnf.hdb
--- a/cpld/db/GR8RAM.asm.qmsg
+++ b/cpld/db/GR8RAM.asm.qmsg
@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677601285636 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677601285638 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 28 11:21:25 2023 " "Processing started: Tue Feb 28 11:21:25 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677601285638 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1677601285638 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1677601285639 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1677601285947 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1677601286047 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1677601286058 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13100 " "Peak virtual memory: 13100 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601286355 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:26 2023 " "Processing ended: Tue Feb 28 11:21:26 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601286355 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601286355 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601286355 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1677601286355 ""}
--- a/cpld/db/GR8RAM.asm.rdb
+++ b/cpld/db/GR8RAM.asm.rdb
--- a/cpld/db/GR8RAM.asm_labs.ddb
+++ b/cpld/db/GR8RAM.asm_labs.ddb
--- a/cpld/db/GR8RAM.cmp.cdb
+++ b/cpld/db/GR8RAM.cmp.cdb
--- a/cpld/db/GR8RAM.cmp.hdb
+++ b/cpld/db/GR8RAM.cmp.hdb
--- a/cpld/db/GR8RAM.cmp.idb
+++ b/cpld/db/GR8RAM.cmp.idb
--- a/cpld/db/GR8RAM.cmp.logdb
+++ b/cpld/db/GR8RAM.cmp.logdb
@ -1 +0,0 @@
-v1
--- a/cpld/db/GR8RAM.cmp.rdb
+++ b/cpld/db/GR8RAM.cmp.rdb
--- a/cpld/db/GR8RAM.cmp0.ddb
+++ b/cpld/db/GR8RAM.cmp0.ddb
--- a/cpld/db/GR8RAM.eda.qmsg
+++ b/cpld/db/GR8RAM.eda.qmsg
@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677601290645 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677601290647 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 28 11:21:30 2023 " "Processing started: Tue Feb 28 11:21:30 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677601290647 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1677601290647 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1677601290647 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1677601291072 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "GR8RAM.vo /Repos2/GR8RAM/cpld2/simulation/questa/ simulation " "Generated file GR8RAM.vo in folder \"/Repos2/GR8RAM/cpld2/simulation/questa/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1677601291254 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13024 " "Peak virtual memory: 13024 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601291299 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:31 2023 " "Processing ended: Tue Feb 28 11:21:31 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601291299 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601291299 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601291299 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1677601291299 ""}
--- a/cpld/db/GR8RAM.fit.qmsg
+++ b/cpld/db/GR8RAM.fit.qmsg
@ -1,44 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1677601279685 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1677601279686 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1677601279701 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1677601279826 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1677601279827 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1677601280022 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1677601280063 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1677601280624 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 80 " "No exact pin location assignment(s) for 1 pins of 80 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1677601280753 ""}
-{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1677601280874 ""}
-{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1677601280923 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1677601280925 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1677601280925 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000         C25M " "  40.000         C25M" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1677601280925 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000         PHI0 " " 978.000         PHI0" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1677601280925 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1677601280925 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1677601280945 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1677601280946 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1677601280959 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1677601280992 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1677601280992 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 10 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1677601280992 ""}  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 9 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1677601280992 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/22.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/22.1std/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/intelfpga_lite/22.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/22.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 9 -1 0 } } { "temporary_test_loc" "" { Generic "//mac/iCloud/Repos2/GR8RAM/cpld2/" { { 0 { 0 ""} 0 418 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1677601280992 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 94 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1677601280993 ""}  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 16 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1677601280993 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1677601280994 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1677601281004 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1677601281114 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1677601281203 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1677601281204 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1677601281205 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1677601281205 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 1 0 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 1 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1677601281234 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1677601281234 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1677601281234 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1677601281236 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 41 1 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used --  1 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1677601281236 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1677601281236 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1677601281236 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601281325 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1677601281341 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1677601281559 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601281888 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1677601281913 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1677601282469 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601282469 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1677601282537 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "30 " "Router estimated average interconnect usage is 30% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "30 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "//mac/iCloud/Repos2/GR8RAM/cpld2/" { { 1 { 0 "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1677601282887 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1677601282887 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1677601282982 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1677601282982 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1677601282982 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601282986 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1677601283019 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601283056 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1677601283164 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1677601283280 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13746 " "Peak virtual memory: 13746 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601283368 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:23 2023 " "Processing ended: Tue Feb 28 11:21:23 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601283368 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601283368 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601283368 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1677601283368 ""}
--- a/cpld/db/GR8RAM.hier_info
+++ b/cpld/db/GR8RAM.hier_info
@ -1,220 +0,0 @@
-|GR8RAM
-C25M => SA[0]~reg0.CLK
-C25M => SA[1]~reg0.CLK
-C25M => SA[2]~reg0.CLK
-C25M => SA[3]~reg0.CLK
-C25M => SA[4]~reg0.CLK
-C25M => SA[5]~reg0.CLK
-C25M => SA[6]~reg0.CLK
-C25M => SA[7]~reg0.CLK
-C25M => SA[8]~reg0.CLK
-C25M => SA[9]~reg0.CLK
-C25M => SA[10]~reg0.CLK
-C25M => SA[11]~reg0.CLK
-C25M => SA[12]~reg0.CLK
-C25M => SBA[0]~reg0.CLK
-C25M => SBA[1]~reg0.CLK
-C25M => DQMH~reg0.CLK
-C25M => DQML~reg0.CLK
-C25M => SDOE.CLK
-C25M => nSWE~reg0.CLK
-C25M => nCAS~reg0.CLK
-C25M => nRAS~reg0.CLK
-C25M => nRCS~reg0.CLK
-C25M => RCKE~reg0.CLK
-C25M => WRD[0].CLK
-C25M => WRD[1].CLK
-C25M => WRD[2].CLK
-C25M => WRD[3].CLK
-C25M => WRD[4].CLK
-C25M => WRD[5].CLK
-C25M => WRD[6].CLK
-C25M => WRD[7].CLK
-C25M => MOSIout.CLK
-C25M => FCKOE.CLK
-C25M => MOSIOE.CLK
-C25M => FCS.CLK
-C25M => FCKout.CLK
-C25M => Bank.CLK
-C25M => AddrIncH.CLK
-C25M => AddrIncM.CLK
-C25M => AddrIncL.CLK
-C25M => Addr[0].CLK
-C25M => Addr[1].CLK
-C25M => Addr[2].CLK
-C25M => Addr[3].CLK
-C25M => Addr[4].CLK
-C25M => Addr[5].CLK
-C25M => Addr[6].CLK
-C25M => Addr[7].CLK
-C25M => Addr[8].CLK
-C25M => Addr[9].CLK
-C25M => Addr[10].CLK
-C25M => Addr[11].CLK
-C25M => Addr[12].CLK
-C25M => Addr[13].CLK
-C25M => Addr[14].CLK
-C25M => Addr[15].CLK
-C25M => Addr[16].CLK
-C25M => Addr[17].CLK
-C25M => Addr[18].CLK
-C25M => Addr[19].CLK
-C25M => Addr[20].CLK
-C25M => Addr[21].CLK
-C25M => Addr[22].CLK
-C25M => Addr[23].CLK
-C25M => IOROMEN.CLK
-C25M => nIOSTRBr.CLK
-C25M => REGEN.CLK
-C25M => nRESout~reg0.CLK
-C25M => LS[0].CLK
-C25M => LS[1].CLK
-C25M => LS[2].CLK
-C25M => LS[3].CLK
-C25M => LS[4].CLK
-C25M => LS[5].CLK
-C25M => LS[6].CLK
-C25M => LS[7].CLK
-C25M => LS[8].CLK
-C25M => LS[9].CLK
-C25M => LS[10].CLK
-C25M => LS[11].CLK
-C25M => LS[12].CLK
-C25M => LS[13].CLK
-C25M => PS[0].CLK
-C25M => PS[1].CLK
-C25M => PS[2].CLK
-C25M => PS[3].CLK
-C25M => SetFWr[0].CLK
-C25M => SetFWr[1].CLK
-C25M => SetFWLoaded.CLK
-C25M => nRESr.CLK
-C25M => nRESf[0].CLK
-C25M => nRESf[1].CLK
-C25M => nRESf[2].CLK
-C25M => nRESf[3].CLK
-C25M => PHI0r2.CLK
-C25M => PHI0r1.CLK
-C25M => IS~7.DATAIN
-C25M => RDD[0].CLK
-C25M => RDD[1].CLK
-C25M => RDD[2].CLK
-C25M => RDD[3].CLK
-C25M => RDD[4].CLK
-C25M => RDD[5].CLK
-C25M => RDD[6].CLK
-C25M => RDD[7].CLK
-PHI0 => comb.IN1
-PHI0 => nWEr.CLK
-PHI0 => RAr[0].CLK
-PHI0 => RAr[1].CLK
-PHI0 => RAr[2].CLK
-PHI0 => RAr[3].CLK
-PHI0 => RAr[4].CLK
-PHI0 => RAr[5].CLK
-PHI0 => RAr[6].CLK
-PHI0 => RAr[7].CLK
-PHI0 => RAr[8].CLK
-PHI0 => RAr[9].CLK
-PHI0 => RAr[10].CLK
-PHI0 => RAr[11].CLK
-PHI0 => CXXXr.CLK
-PHI0 => PHI0r1.DATAIN
-nRES => nRESf[0].DATAIN
-nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SetFW[0] => SetFWr[0].DATAIN
-SetFW[1] => SetFWr[1].DATAIN
-INTin => INTout.DATAIN
-INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
-DMAin => DMAout.DATAIN
-DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE
-nNMIout <= <VCC>
-nIRQout <= <VCC>
-nRDYout <= <VCC>
-nINHout <= <VCC>
-RWout <= <VCC>
-nDMAout <= <VCC>
-RA[0] => RAr[0].DATAIN
-RA[0] => Equal16.IN10
-RA[1] => RAr[1].DATAIN
-RA[1] => Equal16.IN9
-RA[2] => RAr[2].DATAIN
-RA[2] => Equal16.IN8
-RA[3] => RAr[3].DATAIN
-RA[3] => Equal16.IN7
-RA[4] => RAr[4].DATAIN
-RA[4] => Equal16.IN6
-RA[5] => RAr[5].DATAIN
-RA[5] => Equal16.IN5
-RA[6] => RAr[6].DATAIN
-RA[6] => Equal16.IN4
-RA[7] => RAr[7].DATAIN
-RA[7] => Equal16.IN3
-RA[8] => RAr[8].DATAIN
-RA[8] => Equal16.IN2
-RA[9] => RAr[9].DATAIN
-RA[9] => Equal16.IN1
-RA[10] => RAr[10].DATAIN
-RA[10] => Equal16.IN0
-RA[11] => RAr[11].DATAIN
-RA[12] => Equal8.IN1
-RA[13] => Equal8.IN0
-RA[14] => Equal8.IN3
-RA[15] => Equal8.IN2
-nWE => comb.IN1
-nWE => nWEr.DATAIN
-RD[0] <> RD[0]
-RD[1] <> RD[1]
-RD[2] <> RD[2]
-RD[3] <> RD[3]
-RD[4] <> RD[4]
-RD[5] <> RD[5]
-RD[6] <> RD[6]
-RD[7] <> RD[7]
-RAdir <= <VCC>
-RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
-nIOSEL => comb.IN0
-nIOSEL => always7.IN1
-nDEVSEL => comb.IN1
-nDEVSEL => RAMSEL.IN1
-nDEVSEL => comb.IN1
-nDEVSEL => RAMRegSEL.IN1
-nIOSTRB => nIOSTRBr.DATAIN
-nIOSTRB => comb.IN1
-nIOSTRB => comb.IN1
-SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
-DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE
-DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SD[0] <> SD[0]
-SD[1] <> SD[1]
-SD[2] <> SD[2]
-SD[3] <> SD[3]
-SD[4] <> SD[4]
-SD[5] <> SD[5]
-SD[6] <> SD[6]
-SD[7] <> SD[7]
-nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE
-FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE
-MISO => WRD.DATAB
-MOSI <> MOSI
-
-
--- a/cpld/db/GR8RAM.hif
+++ b/cpld/db/GR8RAM.hif
--- a/cpld/db/GR8RAM.lpc.html
+++ b/cpld/db/GR8RAM.lpc.html
@ -1,18 +0,0 @@
-<TABLE>
-<TR  bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-</TABLE>
--- a/cpld/db/GR8RAM.lpc.rdb
+++ b/cpld/db/GR8RAM.lpc.rdb
--- a/cpld/db/GR8RAM.lpc.txt
+++ b/cpld/db/GR8RAM.lpc.txt
@ -1,5 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
--- a/cpld/db/GR8RAM.map.cdb
+++ b/cpld/db/GR8RAM.map.cdb
--- a/cpld/db/GR8RAM.map.hdb
+++ b/cpld/db/GR8RAM.map.hdb
--- a/cpld/db/GR8RAM.map.logdb
+++ b/cpld/db/GR8RAM.map.logdb
@ -1 +0,0 @@
-v1
--- a/cpld/db/GR8RAM.map.qmsg
+++ b/cpld/db/GR8RAM.map.qmsg
@ -1,19 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677601254100 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677601254102 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 28 11:20:53 2023 " "Processing started: Tue Feb 28 11:20:53 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677601254102 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677601254102 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677601254103 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1677601254505 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1677601254505 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(110) " "Verilog HDL warning at gr8ram.v(110): extended using \"x\" or \"z\"" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 110 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1677601274977 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(286) " "Verilog HDL warning at gr8ram.v(286): extended using \"x\" or \"z\"" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 286 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1677601274981 ""}
-{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677601274993 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1677601274993 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1677601275007 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(42) " "Verilog HDL assignment warning at gr8ram.v(42): truncated value with size 32 to match size of target (4)" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275027 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 gr8ram.v(47) " "Verilog HDL assignment warning at gr8ram.v(47): truncated value with size 32 to match size of target (14)" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275028 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(134) " "Verilog HDL assignment warning at gr8ram.v(134): truncated value with size 32 to match size of target (8)" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275033 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(142) " "Verilog HDL assignment warning at gr8ram.v(142): truncated value with size 32 to match size of target (8)" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275033 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(149) " "Verilog HDL assignment warning at gr8ram.v(149): truncated value with size 32 to match size of target (8)" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 149 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275034 "|GR8RAM"}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 563 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 566 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 565 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 564 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 567 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 562 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" {  } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 561 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|RAdir"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1677601275953 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 " "3 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1677601276221 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "333 " "Implemented 333 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1677601276250 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1677601276250 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1677601276250 ""} { "Info" "ICUT_CUT_TM_LCELLS" "253 " "Implemented 253 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1677601276250 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1677601276250 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg " "Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677601276457 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13114 " "Peak virtual memory: 13114 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601276495 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:16 2023 " "Processing ended: Tue Feb 28 11:21:16 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601276495 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Elapsed time: 00:00:23" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601276495 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601276495 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1677601276495 ""}
--- a/cpld/db/GR8RAM.map.rdb
+++ b/cpld/db/GR8RAM.map.rdb
--- a/cpld/db/GR8RAM.pre_map.hdb
+++ b/cpld/db/GR8RAM.pre_map.hdb
--- a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb
+++ b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb
--- a/cpld/db/GR8RAM.routing.rdb
+++ b/cpld/db/GR8RAM.routing.rdb
--- a/cpld/db/GR8RAM.rtlv.hdb
+++ b/cpld/db/GR8RAM.rtlv.hdb
--- a/cpld/db/GR8RAM.rtlv_sg.cdb
+++ b/cpld/db/GR8RAM.rtlv_sg.cdb
--- a/cpld/db/GR8RAM.rtlv_sg_swap.cdb
+++ b/cpld/db/GR8RAM.rtlv_sg_swap.cdb
--- a/cpld/db/GR8RAM.sld_design_entry.sci
+++ b/cpld/db/GR8RAM.sld_design_entry.sci
--- a/cpld/db/GR8RAM.sld_design_entry_dsc.sci
+++ b/cpld/db/GR8RAM.sld_design_entry_dsc.sci
--- a/cpld/db/GR8RAM.smart_action.txt
+++ b/cpld/db/GR8RAM.smart_action.txt
@ -1 +0,0 @@
-DONE
--- a/cpld/db/GR8RAM.smp_dump.txt
+++ b/cpld/db/GR8RAM.smp_dump.txt
@ -1,9 +0,0 @@
-
-State Machine - |GR8RAM|IS
-Name IS.111 IS.110 IS.101 IS.100 IS.001 IS.000 
-IS.000 0 0 0 0 0 0 
-IS.001 0 0 0 0 1 1 
-IS.100 0 0 0 1 0 1 
-IS.101 0 0 1 0 0 1 
-IS.110 0 1 0 0 0 1 
-IS.111 1 0 0 0 0 1 
--- a/cpld/db/GR8RAM.sta.qmsg
+++ b/cpld/db/GR8RAM.sta.qmsg
@ -1,22 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677601288128 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677601288129 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 28 11:21:27 2023 " "Processing started: Tue Feb 28 11:21:27 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677601288129 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1677601288129 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1677601288130 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1677601288250 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1677601288411 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1677601288411 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601288455 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601288455 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1677601288513 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1677601288921 ""}
-{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1677601289007 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1677601289045 ""}
-{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." {  } {  } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1677601289084 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 10.278 " "Worst-case setup slack is 10.278" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   10.278               0.000 C25M  " "   10.278               0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289092 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289092 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.376 " "Worst-case hold slack is 1.376" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289097 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289097 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.376               0.000 C25M  " "    1.376               0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289097 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289097 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.311 " "Worst-case recovery slack is 33.311" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   33.311               0.000 C25M  " "   33.311               0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289104 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289104 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.135 " "Worst-case removal slack is 6.135" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.135               0.000 C25M  " "    6.135               0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289109 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289109 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.734               0.000 C25M  " "   19.734               0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  488.734               0.000 PHI0  " "  488.734               0.000 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289113 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289113 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1677601289175 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677601289198 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677601289201 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13081 " "Peak virtual memory: 13081 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601289276 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:29 2023 " "Processing ended: Tue Feb 28 11:21:29 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601289276 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601289276 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601289276 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1677601289276 ""}
--- a/cpld/db/GR8RAM.sta.rdb
+++ b/cpld/db/GR8RAM.sta.rdb
--- a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb
+++ b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb
--- a/cpld/db/GR8RAM.tis_db_list.ddb
+++ b/cpld/db/GR8RAM.tis_db_list.ddb
--- a/cpld/db/GR8RAM.vpr.ammdb
+++ b/cpld/db/GR8RAM.vpr.ammdb
--- a/cpld/incremental_db/README
+++ b/cpld/incremental_db/README
@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used.  To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
--- a/cpld/incremental_db/compiled_partitions/GR8RAM.db_info
+++ b/cpld/incremental_db/compiled_partitions/GR8RAM.db_info
@ -1,3 +0,0 @@
-Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
-Version_Index = 553882368
-Creation_Time = Tue Feb 28 11:21:15 2023
--- a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
+++ b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
--- a/cpld/output_files/GR8RAM.asm.rpt
+++ b/cpld/output_files/GR8RAM.asm.rpt
@ -1,6 +1,6 @@
 Assembler report for GR8RAM
-Tue Feb 28 11:21:26 2023
-Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Fri Feb 16 20:54:00 2024
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition


 ---------------------
@ -10,7 +10,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
  2. Assembler Summary
  3. Assembler Settings
  4. Assembler Generated Files
-  5. Assembler Device Options: /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof
+  5. Assembler Device Options: /Repos/GR8RAM/cpld/output_files/GR8RAM.pof
  6. Assembler Messages


@ -18,7 +18,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 2022  Intel Corporation. All rights reserved.
+Copyright (C) 2019  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Tue Feb 28 11:21:26 2023 ;
+; Assembler Status      ; Successful - Fri Feb 16 20:54:00 2024 ;
 ; Revision Name         ; GR8RAM                                ;
 ; Top-level Entity Name ; GR8RAM                                ;
 ; Family                ; MAX II                                ;
@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
 +--------+---------+---------------+


-+----------------------------------------------+
-; Assembler Generated Files                    ;
-+----------------------------------------------+
-; File Name                                    ;
-+----------------------------------------------+
-; /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof ;
-+----------------------------------------------+
+--------------------------------------------+
+; Assembler Generated Files                  ;
+--------------------------------------------+
+; File Name                                  ;
+--------------------------------------------+
+; /Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
+--------------------------------------------+


-+------------------------------------------------------------------------+
-; Assembler Device Options: /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof ;
-+----------------+-------------------------------------------------------+
-; Option         ; Setting                                               ;
-+----------------+-------------------------------------------------------+
-; JTAG usercode  ; 0x00163AA4                                            ;
-; Checksum       ; 0x00163E9C                                            ;
-+----------------+-------------------------------------------------------+
+----------------------------------------------------------------------+
+; Assembler Device Options: /Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
+----------------+-----------------------------------------------------+
+; Option         ; Setting                                             ;
+----------------+-----------------------------------------------------+
+; JTAG usercode  ; 0x00163AA4                                          ;
+; Checksum       ; 0x00163E9C                                          ;
+----------------+-----------------------------------------------------+


 +--------------------+
@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
 +--------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
-    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
-    Info: Processing started: Tue Feb 28 11:21:25 2023
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Fri Feb 16 20:53:59 2024
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 13100 megabytes
-    Info: Processing ended: Tue Feb 28 11:21:26 2023
+    Info: Peak virtual memory: 13097 megabytes
+    Info: Processing ended: Fri Feb 16 20:54:00 2024
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01

--- a/cpld/output_files/GR8RAM.done
+++ b/cpld/output_files/GR8RAM.done
@ -1 +1 @@
-Tue Feb 28 11:21:32 2023
+Fri Feb 16 20:54:03 2024
--- a/cpld/output_files/GR8RAM.fit.rpt
+++ b/cpld/output_files/GR8RAM.fit.rpt
@ -1,6 +1,6 @@
 Fitter report for GR8RAM
-Tue Feb 28 11:21:23 2023
-Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Fri Feb 16 20:53:58 2024
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition


 ---------------------
@ -38,7 +38,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 2022  Intel Corporation. All rights reserved.
+Copyright (C) 2019  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
@ -55,21 +55,21 @@ https://fpgasoftware.intel.com/eula.



-+------------------------------------------------------------------------+
-; Fitter Summary                                                         ;
-+-----------------------+------------------------------------------------+
-; Fitter Status         ; Successful - Tue Feb 28 11:21:23 2023          ;
-; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
-; Revision Name         ; GR8RAM                                         ;
-; Top-level Entity Name ; GR8RAM                                         ;
-; Family                ; MAX II                                         ;
-; Device                ; EPM240T100C5                                   ;
-; Timing Models         ; Final                                          ;
-; Total logic elements  ; 233 / 240 ( 97 % )                             ;
-; Total pins            ; 80 / 80 ( 100 % )                              ;
-; Total virtual pins    ; 0                                              ;
-; UFM blocks            ; 0 / 1 ( 0 % )                                  ;
-+-----------------------+------------------------------------------------+
+---------------------------------------------------------------------+
+; Fitter Summary                                                      ;
+-----------------------+---------------------------------------------+
+; Fitter Status         ; Successful - Fri Feb 16 20:53:58 2024       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name         ; GR8RAM                                      ;
+; Top-level Entity Name ; GR8RAM                                      ;
+; Family                ; MAX II                                      ;
+; Device                ; EPM240T100C5                                ;
+; Timing Models         ; Final                                       ;
+; Total logic elements  ; 233 / 240 ( 97 % )                          ;
+; Total pins            ; 80 / 80 ( 100 % )                           ;
+; Total virtual pins    ; 0                                           ;
+; UFM blocks            ; 0 / 1 ( 0 % )                               ;
+-----------------------+---------------------------------------------+


 +--------------------------------------------------------------------------------------------------------------------------------------+
@ -134,15 +134,15 @@ https://fpgasoftware.intel.com/eula.
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.7%      ;
-;     Processors 3-4         ;   0.5%      ;
+;     Processor 2            ;   0.8%      ;
+;     Processors 3-4         ;   0.7%      ;
 +----------------------------+-------------+


 +--------------+
 ; Pin-Out File ;
 +--------------+
-The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin.
+The pin-out file can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.pin.


 +---------------------------------------------------------------------+
@ -741,13 +741,13 @@ Info (332111): Found 2 clocks
    Info (332111):   40.000         C25M
    Info (332111):  978.000         PHI0
 Info (186079): Completed User Assigned Global Signals Promotion Operation
-Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9
-Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9
+Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
+Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
    Info (186217): Destination "comb~0" may be non-global or may not use global clock
-    Info (186217): Destination "PHI0r1" may be non-global or may not use global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 10
-Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9
-Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 16
-    Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 94
+    Info (186217): Destination "PHI0r1" may be non-global or may not use global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 10
+Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
+Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 16
+    Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 94
 Info (186079): Completed Auto Global Promotion Operation
 Info (176234): Starting register packing
 Info (186468): Started processing fast register assignments
@ -760,13 +760,13 @@ Info (176215): I/O bank details before I/O pin placement
    Info (176214): Statistics of I/O banks
        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  0 pins available
        Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used --  1 pins available
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
 Info (170189): Fitter placement preparation operations beginning
 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
 Info (170191): Fitter placement operations beginning
 Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
 Info (170193): Fitter routing operations beginning
 Info (170195): Router estimated average interconnect usage is 30% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
@ -774,20 +774,20 @@ Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were
    Info (170201): Optimizations that may affect the design's routability were skipped
    Info (170200): Optimizations that may affect the design's timing were skipped
 Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.16 seconds.
 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
-Info (144001): Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg
+Info (144001): Generated suppressed messages file /Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings
-    Info: Peak virtual memory: 13746 megabytes
-    Info: Processing ended: Tue Feb 28 11:21:23 2023
-    Info: Elapsed time: 00:00:06
-    Info: Total CPU time (on all processors): 00:00:05
+    Info: Peak virtual memory: 13772 megabytes
+    Info: Processing ended: Fri Feb 16 20:53:58 2024
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:03


 +----------------------------+
 ; Fitter Suppressed Messages ;
 +----------------------------+
-The suppressed messages can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg.
+The suppressed messages can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg.


--- a/cpld/output_files/GR8RAM.fit.summary
+++ b/cpld/output_files/GR8RAM.fit.summary
@ -1,5 +1,5 @@
-Fitter Status : Successful - Tue Feb 28 11:21:23 2023
-Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Fitter Status : Successful - Fri Feb 16 20:53:58 2024
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 Revision Name : GR8RAM
 Top-level Entity Name : GR8RAM
 Family : MAX II
--- a/cpld/output_files/GR8RAM.flow.rpt
+++ b/cpld/output_files/GR8RAM.flow.rpt
@ -1,6 +1,6 @@
 Flow report for GR8RAM
-Tue Feb 28 11:21:31 2023
-Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Fri Feb 16 20:54:03 2024
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition


 ---------------------
@ -21,7 +21,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 2022  Intel Corporation. All rights reserved.
+Copyright (C) 2019  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.



-+------------------------------------------------------------------------+
-; Flow Summary                                                           ;
-+-----------------------+------------------------------------------------+
-; Flow Status           ; Successful - Tue Feb 28 11:21:31 2023          ;
-; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
-; Revision Name         ; GR8RAM                                         ;
-; Top-level Entity Name ; GR8RAM                                         ;
-; Family                ; MAX II                                         ;
-; Device                ; EPM240T100C5                                   ;
-; Timing Models         ; Final                                          ;
-; Total logic elements  ; 233 / 240 ( 97 % )                             ;
-; Total pins            ; 80 / 80 ( 100 % )                              ;
-; Total virtual pins    ; 0                                              ;
-; UFM blocks            ; 0 / 1 ( 0 % )                                  ;
-+-----------------------+------------------------------------------------+
+---------------------------------------------------------------------+
+; Flow Summary                                                        ;
+-----------------------+---------------------------------------------+
+; Flow Status           ; Successful - Fri Feb 16 20:54:00 2024       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name         ; GR8RAM                                      ;
+; Top-level Entity Name ; GR8RAM                                      ;
+; Family                ; MAX II                                      ;
+; Device                ; EPM240T100C5                                ;
+; Timing Models         ; Final                                       ;
+; Total logic elements  ; 233 / 240 ( 97 % )                          ;
+; Total pins            ; 80 / 80 ( 100 % )                           ;
+; Total virtual pins    ; 0                                           ;
+; UFM blocks            ; 0 / 1 ( 0 % )                               ;
+-----------------------+---------------------------------------------+


 +-----------------------------------------+
@ -60,33 +60,25 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 02/28/2023 11:20:54 ;
+; Start date & time ; 02/16/2024 20:53:35 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; GR8RAM              ;
 +-------------------+---------------------+


-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                                                 ;
-+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name                       ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
-+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID                 ; 121381084694.167760125411500           ; --            ; --          ; --                                ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST       ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST       ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST       ; Off                                    ; --            ; --          ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST       ; Off                                    ; --            ; --          ; eda_board_design_symbol           ;
-; EDA_NETLIST_WRITER_OUTPUT_DIR         ; simulation/questa                      ; --            ; --          ; eda_simulation                    ;
-; EDA_OUTPUT_DATA_FORMAT                ; Verilog Hdl                            ; --            ; --          ; eda_simulation                    ;
-; EDA_SIMULATION_TOOL                   ; Questa Intel FPGA (Verilog)            ; <None>        ; --          ; --                                ;
-; EDA_TIME_SCALE                        ; 1 ps                                   ; --            ; --          ; eda_simulation                    ;
-; IOBANK_VCCIO                          ; -- (Not supported for targeted family) ; --            ; --          ; 1                                 ;
-; IOBANK_VCCIO                          ; -- (Not supported for targeted family) ; --            ; --          ; 2                                 ;
-; MAX_CORE_JUNCTION_TEMP                ; 85                                     ; --            ; --          ; --                                ;
-; MIN_CORE_JUNCTION_TEMP                ; 0                                      ; --            ; --          ; --                                ;
-; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V                                   ; --            ; --          ; --                                ;
-; PROJECT_OUTPUT_DIRECTORY              ; output_files                           ; --            ; --          ; --                                ;
-+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                          ;
+---------------------------------------+----------------------------------------+---------------+-------------+------------+
+; Assignment Name                       ; Value                                  ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+----------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID                 ; 121380219419.170813481504184           ; --            ; --          ; --         ;
+; IOBANK_VCCIO                          ; -- (Not supported for targeted family) ; --            ; --          ; 1          ;
+; IOBANK_VCCIO                          ; -- (Not supported for targeted family) ; --            ; --          ; 2          ;
+; MAX_CORE_JUNCTION_TEMP                ; 85                                     ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP                ; 0                                      ; --            ; --          ; --         ;
+; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V                                   ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY              ; output_files                           ; --            ; --          ; --         ;
+---------------------------------------+----------------------------------------+---------------+-------------+------------+


 +--------------------------------------------------------------------------------------------------------------------------+
@ -94,12 +86,11 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:23     ; 1.0                     ; 13114 MB            ; 00:00:48                           ;
-; Fitter               ; 00:00:06     ; 1.0                     ; 13746 MB            ; 00:00:05                           ;
-; Assembler            ; 00:00:01     ; 1.0                     ; 13099 MB            ; 00:00:01                           ;
-; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 13081 MB            ; 00:00:01                           ;
-; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 13024 MB            ; 00:00:01                           ;
-; Total                ; 00:00:33     ; --                      ; --                  ; 00:00:56                           ;
+; Analysis & Synthesis ; 00:00:20     ; 1.0                     ; 13135 MB            ; 00:00:43                           ;
+; Fitter               ; 00:00:02     ; 1.0                     ; 13772 MB            ; 00:00:03                           ;
+; Assembler            ; 00:00:01     ; 1.0                     ; 13093 MB            ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 13090 MB            ; 00:00:01                           ;
+; Total                ; 00:00:25     ; --                      ; --                  ; 00:00:48                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+


@ -112,7 +103,6 @@ https://fpgasoftware.intel.com/eula.
 ; Fitter               ; ZaneMacWin11     ; Windows 10 ; 10.0       ; x86_64         ;
 ; Assembler            ; ZaneMacWin11     ; Windows 10 ; 10.0       ; x86_64         ;
 ; Timing Analyzer      ; ZaneMacWin11     ; Windows 10 ; 10.0       ; x86_64         ;
-; EDA Netlist Writer   ; ZaneMacWin11     ; Windows 10 ; 10.0       ; x86_64         ;
 +----------------------+------------------+------------+------------+----------------+


@ -123,7 +113,6 @@ quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
 quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
 quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
 quartus_sta GR8RAM -c GR8RAM
-quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM



--- a/cpld/output_files/GR8RAM.jdi
+++ b/cpld/output_files/GR8RAM.jdi
@ -1,6 +1,6 @@
 <sld_project_info>
  <project>
-    <hash md5_digest_80b="e669c88e609b9ce1c5b6"/>
+    <hash md5_digest_80b="1794c049bdbd51a27b8f"/>
  </project>
  <file_info>
    <file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
--- a/cpld/output_files/GR8RAM.map.rpt
+++ b/cpld/output_files/GR8RAM.map.rpt
@ -1,6 +1,6 @@
 Analysis & Synthesis report for GR8RAM
-Tue Feb 28 11:21:16 2023
-Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Fri Feb 16 20:53:55 2024
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition


 ---------------------
@ -26,7 +26,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 2022  Intel Corporation. All rights reserved.
+Copyright (C) 2019  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.



-+------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                 ;
-+-----------------------------+------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Tue Feb 28 11:21:16 2023          ;
-; Quartus Prime Version       ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
-; Revision Name               ; GR8RAM                                         ;
-; Top-level Entity Name       ; GR8RAM                                         ;
-; Family                      ; MAX II                                         ;
-; Total logic elements        ; 253                                            ;
-; Total pins                  ; 80                                             ;
-; Total virtual pins          ; 0                                              ;
-; UFM blocks                  ; 0 / 1 ( 0 % )                                  ;
-+-----------------------------+------------------------------------------------+
+---------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                              ;
+-----------------------------+---------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Fri Feb 16 20:53:55 2024       ;
+; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name               ; GR8RAM                                      ;
+; Top-level Entity Name       ; GR8RAM                                      ;
+; Family                      ; MAX II                                      ;
+; Total logic elements        ; 253                                         ;
+; Total pins                  ; 80                                          ;
+; Total virtual pins          ; 0                                           ;
+; UFM blocks                  ; 0 / 1 ( 0 % )                               ;
+-----------------------------+---------------------------------------------+


 +------------------------------------------------------------------------------------------------------------+
@ -145,13 +145,13 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------+-------------+


-+-----------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                  ;
-+----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path              ; Library ;
-+----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+
-; gr8ram.v                         ; yes             ; Auto-Found Verilog HDL File  ; //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v ;         ;
-+----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                        ;
+----------------------------------+-----------------+------------------------+---------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path          ; Library ;
+----------------------------------+-----------------+------------------------+---------------------------------------+---------+
+; GR8RAM.v                         ; yes             ; User Verilog HDL File  ; //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v ;         ;
+----------------------------------+-----------------+------------------------+---------------------------------------+---------+


 +-----------------------------------------------------+
@ -279,44 +279,44 @@ Encoding Type:  One-Hot
 +-------------------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
-    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
-    Info: Processing started: Tue Feb 28 11:20:53 2023
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Fri Feb 16 20:53:35 2024
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
-    Info (12023): Found entity 1: GR8RAM File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
+    Info (12023): Found entity 1: GR8RAM File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 1
 Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
-Warning (10230): Verilog HDL assignment warning at gr8ram.v(42): truncated value with size 32 to match size of target (4) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 42
-Warning (10230): Verilog HDL assignment warning at gr8ram.v(47): truncated value with size 32 to match size of target (14) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 47
-Warning (10230): Verilog HDL assignment warning at gr8ram.v(134): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 134
-Warning (10230): Verilog HDL assignment warning at gr8ram.v(142): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 142
-Warning (10230): Verilog HDL assignment warning at gr8ram.v(149): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 149
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 42
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 47
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 134
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 142
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 149
 Warning (13024): Output pins are stuck at VCC or GND
-    Warning (13410): Pin "nNMIout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 563
-    Warning (13410): Pin "nIRQout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 566
-    Warning (13410): Pin "nRDYout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 565
-    Warning (13410): Pin "nINHout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 564
-    Warning (13410): Pin "RWout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 567
-    Warning (13410): Pin "nDMAout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 562
-    Warning (13410): Pin "RAdir" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 561
+    Warning (13410): Pin "nNMIout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 563
+    Warning (13410): Pin "nIRQout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 566
+    Warning (13410): Pin "nRDYout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 565
+    Warning (13410): Pin "nINHout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 564
+    Warning (13410): Pin "RWout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 567
+    Warning (13410): Pin "nDMAout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 562
+    Warning (13410): Pin "RAdir" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 561
 Info (17049): 3 registers lost all their fanouts during netlist optimizations.
 Info (21057): Implemented 333 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 28 input pins
    Info (21059): Implemented 35 output pins
    Info (21060): Implemented 17 bidirectional pins
    Info (21061): Implemented 253 logic cells
-Info (144001): Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
-    Info: Peak virtual memory: 13114 megabytes
-    Info: Processing ended: Tue Feb 28 11:21:16 2023
-    Info: Elapsed time: 00:00:23
-    Info: Total CPU time (on all processors): 00:00:48
+Info (144001): Generated suppressed messages file /Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings
+    Info: Peak virtual memory: 13135 megabytes
+    Info: Processing ended: Fri Feb 16 20:53:55 2024
+    Info: Elapsed time: 00:00:20
+    Info: Total CPU time (on all processors): 00:00:43


 +------------------------------------------+
 ; Analysis & Synthesis Suppressed Messages ;
 +------------------------------------------+
-The suppressed messages can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg.
+The suppressed messages can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.


--- a/cpld/output_files/GR8RAM.map.smsg
+++ b/cpld/output_files/GR8RAM.map.smsg
@ -1,2 +1,2 @@
-Warning (10273): Verilog HDL warning at gr8ram.v(110): extended using "x" or "z" File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 110
-Warning (10273): Verilog HDL warning at gr8ram.v(286): extended using "x" or "z" File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 286
+Warning (10273): Verilog HDL warning at GR8RAM.v(110): extended using "x" or "z" File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 110
+Warning (10273): Verilog HDL warning at GR8RAM.v(286): extended using "x" or "z" File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 286
--- a/cpld/output_files/GR8RAM.map.summary
+++ b/cpld/output_files/GR8RAM.map.summary
@ -1,5 +1,5 @@
-Analysis & Synthesis Status : Successful - Tue Feb 28 11:21:16 2023
-Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Analysis & Synthesis Status : Successful - Fri Feb 16 20:53:55 2024
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 Revision Name : GR8RAM
 Top-level Entity Name : GR8RAM
 Family : MAX II
--- a/cpld/output_files/GR8RAM.pin
+++ b/cpld/output_files/GR8RAM.pin
@ -1,4 +1,4 @@
- -- Copyright (C) 2022  Intel Corporation. All rights reserved.
+ -- Copyright (C) 2019  Intel Corporation. All rights reserved.
 -- Your use of Intel Corporation's design tools, logic functions 
 -- and other software and tools, and any partner logic 
 -- functions, and any output files from any of the foregoing 
@ -58,7 +58,7 @@
 -- Pin directions (input, output or bidir) are based on device operating in user mode.
 ---------------------------------------------------------------------------------

-Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 CHIP  "GR8RAM"  ASSIGNED TO AN: EPM240T100C5

 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--- a/cpld/output_files/GR8RAM.pof
+++ b/cpld/output_files/GR8RAM.pof
--- a/cpld/output_files/GR8RAM.sta.rpt
+++ b/cpld/output_files/GR8RAM.sta.rpt
@ -1,6 +1,6 @@
 Timing Analyzer report for GR8RAM
-Tue Feb 28 11:21:29 2023
-Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Fri Feb 16 20:54:03 2024
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition


 ---------------------
@ -40,7 +40,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 2022  Intel Corporation. All rights reserved.
+Copyright (C) 2019  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula.



-+--------------------------------------------------------------------------------+
-; Timing Analyzer Summary                                                        ;
-+-----------------------+--------------------------------------------------------+
-; Quartus Prime Version ; Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
-; Timing Analyzer       ; Legacy Timing Analyzer                                 ;
-; Revision Name         ; GR8RAM                                                 ;
-; Device Family         ; MAX II                                                 ;
-; Device Name           ; EPM240T100C5                                           ;
-; Timing Models         ; Final                                                  ;
-; Delay Model           ; Slow Model                                             ;
-; Rise/Fall Delays      ; Unavailable                                            ;
-+-----------------------+--------------------------------------------------------+
+-----------------------------------------------------------------------------+
+; Timing Analyzer Summary                                                     ;
+-----------------------+-----------------------------------------------------+
+; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Timing Analyzer       ; Legacy Timing Analyzer                              ;
+; Revision Name         ; GR8RAM                                              ;
+; Device Family         ; MAX II                                              ;
+; Device Name           ; EPM240T100C5                                        ;
+; Timing Models         ; Final                                               ;
+; Delay Model           ; Slow Model                                          ;
+; Rise/Fall Delays      ; Unavailable                                         ;
+-----------------------+-----------------------------------------------------+


 +------------------------------------------+
@ -80,10 +80,11 @@ https://fpgasoftware.intel.com/eula.
 ; Maximum allowed            ; 4           ;
 ;                            ;             ;
 ; Average used               ; 1.00        ;
-; Maximum used               ; 1           ;
+; Maximum used               ; 2           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.0%      ;
 +----------------------------+-------------+


@ -92,7 +93,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------+--------+--------------------------+
 ; SDC File Path ; Status ; Read at                  ;
 +---------------+--------+--------------------------+
-; GR8RAM.sdc    ; OK     ; Tue Feb 28 11:21:29 2023 ;
+; GR8RAM.sdc    ; OK     ; Fri Feb 16 20:54:03 2024 ;
 +---------------+--------+--------------------------+


@ -745,8 +746,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +--------------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
-    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
-    Info: Processing started: Tue Feb 28 11:21:27 2023
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Fri Feb 16 20:54:01 2024
 Info: Command: quartus_sta GR8RAM -c GR8RAM
 Info: qsta_default_script.tcl version: #1
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@ -783,8 +784,8 @@ Info (332001): The selected device family is not supported by the report_metasta
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 13081 megabytes
-    Info: Processing ended: Tue Feb 28 11:21:29 2023
+    Info: Peak virtual memory: 13090 megabytes
+    Info: Processing ended: Fri Feb 16 20:54:03 2024
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01

--- a/cpld/simulation/questa/GR8RAM.sft
+++ b/cpld/simulation/questa/GR8RAM.sft
@ -1 +0,0 @@
-set tool_name "Questa Intel FPGA (Verilog)"
--- a/cpld/simulation/questa/GR8RAM.vo
+++ b/cpld/simulation/questa/GR8RAM.vo
Author	SHA1	Message	Date
Zane Kaminski	c3716ebb82	Change ~ to ! where appropriate in GR8RAM.v	2024-02-16 20:54:16 -05:00
Zane Kaminski	97943bc2e7	Recompile	2024-02-16 20:48:50 -05:00
Zane Kaminski	7eb62dbe5a	Untrack and delete .qws files	2024-02-16 20:46:40 -05:00
Zane Kaminski	f347a27f89	Create new quartus project	2024-02-16 20:43:29 -05:00
Zane Kaminski	9f456e8d0f	Delete old quartus stuff	2024-02-16 20:41:52 -05:00
Zane Kaminski	b467eaac6b	Update .gitignore	2024-02-16 20:41:33 -05:00