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GR8RAM
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4 Commits
b406b1da16 ... 0c8bf7ebe5

Author SHA1 Message Date
Zane Kaminski 0c8bf7ebe5 SPI? 2023-06-07 18:52:44 -04:00
Zane Kaminski 3ef608802c Fix pinout 2023-04-14 03:58:48 -04:00
Zane Kaminski 95a87fef83 Some power improvements 2023-04-14 03:58:43 -04:00
Zane Kaminski d0ece610cc Undo 14 MB attempt 2023-04-14 03:06:52 -04:00
51 changed files with 1291 additions and 1056 deletions
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31
cpld/GR8RAM.qsf
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@ -1,3 +1,4 @@
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
@ -41,7 +42,7 @@ set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:15:44 FEBRUARY 28, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@ -50,14 +51,12 @@ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/questa -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_location_assignment PIN_1 -to RA[4]
set_location_assignment PIN_2 -to RA[5]
set_location_assignment PIN_3 -to RA[6]
set_location_assignment PIN_4 -to RA[3]
@ -76,9 +75,9 @@ set_location_assignment PIN_36 -to RA[13]
set_location_assignment PIN_37 -to RA[14]
set_location_assignment PIN_38 -to RA[15]
set_location_assignment PIN_39 -to nIOSEL
set_location_assignment PIN_42 -to nIOSTRB
set_location_assignment PIN_40 -to nDEVSEL
set_location_assignment PIN_41 -to PHI0
set_location_assignment PIN_42 -to nIOSTRB
set_location_assignment PIN_43 -to nWE
set_location_assignment PIN_44 -to nRES
set_location_assignment PIN_47 -to SD[1]
@ -138,9 +137,9 @@ set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MISO
set_location_assignment PIN_21 -to nDMAout
set_location_assignment PIN_19 -to RAdir
set_location_assignment PIN_20 -to INTout
set_location_assignment PIN_26 -to nNMIout
set_location_assignment PIN_27 -to nINHout
set_location_assignment PIN_28 -to nRDYout
set_location_assignment PIN_26 -to GNDout1
set_location_assignment PIN_27 -to PU
set_location_assignment PIN_28 -to GNDout2
set_location_assignment PIN_29 -to nIRQout
set_location_assignment PIN_33 -to RWout
set_location_assignment PIN_48 -to DMAin
@ -148,7 +147,6 @@ set_location_assignment PIN_49 -to INTin
set_location_assignment PIN_17 -to RDdir
set_location_assignment PIN_18 -to DMAout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
@ -254,4 +252,15 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SD
set_instance_assignment -name SLOW_SLEW_RATE ON -to SD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD
set_global_assignment -name SDC_FILE GR8RAM.sdc
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RA[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PU
set_global_assignment -name VERILOG_FILE GR8RAM.v
set_global_assignment -name SDC_FILE GR8RAM.sdc
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"

254
cpld/GR8RAM.v
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@ -1,14 +1,16 @@
module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
INTin, INTout, DMAin, DMAout,
nNMIout, nIRQout, nRDYout, nINHout, RWout, nDMAout,
RA, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
GNDout1, GNDout2, nIRQout, RWout, nDMAout,
RA, PU, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
nFCS, FCK, MISO, MOSI);
/* Clock signals */
input C25M, PHI0;
reg PHI0r1, PHI0r2;
always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
/* PHI0 synchronization to 25 MHz clock */
reg [2:0] PHI0r;
always @(posedge C25M) PHI0r <= { PHI0r[1:0], PHI0 };
/* Reset synchronization */
input nRES; reg nRESr = 0;
@ -19,12 +21,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
/* Firmware select */
input [1:0] SetFW;
wire [1:0] SetROM = ~SetFW[1:0];
wire SetENRestore = SetROM[1:0]==1'b11;
wire SetENRestore = SetROM[1:0]==2'b11;
wire SetEN24bit = SetROM[1];
/* State counter from PHI0 rising edge */
reg [3:0] PS = 0;
wire PSStart = PS==0 && PHI0r1 && !PHI0r2;
wire PSStart = PS==0 && PHI0r[0] && !PHI0r[1];
always @(posedge C25M) begin
if (PSStart) PS <= 1;
else if (PS==0) PS <= 0;
@ -53,20 +55,38 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
input nIOSEL, nDEVSEL, nIOSTRB;
/* Apple address bus */
input [15:0] RA; reg CXXXr;
input [15:0] RA;
input nWE;
always @(posedge PHI0) CXXXr <= RA[15:12]==4'hC;
input PU;
wire RA4 = RA[4] && PU;
/* Apple select signals */
wire RAMExists = (!SetEN24bit || !Addr[23] || Addr[22] || Addr[21]);
wire RAMExists = !SetEN24bit || !Addr[23] ;
wire BankSEL = REGEN && !nDEVSEL && RA[3:0]==4'hF;
wire SPITX1SEL = REGEN && !nDEVSEL && RA[3:0]==4'hD;
wire SPITX0SEL = REGEN && !nDEVSEL && RA[3:0]==4'hC;
wire SPITXSEL = REGEN && !nDEVSEL && (RA[3:0]==4'hC || RA[3:0]==4'hD) &&
!RestoreDone && SetENRestore;
wire RAMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h3;
wire AddrHSEL = REGEN && !nDEVSEL && RA[3:0]==4'h2;
wire AddrMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h1;
wire AddrLSEL = REGEN && !nDEVSEL && RA[3:0]==4'h0;
/* Slot number detect */
reg SlotKnown = 0;
reg [2:0] Slot;
always @(negedge PHI0) begin
if (!nIOSEL) begin
SlotKnown <= 1;
Slot <= RA[10:8];
end
end
/* RAM/ROM speculative select */
wire RAMSpecSEL = RA[15:8]==8'hC0 && RA[7] && RA[3:0]==4'h3 && REGEN;
wire IOSELSpecSEL = RA[15:12]==4'hC && !RA[11] && (RA[10:8]==Slot[2:0] || !SlotKnown);
wire IOSTRBSpecSEL = RA[15:12]==4'hC && RA[11] && IOROMEN;
wire RAMROMSpecSEL = RAMSpecSEL || IOSELSpecSEL || IOSTRBSpecSEL;
reg RAMROMSpecSELr; always @(posedge PHI0) RAMROMSpecSELr <= RAMROMSpecSEL;
/* IOROMEN control */
reg IOROMEN = 0;
wire IOROMRES = !nIOSTRB && RA[10:0]==11'h7FF;
@ -84,10 +104,11 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
end
/* Apple data bus */
inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
wire RDOEbase = PHI0 && nWE &&
((!nDEVSEL && RAMExists) || !nIOSEL || (!nIOSTRB && IOROMEN));
reg [7:0] RDD;
output RDdir = !(PHI0r2 && nWE && PHI0 &&
((!nDEVSEL && RAMExists) || !nIOSEL || (!nIOSTRB && IOROMEN)));
inout [7:0] RD = (RDOEbase && PHI0r[2]) ? RDD[7:0] : 8'bZ;
output RDdir = !(RDOEbase && PHI0r[1]);
/* Slinky address registers */
reg [23:0] Addr = 0;
@ -97,9 +118,6 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
always @(posedge C25M, negedge nRESr) begin
if (!nRESr) begin
Addr[23:0] <= 24'h000000;
AddrIncL <= 0;
AddrIncM <= 0;
AddrIncH <= 0;
end else begin
if (PS==8 && RAMSEL) AddrIncL <= 1;
else AddrIncL <= 0;
@ -130,138 +148,101 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
/* ROM bank register */
reg Bank;
always @(posedge C25M, negedge nRESr) begin
always @(negedge PHI0, negedge nRESr) begin
if (!nRESr) Bank <= 0;
else if (PS==8 && BankSEL && !nWE) begin
Bank <= RD[0];
end
else if (BankSEL && !nWE) Bank <= RD[0];
end
/* Restore state */
reg RestoreDone = 0;
always @(posedge C25M) begin
always @(negedge PHI0, negedge SetENRestore) begin
if (!SetENRestore) RestoreDone <= 1;
else if (PS==8 && BankSEL && !nWE) begin
if (RD[1:0]==2'b11) RestoreDone <= 1;
end
else if (BankSEL && !nWE && RD[1]) RestoreDone <= 1;
end
/* Flash chip select register */
reg FCS = 0;
always @(negedge PHI0, posedge RestoreDone) begin
if (RestoreDone) FCS <= 0;
else if (BankSEL && !nWE) FCS <= RD[0];
end
/* SPI flash control signals */
output reg nFCS = 1;
output FCK = FCKout;
reg FCKout = 0;
reg FCKout; output FCK = FCKout;
inout MOSI = MOSIOE ? MOSIout : 1'bZ;
reg MOSIOE = 0;
reg MOSIOE;
input MISO;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE
FCKout <= 1'b1;
end 1: begin // ACT
FCKout <= !(IS==5 || IS==6);
end 2: begin // RD
FCKout <= 1'b1;
end 3: begin // NOP CKE
FCKout <= !(IS==5 || IS==6);
end 4: begin // NOP CKE
FCKout <= 1'b1;
end 5: begin // NOP CKE
FCKout <= !(IS==5 || IS==6);
end 6: begin // NOP CKE
FCKout <= 1'b1;
end 7: begin // NOP CKE
FCKout <= !(IS==5 || IS==6 || (!RestoreDone && SetENRestore && (SPITX0SEL || SPITX1SEL)));
end 8: begin // WR AP
FCKout <= 1'b1;
end 9: begin // NOP CKE
FCKout <= !(IS==5);
end 10: begin // PC all
FCKout <= 1'b1;
end 11: begin // AREF
FCKout <= !(IS==5);
end 12: begin // NOP CKE
FCKout <= 1'b1;
end 13: begin // NOP CKE
FCKout <= !(IS==5);
end 14: begin // NOP CKE
FCKout <= 1'b1;
end 15: begin // NOP CKE
FCKout <= !(IS==5);
end
0: FCKout <= 1'b1; // NOP CKE
1: FCKout <= !(IS==5 || IS==6); // ACT
2: FCKout <= 1'b1; // RD
3: FCKout <= !(IS==5 || IS==6); // NOP CKE
4: FCKout <= 1'b1; // NOP CKE
5: FCKout <= !(IS==5 || IS==6); // NOP CKE
6: FCKout <= 1'b1; // NOP CKE
7: FCKout <= !(IS==5 || IS==6 || SPITXSEL); // NOP CKE
8: FCKout <= 1'b1; // WR AP
9: FCKout <= !(IS==5); // NOP CKE
10: FCKout <= 1'b1; // PC all
11: FCKout <= !(IS==5); // AREF
12: FCKout <= 1'b1; // NOP CKE
13: FCKout <= !(IS==5); // NOP CKE
14: FCKout <= 1'b1; // NOP CKE
15: FCKout <= !(IS==5); // NOP CKE
endcase
nFCS <= !(IS==4 || IS==5 || IS==6);
MOSIOE <= IS==5;
nFCS <= !(IS==4 || IS==5 || IS==6 || FCS);
MOSIOE <= IS==5 || (IS==7 && SetENRestore && !RestoreDone);
end
/* SPI flash MOSI control */
reg MOSIout = 0;
always @(posedge C25M) begin
case (PS[3:0])
1: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 7
3'h4: MOSIout <= 1'b0; // Address bit 23
3'h5: MOSIout <= 1'b0; // Address bit 15
3'h6: MOSIout <= 1'b0; // Address bit 7
default MOSIout <= 1'b0;
endcase
end 3: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 6
3'h4: MOSIout <= 1'b0; // Address bit 22
3'h5: MOSIout <= SetROM[1]; // Address bit 14
3'h6: MOSIout <= 1'b0; // Address bit 6
default MOSIout <= 1'b0;
endcase
end 5: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 5
3'h4: MOSIout <= 1'b0; // Address bit 21
3'h5: MOSIout <= SetROM[0]; // Address bit 13
3'h6: MOSIout <= 1'b0; // Address bit 5
default MOSIout <= 1'b0;
endcase
end 7: begin
if (nRESout) case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 4
3'h4: MOSIout <= 1'b0; // Address bit 20
3'h5: MOSIout <= 1'b0; // Address bit 12
3'h6: MOSIout <= 1'b0; // Address bit 4
default MOSIout <= 1'b0;
1: case (LS[1:0])
2'h3: MOSIout <= 1'b0; // Command bit 7
2'h0: MOSIout <= 1'b0; // Address bit 23
2'h1: MOSIout <= 1'b0; // Address bit 15
2'h2: MOSIout <= 1'b0; // Address bit 7
endcase 3: case (LS[1:0])
2'h3: MOSIout <= 1'b0; // Command bit 6
2'h0: MOSIout <= 1'b0; // Address bit 22
2'h1: MOSIout <= SetROM[1]; // Address bit 14
2'h2: MOSIout <= 1'b0; // Address bit 6
endcase 5: case (LS[1:0])
2'h3: MOSIout <= 1'b1; // Command bit 5
2'h0: MOSIout <= 1'b0; // Address bit 21
2'h1: MOSIout <= SetROM[0]; // Address bit 13
2'h2: MOSIout <= 1'b0; // Address bit 5
endcase 7: begin
if (!nRESout) case (LS[1:0])
2'h3: MOSIout <= 1'b1; // Command bit 4
2'h0: MOSIout <= 1'b0; // Address bit 20
2'h1: MOSIout <= 1'b0; // Address bit 12
2'h2: MOSIout <= 1'b0; // Address bit 4
endcase else MOSIout <= RA[0];
end 9: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 3
3'h4: MOSIout <= 1'b0; // Address bit 19
3'h5: MOSIout <= 1'b0; // Address bit 11
3'h6: MOSIout <= 1'b0; // Address bit 3
default MOSIout <= 1'b0;
endcase
end 11: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 2
3'h4: MOSIout <= 1'b0; // Address bit 18
3'h5: MOSIout <= 1'b0; // Address bit 10
3'h6: MOSIout <= 1'b0; // Address bit 2
default MOSIout <= 1'b0;
endcase
end 13: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 1
3'h4: MOSIout <= 1'b0; // Address bit 16
3'h5: MOSIout <= 1'b0; // Address bit 9
3'h6: MOSIout <= 1'b0; // Address bit 1
default MOSIout <= 1'b0;
endcase
end 15: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 0
3'h4: MOSIout <= 1'b0; // Address bit 15
3'h5: MOSIout <= 1'b0; // Address bit 7
3'h6: MOSIout <= 1'b0; // Address bit 0
default MOSIout <= 1'b0;
endcase
end
end 9: case (LS[1:0])
2'h3: MOSIout <= 1'b1; // Command bit 3
2'h0: MOSIout <= 1'b0; // Address bit 19
2'h1: MOSIout <= 1'b0; // Address bit 11
2'h2: MOSIout <= 1'b0; // Address bit 3
endcase 11: case (LS[1:0])
2'h3: MOSIout <= 1'b0; // Command bit 2
2'h0: MOSIout <= 1'b0; // Address bit 18
2'h1: MOSIout <= 1'b0; // Address bit 10
2'h2: MOSIout <= 1'b0; // Address bit 2
endcase 13: case (LS[1:0])
2'h3: MOSIout <= 1'b1; // Command bit 1
2'h0: MOSIout <= 1'b0; // Address bit 16
2'h1: MOSIout <= 1'b0; // Address bit 9
2'h2: MOSIout <= 1'b0; // Address bit 1
endcase 15: case (LS[1:0])
2'h3: MOSIout <= 1'b1; // Command bit 0
2'h0: MOSIout <= 1'b0; // Address bit 15
2'h1: MOSIout <= 1'b0; // Address bit 7
2'h2: MOSIout <= 1'b0; // Address bit 0
endcase
endcase
end
@ -331,7 +312,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE / NOP CKD
RCKE <= PSStart && (IS==6 || (IS==7 && CXXXr));
RCKE <= PSStart && (IS==6 || (IS==7 && RAMROMSpecSELr));
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
@ -445,7 +426,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
SA[12:0] <= { 10'b0011000100, LS[12:10] };
end else if (nIOSEL && nIOSTRB) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
SA[12:10] <= SetEN24bit ? { Addr[23], Addr[21:20] } : 3'b000;
SA[12:10] <= SetEN24bit ? { 1'b0, Addr[21:20] } : 3'b000;
SA[9:0] <= Addr[19:10];
end else if (!nIOSTRB) begin
SBA[1:0] <= 2'b10;
@ -462,7 +443,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
DQMH <= !Addr[0];
end else begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, RA[9:1]};
SA[12:0] <= { 4'b0011, RA[9:5], RA4, RA[3:1]};
DQML <= RA[0];
DQMH <= !RA[0];
end
@ -495,12 +476,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
if (IS==6) begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, LS[9:1] };
DQML <= LS[0];
DQML <= LS[0];
DQMH <= !LS[0];
end else begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQML <= Addr[0];
DQMH <= !Addr[0];
end
end 9: begin // NOP CKE
@ -550,9 +531,10 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
/* Unused Pins */
output RAdir = 1;
output nDMAout = 1;
output nNMIout = 1;
output nINHout = 1;
output nRDYout = 1;
output nIRQout = 1;
output RWout = 1;
/* Grounds next to PU */
output GNDout1 = 0;
output GNDout2 = 0;
endmodule

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@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677601285636 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677601285638 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 28 11:21:25 2023 " "Processing started: Tue Feb 28 11:21:25 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677601285638 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1677601285638 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1677601285639 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1677601285947 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1677601286047 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1677601286058 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13100 " "Peak virtual memory: 13100 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601286355 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:26 2023 " "Processing ended: Tue Feb 28 11:21:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601286355 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601286355 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601286355 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1677601286355 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681561246026 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681561246026 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 15 08:20:45 2023 " "Processing started: Sat Apr 15 08:20:45 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681561246026 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1681561246026 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1681561246026 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1681561246292 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1681561246340 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1681561246356 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13059 " "Peak virtual memory: 13059 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681561246593 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 15 08:20:46 2023 " "Processing ended: Sat Apr 15 08:20:46 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681561246593 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681561246593 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681561246593 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1681561246593 ""}

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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="GR8RAM">
</PROJECT>
</LOG_ROOT>

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cpld/db/GR8RAM.fit.qmsg
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@ -1,44 +1,41 @@
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1677601279685 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1677601279686 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1677601279701 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1677601279826 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1677601279827 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1677601280022 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1677601280063 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1677601280624 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 80 " "No exact pin location assignment(s) for 1 pins of 80 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1677601280753 ""}
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1677601280874 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1677601280923 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1677601280925 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1677601280925 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1677601280925 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1677601280925 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1677601280925 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1677601280945 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1677601280946 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1677601280959 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1677601280992 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1677601280992 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1677601280992 ""} } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1677601280992 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/22.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/22.1std/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/intelfpga_lite/22.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/22.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 9 -1 0 } } { "temporary_test_loc" "" { Generic "//mac/iCloud/Repos2/GR8RAM/cpld2/" { { 0 { 0 ""} 0 418 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1677601280992 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 94 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1677601280993 ""} } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1677601280993 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1677601280994 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1677601281004 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1677601281114 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1677601281203 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1677601281204 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1677601281205 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1677601281205 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 1 0 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 1 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1677601281234 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1677601281234 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1677601281234 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1677601281236 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 41 1 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1677601281236 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1677601281236 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1677601281236 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601281325 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1677601281341 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1677601281559 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601281888 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1677601281913 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1677601282469 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601282469 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1677601282537 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "30 " "Router estimated average interconnect usage is 30% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "30 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//mac/iCloud/Repos2/GR8RAM/cpld2/" { { 1 { 0 "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1677601282887 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1677601282887 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1677601282982 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1677601282982 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1677601282982 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601282986 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1677601283019 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601283056 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1677601283164 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1677601283280 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13746 " "Peak virtual memory: 13746 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601283368 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:23 2023 " "Processing ended: Tue Feb 28 11:21:23 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601283368 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601283368 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601283368 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1677601283368 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1681561242097 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1681561242097 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1681561242097 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681561242166 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681561242166 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1681561242338 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1681561242354 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681561242767 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681561242767 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681561242767 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681561242767 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681561242767 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1681561242767 ""}
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1681561242878 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1681561242893 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681561242893 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681561242893 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681561242893 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681561242893 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1681561242893 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681561242901 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681561242901 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681561242901 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681561242917 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681561242917 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r\[0\] " "Destination \"PHI0r\[0\]\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681561242917 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681561242917 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681561242917 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "temporary_test_loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 419 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1681561242917 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 91 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681561242917 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "AddrIncH " "Destination \"AddrIncH\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 117 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681561242917 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "AddrIncM " "Destination \"AddrIncM\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 116 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681561242917 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "AddrIncL " "Destination \"AddrIncL\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 115 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681561242917 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681561242917 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681561242933 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1681561242933 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1681561242964 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1681561243013 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1681561243013 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1681561243013 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1681561243013 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681561243091 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1681561243102 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1681561243235 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681561243454 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1681561243454 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1681561243941 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681561243941 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1681561243988 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "30 " "Router estimated average interconnect usage is 30% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "30 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1681561244210 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1681561244210 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1681561244272 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1681561244272 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1681561244272 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681561244272 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.21 " "Total time spent on timing analysis during the Fitter is 0.21 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1681561244288 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681561244304 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1681561244350 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1681561244414 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13737 " "Peak virtual memory: 13737 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681561244461 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 15 08:20:44 2023 " "Processing ended: Sat Apr 15 08:20:44 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681561244461 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681561244461 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681561244461 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1681561244461 ""}

291
cpld/db/GR8RAM.hier_info
View File

@ -31,11 +31,9 @@ C25M => WRD[5].CLK
C25M => WRD[6].CLK
C25M => WRD[7].CLK
C25M => MOSIout.CLK
C25M => FCKOE.CLK
C25M => MOSIOE.CLK
C25M => FCS.CLK
C25M => nFCS~reg0.CLK
C25M => FCKout.CLK
C25M => Bank.CLK
C25M => AddrIncH.CLK
C25M => AddrIncM.CLK
C25M => AddrIncL.CLK
@ -63,9 +61,8 @@ C25M => Addr[20].CLK
C25M => Addr[21].CLK
C25M => Addr[22].CLK
C25M => Addr[23].CLK
C25M => IOROMEN.CLK
C25M => nIOSTRBr.CLK
C25M => REGEN.CLK
C25M => IOROMEN.CLK
C25M => nRESout~reg0.CLK
C25M => LS[0].CLK
C25M => LS[1].CLK
@ -85,16 +82,10 @@ C25M => PS[0].CLK
C25M => PS[1].CLK
C25M => PS[2].CLK
C25M => PS[3].CLK
C25M => SetFWr[0].CLK
C25M => SetFWr[1].CLK
C25M => SetFWLoaded.CLK
C25M => nRESr.CLK
C25M => nRESf[0].CLK
C25M => nRESf[1].CLK
C25M => nRESf[2].CLK
C25M => nRESf[3].CLK
C25M => PHI0r2.CLK
C25M => PHI0r1.CLK
C25M => PHI0r[0].CLK
C25M => PHI0r[1].CLK
C25M => PHI0r[2].CLK
C25M => IS~7.DATAIN
C25M => RDD[0].CLK
C25M => RDD[1].CLK
@ -104,65 +95,151 @@ C25M => RDD[4].CLK
C25M => RDD[5].CLK
C25M => RDD[6].CLK
C25M => RDD[7].CLK
PHI0 => comb.IN1
PHI0 => nWEr.CLK
PHI0 => RAr[0].CLK
PHI0 => RAr[1].CLK
PHI0 => RAr[2].CLK
PHI0 => RAr[3].CLK
PHI0 => RAr[4].CLK
PHI0 => RAr[5].CLK
PHI0 => RAr[6].CLK
PHI0 => RAr[7].CLK
PHI0 => RAr[8].CLK
PHI0 => RAr[9].CLK
PHI0 => RAr[10].CLK
PHI0 => RAr[11].CLK
PHI0 => CXXXr.CLK
PHI0 => PHI0r1.DATAIN
nRES => nRESf[0].DATAIN
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
SetFW[0] => SetFWr[0].DATAIN
SetFW[1] => SetFWr[1].DATAIN
PHI0 => comb.IN0
PHI0 => RAMROMSpecSELr.CLK
PHI0 => PHI0r[0].DATAIN
PHI0 => Slot[0].CLK
PHI0 => Slot[1].CLK
PHI0 => Slot[2].CLK
PHI0 => SlotKnown.CLK
PHI0 => FCS.CLK
PHI0 => Bank.CLK
PHI0 => RestoreDone.CLK
nRES => nRESr.DATAIN
nRESout << nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
SetFW[0] => Mux1.IN3
SetFW[0] => Equal1.IN1
SetFW[1] => RAMExists.IN1
SetFW[1] => RDD.OUTPUTSELECT
SetFW[1] => RDD.OUTPUTSELECT
SetFW[1] => RDD.OUTPUTSELECT
SetFW[1] => RDD.OUTPUTSELECT
SetFW[1] => SA.OUTPUTSELECT
SetFW[1] => SA.OUTPUTSELECT
SetFW[1] => SBA.OUTPUTSELECT
SetFW[1] => MOSIout.DATAB
SetFW[1] => Equal1.IN0
INTin => INTout.DATAIN
INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
INTout << INTin.DB_MAX_OUTPUT_PORT_TYPE
DMAin => DMAout.DATAIN
DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE
nNMIout <= <VCC>
nIRQout <= <VCC>
nRDYout <= <VCC>
nINHout <= <VCC>
RWout <= <VCC>
nDMAout <= <VCC>
RA[0] => RAr[0].DATAIN
RA[0] => Equal16.IN10
RA[1] => RAr[1].DATAIN
RA[1] => Equal16.IN9
RA[2] => RAr[2].DATAIN
RA[2] => Equal16.IN8
RA[3] => RAr[3].DATAIN
RA[3] => Equal16.IN7
RA[4] => RAr[4].DATAIN
RA[4] => Equal16.IN6
RA[5] => RAr[5].DATAIN
RA[5] => Equal16.IN5
RA[6] => RAr[6].DATAIN
RA[6] => Equal16.IN4
RA[7] => RAr[7].DATAIN
RA[7] => Equal16.IN3
RA[8] => RAr[8].DATAIN
DMAout << DMAin.DB_MAX_OUTPUT_PORT_TYPE
GNDout1 << <GND>
GNDout2 << <GND>
nIRQout << <VCC>
RWout << <VCC>
nDMAout << <VCC>
RA[0] => Mux11.IN16
RA[0] => Mux12.IN17
RA[0] => Mux13.IN17
RA[0] => Mux14.IN17
RA[0] => Mux15.IN16
RA[0] => Mux16.IN16
RA[0] => Mux17.IN16
RA[0] => Mux18.IN16
RA[0] => DQML.DATAA
RA[0] => MOSIout.DATAB
RA[0] => Equal8.IN3
RA[0] => Equal9.IN3
RA[0] => Equal10.IN2
RA[0] => Equal11.IN1
RA[0] => Equal12.IN3
RA[0] => Equal13.IN0
RA[0] => Equal14.IN3
RA[0] => Equal18.IN10
RA[0] => DQMH.DATAA
RA[1] => Mux11.IN15
RA[1] => Mux12.IN16
RA[1] => Mux13.IN16
RA[1] => Mux14.IN16
RA[1] => Mux15.IN15
RA[1] => Mux16.IN15
RA[1] => Mux17.IN15
RA[1] => Mux18.IN15
RA[1] => SA.DATAA
RA[1] => Equal8.IN2
RA[1] => Equal9.IN2
RA[1] => Equal10.IN3
RA[1] => Equal11.IN0
RA[1] => Equal12.IN0
RA[1] => Equal13.IN3
RA[1] => Equal14.IN2
RA[1] => Equal18.IN9
RA[2] => Mux11.IN14
RA[2] => Mux12.IN15
RA[2] => Mux13.IN15
RA[2] => Mux14.IN15
RA[2] => Mux15.IN14
RA[2] => Mux16.IN14
RA[2] => Mux17.IN14
RA[2] => Mux18.IN14
RA[2] => SA.DATAA
RA[2] => Equal8.IN1
RA[2] => Equal9.IN1
RA[2] => Equal10.IN1
RA[2] => Equal11.IN3
RA[2] => Equal12.IN2
RA[2] => Equal13.IN2
RA[2] => Equal14.IN1
RA[2] => Equal18.IN8
RA[3] => Mux11.IN13
RA[3] => Mux12.IN14
RA[3] => Mux13.IN14
RA[3] => Mux14.IN14
RA[3] => Mux15.IN13
RA[3] => Mux16.IN13
RA[3] => Mux17.IN13
RA[3] => Mux18.IN13
RA[3] => SA.DATAA
RA[3] => Equal8.IN0
RA[3] => Equal9.IN0
RA[3] => Equal10.IN0
RA[3] => Equal11.IN2
RA[3] => Equal12.IN1
RA[3] => Equal13.IN1
RA[3] => Equal14.IN0
RA[3] => Equal18.IN7
RA[4] => RA4.IN0
RA[4] => Equal18.IN6
RA[5] => SA.DATAA
RA[5] => Equal18.IN5
RA[6] => SA.DATAA
RA[6] => Equal18.IN4
RA[7] => comb.IN1
RA[7] => SA.DATAA
RA[7] => Equal18.IN3
RA[8] => Equal16.IN2
RA[9] => RAr[9].DATAIN
RA[8] => SA.DATAA
RA[8] => Equal15.IN7
RA[8] => Equal18.IN2
RA[8] => Slot[0].DATAIN
RA[9] => Equal16.IN1
RA[10] => RAr[10].DATAIN
RA[9] => SA.DATAA
RA[9] => Equal15.IN6
RA[9] => Equal18.IN1
RA[9] => Slot[1].DATAIN
RA[10] => Equal16.IN0
RA[11] => RAr[11].DATAIN
RA[12] => Equal8.IN1
RA[13] => Equal8.IN0
RA[14] => Equal8.IN3
RA[15] => Equal8.IN2
RA[10] => SA.DATAA
RA[10] => Equal15.IN5
RA[10] => Equal18.IN0
RA[10] => Slot[2].DATAIN
RA[11] => comb.IN1
RA[11] => Equal15.IN4
RA[11] => comb.IN1
RA[12] => Equal15.IN3
RA[12] => Equal17.IN3
RA[13] => Equal15.IN2
RA[13] => Equal17.IN2
RA[14] => Equal15.IN1
RA[14] => Equal17.IN1
RA[15] => Equal15.IN0
RA[15] => Equal17.IN0
PU => RA4.IN1
nWE => comb.IN1
nWE => nWEr.DATAIN
nWE => RCKE.IN1
nWE => always12.IN1
nWE => always9.IN1
nWE => always9.IN1
nWE => always9.IN1
RD[0] <> RD[0]
RD[1] <> RD[1]
RD[2] <> RD[2]
@ -171,39 +248,54 @@ RD[4] <> RD[4]
RD[5] <> RD[5]
RD[6] <> RD[6]
RD[7] <> RD[7]
RAdir <= <VCC>
RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
nIOSEL => comb.IN0
nIOSEL => always7.IN1
RAdir << <VCC>
RDdir << comb.DB_MAX_OUTPUT_PORT_TYPE
nIOSEL => always18.IN0
nIOSEL => IOROMEN.OUTPUTSELECT
nIOSEL => comb.IN1
nIOSEL => always8.IN1
nIOSEL => Slot[0].ENA
nIOSEL => Slot[1].ENA
nIOSEL => Slot[2].ENA
nIOSEL => SlotKnown.ENA
nDEVSEL => RDD.OUTPUTSELECT
nDEVSEL => RDD.OUTPUTSELECT
nDEVSEL => RDD.OUTPUTSELECT
nDEVSEL => RDD.OUTPUTSELECT
nDEVSEL => RDD.OUTPUTSELECT
nDEVSEL => RDD.OUTPUTSELECT
nDEVSEL => RDD.OUTPUTSELECT
nDEVSEL => RDD.OUTPUTSELECT
nDEVSEL => comb.IN1
nDEVSEL => RAMSEL.IN1
nDEVSEL => comb.IN1
nDEVSEL => RAMRegSEL.IN1
nIOSTRB => nIOSTRBr.DATAIN
nDEVSEL => comb.IN1
nIOSTRB => always18.IN1
nIOSTRB => comb.IN1
nIOSTRB => comb.IN1
SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE
DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE
RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
nIOSTRB => SA.OUTPUTSELECT
nIOSTRB => SA.DATAA
nIOSTRB => IOROMRES.IN1
SBA[0] << SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SBA[1] << SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[0] << SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[1] << SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[2] << SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[3] << SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[4] << SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[5] << SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[6] << SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[7] << SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[8] << SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[9] << SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[10] << SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[11] << SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[12] << SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRCS << nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRAS << nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nCAS << nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nSWE << nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
DQML << DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE
DQMH << DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE
RCKE << RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
SD[0] <> SD[0]
SD[1] <> SD[1]
SD[2] <> SD[2]
@ -212,9 +304,10 @@ SD[4] <> SD[4]
SD[5] <> SD[5]
SD[6] <> SD[6]
SD[7] <> SD[7]
nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE
FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE
nFCS << nFCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
FCK << FCKout.DB_MAX_OUTPUT_PORT_TYPE
MISO => WRD.DATAB
MISO => Mux11.IN19
MOSI <> MOSI

BIN
cpld/db/GR8RAM.hif
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Binary file not shown.

BIN
cpld/db/GR8RAM.lpc.rdb
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Binary file not shown.

BIN
cpld/db/GR8RAM.map.cdb
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BIN
cpld/db/GR8RAM.map.hdb
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38
cpld/db/GR8RAM.map.qmsg
View File

@ -1,19 +1,19 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677601254100 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677601254102 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 28 11:20:53 2023 " "Processing started: Tue Feb 28 11:20:53 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677601254102 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677601254102 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677601254103 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1677601254505 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1677601254505 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(110) " "Verilog HDL warning at gr8ram.v(110): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 110 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1677601274977 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(286) " "Verilog HDL warning at gr8ram.v(286): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 286 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1677601274981 ""}
{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677601274993 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1677601274993 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1677601275007 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(42) " "Verilog HDL assignment warning at gr8ram.v(42): truncated value with size 32 to match size of target (4)" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275027 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 gr8ram.v(47) " "Verilog HDL assignment warning at gr8ram.v(47): truncated value with size 32 to match size of target (14)" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275028 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(134) " "Verilog HDL assignment warning at gr8ram.v(134): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 134 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275033 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(142) " "Verilog HDL assignment warning at gr8ram.v(142): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 142 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275033 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(149) " "Verilog HDL assignment warning at gr8ram.v(149): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 149 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275034 "|GR8RAM"}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 563 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 566 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 565 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 564 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 567 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 562 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 561 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1677601275953 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 " "3 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1677601276221 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "333 " "Implemented 333 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1677601276250 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1677601276250 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1677601276250 ""} { "Info" "ICUT_CUT_TM_LCELLS" "253 " "Implemented 253 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1677601276250 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1677601276250 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg " "Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677601276457 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13114 " "Peak virtual memory: 13114 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601276495 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:16 2023 " "Processing ended: Tue Feb 28 11:21:16 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601276495 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Elapsed time: 00:00:23" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601276495 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601276495 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1677601276495 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681561218013 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681561218029 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 15 08:20:17 2023 " "Processing started: Sat Apr 15 08:20:17 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681561218029 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681561218029 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681561218029 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1681561218818 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1681561218818 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 110 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681561238232 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(250) " "Verilog HDL warning at GR8RAM.v(250): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 250 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681561238232 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1681561238232 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681561238232 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1681561238284 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(33) " "Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 33 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681561238284 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(38) " "Verilog HDL assignment warning at GR8RAM.v(38): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 38 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681561238284 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(129) " "Verilog HDL assignment warning at GR8RAM.v(129): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 129 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681561238284 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(137) " "Verilog HDL assignment warning at GR8RAM.v(137): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 137 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681561238284 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(144) " "Verilog HDL assignment warning at GR8RAM.v(144): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 144 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681561238284 "|GR8RAM"}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "GNDout1 GND " "Pin \"GNDout1\" is stuck at GND" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 538 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681561238861 "|GR8RAM|GNDout1"} { "Warning" "WMLS_MLS_STUCK_PIN" "GNDout2 GND " "Pin \"GNDout2\" is stuck at GND" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681561238861 "|GR8RAM|GNDout2"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 534 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681561238861 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 535 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681561238861 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 533 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681561238861 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 532 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681561238861 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[12\] GND " "Pin \"SA\[12\]\" is stuck at GND" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 414 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681561238861 "|GR8RAM|SA[12]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1681561238861 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 " "3 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1681561239297 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "29 " "Implemented 29 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1681561239338 ""} { "Info" "ICUT_CUT_TM_OPINS" "34 " "Implemented 34 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1681561239338 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1681561239338 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1681561239338 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1681561239338 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681561239484 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13095 " "Peak virtual memory: 13095 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681561239514 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 15 08:20:39 2023 " "Processing ended: Sat Apr 15 08:20:39 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681561239514 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Elapsed time: 00:00:22" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681561239514 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:42 " "Total CPU time (on all processors): 00:00:42" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681561239514 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1681561239514 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677601288128 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677601288129 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 28 11:21:27 2023 " "Processing started: Tue Feb 28 11:21:27 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677601288129 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1677601288129 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1677601288130 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1677601288250 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1677601288411 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1677601288411 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601288455 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601288455 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1677601288513 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1677601288921 ""}
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1677601289007 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1677601289045 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1677601289084 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 10.278 " "Worst-case setup slack is 10.278" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 10.278 0.000 C25M " " 10.278 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289092 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289092 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.376 " "Worst-case hold slack is 1.376" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289097 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289097 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.376 0.000 C25M " " 1.376 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289097 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289097 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.311 " "Worst-case recovery slack is 33.311" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.311 0.000 C25M " " 33.311 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289104 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289104 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.135 " "Worst-case removal slack is 6.135" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.135 0.000 C25M " " 6.135 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289109 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289109 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289113 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289113 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1677601289175 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677601289198 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677601289201 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13081 " "Peak virtual memory: 13081 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601289276 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:29 2023 " "Processing ended: Tue Feb 28 11:21:29 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601289276 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601289276 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601289276 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1677601289276 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681561248233 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681561248242 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 15 08:20:47 2023 " "Processing started: Sat Apr 15 08:20:47 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681561248242 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1681561248242 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1681561248242 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1681561248360 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1681561248512 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1681561248512 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681561248555 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681561248555 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1681561248601 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1681561249057 ""}
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1681561249132 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1681561249150 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1681561249166 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 11.915 " "Worst-case setup slack is 11.915" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249182 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249182 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 11.915 0.000 C25M " " 11.915 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249182 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 483.193 0.000 PHI0 " " 483.193 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249182 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681561249182 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.411 " "Worst-case hold slack is 1.411" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249182 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249182 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.411 0.000 C25M " " 1.411 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249182 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.670 0.000 PHI0 " " 2.670 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249182 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681561249182 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.174 " "Worst-case recovery slack is 33.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249198 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249198 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.174 0.000 C25M " " 33.174 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249198 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 973.979 0.000 PHI0 " " 973.979 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249198 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681561249198 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.467 " "Worst-case removal slack is 3.467" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249198 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249198 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.467 0.000 PHI0 " " 3.467 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249198 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.272 0.000 C25M " " 6.272 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249198 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681561249198 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249198 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249198 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249198 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681561249198 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681561249198 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1681561249261 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681561249281 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681561249281 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13055 " "Peak virtual memory: 13055 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681561249343 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 15 08:20:49 2023 " "Processing ended: Sat Apr 15 08:20:49 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681561249343 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681561249343 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681561249343 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1681561249343 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681461688556 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681461688556 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 04:41:28 2023 " "Processing started: Fri Apr 14 04:41:28 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681461688556 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681461688556 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681461688556 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1681461689406 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1681461689406 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 110 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681461707137 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(250) " "Verilog HDL warning at GR8RAM.v(250): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 250 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681461707137 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1681461707137 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681461707137 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1681461707184 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(33) " "Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 33 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681461707184 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(38) " "Verilog HDL assignment warning at GR8RAM.v(38): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 38 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681461707184 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(129) " "Verilog HDL assignment warning at GR8RAM.v(129): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 129 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681461707195 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(137) " "Verilog HDL assignment warning at GR8RAM.v(137): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 137 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681461707195 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(144) " "Verilog HDL assignment warning at GR8RAM.v(144): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 144 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681461707195 "|GR8RAM"}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "GNDout1 GND " "Pin \"GNDout1\" is stuck at GND" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 538 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681461707759 "|GR8RAM|GNDout1"} { "Warning" "WMLS_MLS_STUCK_PIN" "GNDout2 GND " "Pin \"GNDout2\" is stuck at GND" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681461707759 "|GR8RAM|GNDout2"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 534 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681461707759 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 535 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681461707759 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 533 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681461707759 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 532 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681461707759 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[12\] GND " "Pin \"SA\[12\]\" is stuck at GND" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 414 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681461707759 "|GR8RAM|SA[12]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1681461707759 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 " "3 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1681461708175 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "29 " "Implemented 29 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1681461708206 ""} { "Info" "ICUT_CUT_TM_OPINS" "34 " "Implemented 34 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1681461708206 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1681461708206 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1681461708206 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1681461708206 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681461708340 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13096 " "Peak virtual memory: 13096 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681461708371 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 04:41:48 2023 " "Processing ended: Fri Apr 14 04:41:48 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681461708371 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Elapsed time: 00:00:20" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681461708371 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681461708371 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1681461708371 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1681461710173 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681461710189 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 04:41:49 2023 " "Processing started: Fri Apr 14 04:41:49 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681461710189 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1681461710189 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1681461710189 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1681461710821 ""}
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1681461710821 ""}
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1681461710821 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1681461710915 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1681461710915 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1681461710915 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681461710978 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681461710978 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1681461711167 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1681461711198 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681461711655 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681461711655 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681461711655 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681461711655 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681461711655 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1681461711655 ""}
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1681461711737 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1681461711751 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681461711751 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681461711751 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681461711751 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681461711751 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1681461711751 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681461711767 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681461711767 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681461711767 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681461711783 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681461711783 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r\[0\] " "Destination \"PHI0r\[0\]\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681461711783 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681461711783 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681461711783 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "temporary_test_loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 420 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1681461711783 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 91 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681461711798 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "AddrIncH " "Destination \"AddrIncH\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 117 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681461711798 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "AddrIncM " "Destination \"AddrIncM\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 116 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681461711798 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "AddrIncL " "Destination \"AddrIncL\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 115 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681461711798 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681461711798 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681461711798 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1681461711798 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1681461711830 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1681461711877 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1681461711877 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1681461711877 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1681461711877 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681461711943 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1681461711943 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1681461712094 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681461712294 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1681461712294 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1681461712743 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681461712743 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1681461712792 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "30 " "Router estimated average interconnect usage is 30% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "30 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1681461712994 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1681461712994 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1681461713057 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1681461713057 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1681461713057 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681461713057 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.19 " "Total time spent on timing analysis during the Fitter is 0.19 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1681461713088 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681461713088 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1681461713137 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1681461713199 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13736 " "Peak virtual memory: 13736 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681461713247 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 04:41:53 2023 " "Processing ended: Fri Apr 14 04:41:53 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681461713247 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681461713247 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681461713247 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1681461713247 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1681461714742 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681461714757 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 04:41:54 2023 " "Processing started: Fri Apr 14 04:41:54 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681461714757 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1681461714757 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1681461714757 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1681461715009 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1681461715056 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1681461715072 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13059 " "Peak virtual memory: 13059 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681461715308 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 04:41:55 2023 " "Processing ended: Fri Apr 14 04:41:55 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681461715308 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681461715308 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681461715308 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1681461715308 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1681461716056 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1681461716909 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681461716925 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 04:41:56 2023 " "Processing started: Fri Apr 14 04:41:56 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681461716925 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1681461716925 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1681461716925 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1681461717035 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1681461717178 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1681461717178 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681461717223 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681461717223 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1681461717274 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1681461717649 ""}
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1681461717702 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1681461717717 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1681461717748 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 11.915 " "Worst-case setup slack is 11.915" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 11.915 0.000 C25M " " 11.915 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 483.193 0.000 PHI0 " " 483.193 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717750 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681461717750 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.411 " "Worst-case hold slack is 1.411" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.411 0.000 C25M " " 1.411 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.670 0.000 PHI0 " " 2.670 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717750 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681461717750 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.174 " "Worst-case recovery slack is 33.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.174 0.000 C25M " " 33.174 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 973.979 0.000 PHI0 " " 973.979 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717764 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681461717764 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.467 " "Worst-case removal slack is 3.467" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.467 0.000 PHI0 " " 3.467 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.272 0.000 C25M " " 6.272 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717764 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681461717764 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681461717764 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681461717764 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1681461717827 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681461717850 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681461717850 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13054 " "Peak virtual memory: 13054 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681461717909 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 04:41:57 2023 " "Processing ended: Fri Apr 14 04:41:57 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681461717909 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681461717909 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681461717909 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1681461717909 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 19 s " "Quartus Prime Full Compilation was successful. 0 errors, 19 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1681461718683 ""}

6
cpld/incremental_db/compiled_partitions/GR8RAM.db_info
View File

@ -1,3 +1,3 @@
Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Version_Index = 553882368
Creation_Time = Tue Feb 28 11:21:15 2023
Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Version_Index = 503488000
Creation_Time = Fri Apr 14 03:02:36 2023

BIN
cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
View File

Binary file not shown.

26
cpld/output_files/GR8RAM.asm.rpt
View File

@ -1,6 +1,6 @@
Assembler report for GR8RAM
Tue Feb 28 11:21:26 2023
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Sat Apr 15 08:20:46 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -10,7 +10,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof
5. Assembler Device Options: Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof
6. Assembler Messages
@ -18,7 +18,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
----------------
; Legal Notice ;
----------------
Copyright (C) 2022 Intel Corporation. All rights reserved.
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Feb 28 11:21:26 2023 ;
; Assembler Status ; Successful - Sat Apr 15 08:20:46 2023 ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
@ -58,17 +58,17 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------+
; File Name ;
+----------------------------------------------+
; /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof ;
; Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
+----------------------------------------------+
+------------------------------------------------------------------------+
; Assembler Device Options: /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof ;
; Assembler Device Options: Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
+----------------+-------------------------------------------------------+
; Option ; Setting ;
+----------------+-------------------------------------------------------+
; JTAG usercode ; 0x00163AA4 ;
; Checksum ; 0x00163E9C ;
; JTAG usercode ; 0x0016624C ;
; Checksum ; 0x0016664C ;
+----------------+-------------------------------------------------------+
@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Info: Processing started: Tue Feb 28 11:21:25 2023
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Sat Apr 15 08:20:45 2023
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13100 megabytes
Info: Processing ended: Tue Feb 28 11:21:26 2023
Info: Peak virtual memory: 13059 megabytes
Info: Processing ended: Sat Apr 15 08:20:46 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

2
cpld/output_files/GR8RAM.done
View File

@ -1 +1 @@
Tue Feb 28 11:21:32 2023
Sat Apr 15 08:20:50 2023

447
cpld/output_files/GR8RAM.fit.rpt
View File

@ -1,6 +1,6 @@
Fitter report for GR8RAM
Tue Feb 28 11:21:23 2023
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Sat Apr 15 08:20:44 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -18,27 +18,26 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
10. I/O Bank Usage
11. All Package Pins
12. Output Pin Default Load For Reported TCO
13. I/O Assignment Warnings
14. Fitter Resource Utilization by Entity
15. Delay Chain Summary
16. Control Signals
17. Global & Other Fast Signals
18. Routing Usage Summary
19. LAB Logic Elements
20. LAB-wide Signals
21. LAB Signals Sourced
22. LAB Signals Sourced Out
23. LAB Distinct Inputs
24. Fitter Device Options
25. Fitter Messages
26. Fitter Suppressed Messages
13. Fitter Resource Utilization by Entity
14. Delay Chain Summary
15. Control Signals
16. Global & Other Fast Signals
17. Routing Usage Summary
18. LAB Logic Elements
19. LAB-wide Signals
20. LAB Signals Sourced
21. LAB Signals Sourced Out
22. LAB Distinct Inputs
23. Fitter Device Options
24. Fitter Messages
25. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2022 Intel Corporation. All rights reserved.
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
@ -55,21 +54,21 @@ https://fpgasoftware.intel.com/eula.
+------------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+------------------------------------------------+
; Fitter Status ; Successful - Tue Feb 28 11:21:23 2023 ;
; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 233 / 240 ( 97 % ) ;
; Total pins ; 80 / 80 ( 100 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+------------------------------------------------+
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Sat Apr 15 08:20:44 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 232 / 240 ( 97 % ) ;
; Total pins ; 80 / 80 ( 100 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+---------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
@ -129,20 +128,20 @@ https://fpgasoftware.intel.com/eula.
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.02 ;
; Average used ; 1.03 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.7% ;
; Processors 3-4 ; 0.5% ;
; Processor 2 ; 1.1% ;
; Processors 3-4 ; 0.8% ;
+----------------------------+-------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin.
The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+---------------------------------------------------------------------+
@ -150,27 +149,27 @@ The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin.
+---------------------------------------------+-----------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------+
; Total logic elements ; 233 / 240 ( 97 % ) ;
; -- Combinational with no register ; 109 ;
; -- Register only ; 6 ;
; -- Combinational with a register ; 118 ;
; Total logic elements ; 232 / 240 ( 97 % ) ;
; -- Combinational with no register ; 124 ;
; -- Register only ; 4 ;
; -- Combinational with a register ; 104 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 124 ;
; -- 3 input functions ; 30 ;
; -- 2 input functions ; 71 ;
; -- 1 input functions ; 0 ;
; -- 4 input functions ; 123 ;
; -- 3 input functions ; 35 ;
; -- 2 input functions ; 67 ;
; -- 1 input functions ; 1 ;
; -- 0 input functions ; 2 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 200 ;
; -- normal mode ; 199 ;
; -- arithmetic mode ; 33 ;
; -- qfbk mode ; 18 ;
; -- qfbk mode ; 7 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 68 ;
; -- synchronous clear/load mode ; 53 ;
; -- asynchronous clear/load mode ; 29 ;
; ; ;
; Total registers ; 124 / 240 ( 52 % ) ;
; Total registers ; 108 / 240 ( 45 % ) ;
; Total LABs ; 24 / 24 ( 100 % ) ;
; Logic elements in carry chains ; 37 ;
; Virtual pins ; 0 ;
@ -185,12 +184,12 @@ The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin.
; Global signals ; 3 ;
; -- Global clocks ; 3 / 4 ( 75 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 34.1% / 35.6% / 32.6% ;
; Peak interconnect usage (total/H/V) ; 34.1% / 35.6% / 32.6% ;
; Maximum fan-out ; 110 ;
; Highest non-global fan-out ; 53 ;
; Total fan-out ; 1071 ;
; Average fan-out ; 3.42 ;
; Average interconnect usage (total/H/V) ; 33.3% / 35.1% / 31.5% ;
; Peak interconnect usage (total/H/V) ; 33.3% / 35.1% / 31.5% ;
; Maximum fan-out ; 100 ;
; Highest non-global fan-out ; 48 ;
; Total fan-out ; 1061 ;
; Average fan-out ; 3.40 ;
+---------------------------------------------+-----------------------+
@ -199,34 +198,35 @@ The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin.
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 110 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 100 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ; no ;
; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 2 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ; no ;
; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 11 ; 0 ; yes ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; PU ; 27 ; 1 ; 2 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; On ; 3.3-V LVTTL ; User ; no ;
; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; no ;
; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; On ; 3.3-V LVTTL ; User ; no ;
; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ;
; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ;
; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 3 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ;
; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 10 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ;
; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 14 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
@ -238,7 +238,9 @@ The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin.
; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; yes ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; yes ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; GNDout1 ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; GNDout2 ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
@ -246,29 +248,26 @@ The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin.
; RWout ; 33 ; 1 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[0] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[10] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[11] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; SA[12] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; SA[11] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[12] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[1] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[9] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SBA[0] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -279,22 +278,22 @@ The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin.
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; MOSIOE ; - ;
; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; comb~1 ; - ;
; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; comb~1 ; - ;
; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; comb~1 ; - ;
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; comb~1 ; - ;
; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; comb~1 ; - ;
; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ;
; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -313,7 +312,7 @@ The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin.
+----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
; 1 ; 83 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 1 ; 83 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 2 ; 0 ; 1 ; RA[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 3 ; 1 ; 1 ; RA[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 4 ; 2 ; 1 ; RA[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
@ -338,9 +337,9 @@ The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin.
; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 26 ; 20 ; 1 ; nNMIout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 27 ; 21 ; 1 ; nINHout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 28 ; 22 ; 1 ; nRDYout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 26 ; 20 ; 1 ; GNDout1 ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 27 ; 21 ; 1 ; PU ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 28 ; 22 ; 1 ; GNDout2 ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 29 ; 23 ; 1 ; nIRQout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 30 ; 24 ; 1 ; nRESout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
@ -433,21 +432,12 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+----------------------------------------+
; I/O Assignment Warnings ;
+----------+-----------------------------+
; Pin Name ; Reason ;
+----------+-----------------------------+
; RA[4] ; Missing location assignment ;
+----------+-----------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; |GR8RAM ; 233 (233) ; 124 ; 0 ; 80 ; 0 ; 109 (109) ; 6 (6) ; 118 (118) ; 37 (37) ; 18 (18) ; |GR8RAM ; GR8RAM ; work ;
; |GR8RAM ; 232 (232) ; 108 ; 0 ; 80 ; 0 ; 124 (124) ; 4 (4) ; 104 (104) ; 37 (37) ; 7 (7) ; |GR8RAM ; GR8RAM ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@ -460,10 +450,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; nRESout ; Output ; -- ;
; INTout ; Output ; -- ;
; DMAout ; Output ; -- ;
; nNMIout ; Output ; -- ;
; GNDout1 ; Output ; -- ;
; GNDout2 ; Output ; -- ;
; nIRQout ; Output ; -- ;
; nRDYout ; Output ; -- ;
; nINHout ; Output ; -- ;
; RWout ; Output ; -- ;
; nDMAout ; Output ; -- ;
; RAdir ; Output ; -- ;
@ -511,57 +500,61 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; MOSI ; Bidir ; (1) ;
; INTin ; Input ; (1) ;
; DMAin ; Input ; (1) ;
; SetFW[1] ; Input ; (1) ;
; nDEVSEL ; Input ; (1) ;
; nIOSTRB ; Input ; (1) ;
; nIOSEL ; Input ; (1) ;
; PHI0 ; Input ; (0) ;
; nWE ; Input ; (1) ;
; RA[0] ; Input ; (1) ;
; C25M ; Input ; (0) ;
; RA[1] ; Input ; (1) ;
; RA[2] ; Input ; (1) ;
; RA[3] ; Input ; (1) ;
; RA[0] ; Input ; (1) ;
; RA[4] ; Input ; (1) ;
; RA[7] ; Input ; (1) ;
; RA[5] ; Input ; (1) ;
; RA[6] ; Input ; (1) ;
; RA[7] ; Input ; (1) ;
; RA[8] ; Input ; (1) ;
; RA[9] ; Input ; (1) ;
; RA[10] ; Input ; (1) ;
; nIOSTRB ; Input ; (1) ;
; nIOSEL ; Input ; (1) ;
; nDEVSEL ; Input ; (1) ;
; C25M ; Input ; (0) ;
; RA[11] ; Input ; (1) ;
; PU ; Input ; (1) ;
; SetFW[0] ; Input ; (1) ;
; nRES ; Input ; (1) ;
; RA[14] ; Input ; (1) ;
; RA[15] ; Input ; (1) ;
; RA[12] ; Input ; (1) ;
; RA[13] ; Input ; (1) ;
; SetFW[1] ; Input ; (1) ;
; SetFW[0] ; Input ; (1) ;
; nRES ; Input ; (1) ;
; RA[11] ; Input ; (1) ;
; MISO ; Input ; (1) ;
+----------+----------+---------------+
+--------------------------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
; C25M ; PIN_64 ; 110 ; Clock ; yes ; Global Clock ; GCLK3 ;
; Equal20~0 ; LC_X2_Y4_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal2~1 ; LC_X2_Y1_N5 ; 16 ; Clock enable ; no ; -- ; -- ;
; FCKOE ; LC_X3_Y1_N1 ; 2 ; Output enable ; no ; -- ; -- ;
; IS~19 ; LC_X2_Y2_N7 ; 5 ; Clock enable ; no ; -- ; -- ;
; MOSIOE ; LC_X2_Y2_N8 ; 1 ; Output enable ; no ; -- ; -- ;
; PHI0 ; PIN_41 ; 16 ; Clock ; yes ; Global Clock ; GCLK2 ;
; PS[0] ; LC_X6_Y1_N1 ; 52 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ;
; PS[2] ; LC_X2_Y1_N2 ; 27 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; SDOE ; LC_X5_Y1_N4 ; 8 ; Output enable ; no ; -- ; -- ;
; SetFWLoaded ; LC_X4_Y2_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
; always9~2 ; LC_X7_Y3_N6 ; 8 ; Sync. load ; no ; -- ; -- ;
; always9~3 ; LC_X7_Y3_N7 ; 9 ; Sync. load ; no ; -- ; -- ;
; always9~4 ; LC_X6_Y3_N9 ; 9 ; Sync. load ; no ; -- ; -- ;
; comb~2 ; LC_X4_Y1_N8 ; 9 ; Output enable ; no ; -- ; -- ;
; nRESr ; LC_X3_Y1_N7 ; 30 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK1 ;
+-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
+----------------------------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+-------------+-------------+---------+-----------------------------------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-------------+-------------+---------+-----------------------------------------+--------+----------------------+------------------+
; C25M ; PIN_64 ; 100 ; Clock ; yes ; Global Clock ; GCLK3 ;
; Equal0~0 ; LC_X6_Y1_N2 ; 17 ; Clock enable ; no ; -- ; -- ;
; Equal1~0 ; LC_X5_Y2_N4 ; 1 ; Async. load ; no ; -- ; -- ;
; Equal22~0 ; LC_X2_Y3_N8 ; 8 ; Clock enable ; no ; -- ; -- ;
; IOROMRES~3 ; LC_X3_Y3_N1 ; 1 ; Async. clear ; no ; -- ; -- ;
; IS~19 ; LC_X2_Y2_N2 ; 5 ; Clock enable ; no ; -- ; -- ;
; MOSIOE ; LC_X2_Y1_N1 ; 1 ; Output enable ; no ; -- ; -- ;
; PHI0 ; PIN_41 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ;
; PS[0] ; LC_X5_Y1_N7 ; 47 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ;
; PS[2] ; LC_X6_Y1_N8 ; 28 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; RestoreDone ; LC_X5_Y2_N2 ; 4 ; Async. clear ; no ; -- ; -- ;
; SDOE ; LC_X7_Y1_N8 ; 8 ; Output enable ; no ; -- ; -- ;
; always12~3 ; LC_X5_Y2_N1 ; 3 ; Clock enable ; no ; -- ; -- ;
; always9~2 ; LC_X5_Y2_N5 ; 8 ; Sync. load ; no ; -- ; -- ;
; always9~3 ; LC_X5_Y2_N0 ; 9 ; Sync. load ; no ; -- ; -- ;
; always9~4 ; LC_X5_Y2_N6 ; 9 ; Sync. load ; no ; -- ; -- ;
; comb~1 ; LC_X5_Y1_N3 ; 8 ; Output enable ; no ; -- ; -- ;
; nIOSEL ; PIN_39 ; 14 ; Clock enable ; no ; -- ; -- ;
; nRESr ; LC_X6_Y1_N3 ; 30 ; Async. clear, Clock enable, Sync. clear ; yes ; Global Clock ; GCLK1 ;
+-------------+-------------+---------+-----------------------------------------+--------+----------------------+------------------+
+-------------------------------------------------------------------------+
@ -569,9 +562,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------+-------------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-------+-------------+---------+----------------------+------------------+
; C25M ; PIN_64 ; 110 ; Global Clock ; GCLK3 ;
; PHI0 ; PIN_41 ; 16 ; Global Clock ; GCLK2 ;
; nRESr ; LC_X3_Y1_N7 ; 30 ; Global Clock ; GCLK1 ;
; C25M ; PIN_64 ; 100 ; Global Clock ; GCLK3 ;
; PHI0 ; PIN_41 ; 11 ; Global Clock ; GCLK2 ;
; nRESr ; LC_X6_Y1_N3 ; 30 ; Global Clock ; GCLK1 ;
+-------+-------------+---------+----------------------+------------------+
@ -580,20 +573,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------+--------------------+
; Routing Resource Type ; Usage ;
+-----------------------+--------------------+
; C4s ; 211 / 784 ( 27 % ) ;
; Direct links ; 50 / 888 ( 6 % ) ;
; C4s ; 202 / 784 ( 26 % ) ;
; Direct links ; 37 / 888 ( 4 % ) ;
; Global clocks ; 3 / 4 ( 75 % ) ;
; LAB clocks ; 13 / 32 ( 41 % ) ;
; LUT chains ; 8 / 216 ( 4 % ) ;
; Local interconnects ; 379 / 888 ( 43 % ) ;
; R4s ; 199 / 704 ( 28 % ) ;
; LAB clocks ; 12 / 32 ( 38 % ) ;
; LUT chains ; 9 / 216 ( 4 % ) ;
; Local interconnects ; 393 / 888 ( 44 % ) ;
; R4s ; 200 / 704 ( 28 % ) ;
+-----------------------+--------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 9.71) ; Number of LABs (Total = 24) ;
; Number of Logic Elements (Average = 9.67) ; Number of LABs (Total = 24) ;
+--------------------------------------------+------------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
@ -601,55 +594,53 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 2 ;
; 10 ; 20 ;
; 7 ; 0 ;
; 8 ; 2 ;
; 9 ; 4 ;
; 10 ; 18 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.71) ; Number of LABs (Total = 24) ;
; LAB-wide Signals (Average = 1.96) ; Number of LABs (Total = 24) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 5 ;
; 1 Async. clear ; 6 ;
; 1 Clock ; 21 ;
; 1 Clock enable ; 5 ;
; 1 Sync. clear ; 4 ;
; 1 Sync. load ; 3 ;
; 2 Clocks ; 3 ;
; 1 Clock enable ; 7 ;
; 1 Sync. clear ; 5 ;
; 1 Sync. load ; 5 ;
; 2 Clock enables ; 1 ;
; 2 Clocks ; 2 ;
+------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 10.50) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 15 ;
; 11 ; 0 ;
; 12 ; 3 ;
; 13 ; 1 ;
; 14 ; 1 ;
; 15 ; 1 ;
+----------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 9.88) ; Number of LABs (Total = 24) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 2 ;
; 9 ; 4 ;
; 10 ; 15 ;
; 11 ; 1 ;
; 12 ; 2 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 7.42) ; Number of LABs (Total = 24) ;
; Number of Signals Sourced Out (Average = 6.75) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
@ -657,37 +648,35 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 3 ; 1 ;
; 4 ; 2 ;
; 5 ; 4 ;
; 6 ; 4 ;
; 7 ; 2 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 6 ;
; 11 ; 0 ;
; 12 ; 2 ;
; 6 ; 7 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 6 ;
; 10 ; 2 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 14.13) ; Number of LABs (Total = 24) ;
; Number of Distinct Inputs (Average = 14.33) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 6 ; 2 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 2 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 4 ;
; 15 ; 3 ;
; 10 ; 1 ;
; 11 ; 3 ;
; 12 ; 1 ;
; 13 ; 3 ;
; 14 ; 2 ;
; 15 ; 2 ;
; 16 ; 1 ;
; 17 ; 1 ;
; 18 ; 1 ;
@ -695,10 +684,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 20 ; 1 ;
; 21 ; 0 ;
; 22 ; 1 ;
; 23 ; 0 ;
; 24 ; 1 ;
; 25 ; 1 ;
; 26 ; 1 ;
; 23 ; 1 ;
; 24 ; 2 ;
+----------------------------------------------+------------------------------+
@ -732,7 +719,6 @@ Info (176444): Device migration not selected. If you intend to use device migrat
Info (176445): Device EPM570T100C5 is compatible
Info (176445): Device EPM570T100I5 is compatible
Info (176445): Device EPM570T100A5 is compatible
Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 80 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Info (332104): Reading SDC File: 'GR8RAM.sdc'
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 2 clocks
@ -741,32 +727,29 @@ Info (332111): Found 2 clocks
Info (332111): 40.000 C25M
Info (332111): 978.000 PHI0
Info (186079): Completed User Assigned Global Signals Promotion Operation
Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9
Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9
Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
Info (186217): Destination "comb~0" may be non-global or may not use global clock
Info (186217): Destination "PHI0r1" may be non-global or may not use global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 10
Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9
Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 16
Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 94
Info (186217): Destination "PHI0r[0]" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 13
Info (186217): Destination "comb~1" may be non-global or may not use global clock
Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 16
Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 91
Info (186217): Destination "AddrIncH" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 117
Info (186217): Destination "AddrIncM" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 116
Info (186217): Destination "AddrIncL" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 115
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 1 input, 0 output, 0 bidirectional)
Info (176212): I/O standards used: 3.3-V LVTTL.
Info (176215): I/O bank details before I/O pin placement
Info (176214): Statistics of I/O banks
Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available
Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 30% of the available device resources
Info (170196): Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
@ -774,20 +757,20 @@ Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170200): Optimizations that may affect the design's timing were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds.
Info (11888): Total time spent on timing analysis during the Fitter is 0.21 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 13746 megabytes
Info: Processing ended: Tue Feb 28 11:21:23 2023
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05
Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 13737 megabytes
Info: Processing ended: Sat Apr 15 08:20:44 2023
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:03
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg.
The suppressed messages can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg.

6
cpld/output_files/GR8RAM.fit.summary
View File

@ -1,11 +1,11 @@
Fitter Status : Successful - Tue Feb 28 11:21:23 2023
Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Fitter Status : Successful - Sat Apr 15 08:20:44 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Total logic elements : 233 / 240 ( 97 % )
Total logic elements : 232 / 240 ( 97 % )
Total pins : 80 / 80 ( 100 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )

58
cpld/output_files/GR8RAM.flow.rpt
View File

@ -1,6 +1,6 @@
Flow report for GR8RAM
Tue Feb 28 11:21:31 2023
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Sat Apr 15 08:20:49 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -21,7 +21,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
----------------
; Legal Notice ;
----------------
Copyright (C) 2022 Intel Corporation. All rights reserved.
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
+------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+------------------------------------------------+
; Flow Status ; Successful - Tue Feb 28 11:21:31 2023 ;
; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 233 / 240 ( 97 % ) ;
; Total pins ; 80 / 80 ( 100 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+------------------------------------------------+
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
; Flow Status ; Successful - Sat Apr 15 08:20:46 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 232 / 240 ( 97 % ) ;
; Total pins ; 80 / 80 ( 100 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+---------------------------------------------+
+-----------------------------------------+
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 02/28/2023 11:20:54 ;
; Start date & time ; 04/15/2023 08:20:18 ;
; Main task ; Compilation ;
; Revision Name ; GR8RAM ;
+-------------------+---------------------+
@ -71,20 +71,17 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 121381084694.167760125411500 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 121381084694.168156121801616 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
; EDA_NETLIST_WRITER_OUTPUT_DIR ; simulation/questa ; -- ; -- ; eda_simulation ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; Questa Intel FPGA (Verilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ;
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 2 ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
@ -94,12 +91,11 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:23 ; 1.0 ; 13114 MB ; 00:00:48 ;
; Fitter ; 00:00:06 ; 1.0 ; 13746 MB ; 00:00:05 ;
; Assembler ; 00:00:01 ; 1.0 ; 13099 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13081 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 13024 MB ; 00:00:01 ;
; Total ; 00:00:33 ; -- ; -- ; 00:00:56 ;
; Analysis & Synthesis ; 00:00:22 ; 1.0 ; 13095 MB ; 00:00:42 ;
; Fitter ; 00:00:04 ; 1.0 ; 13737 MB ; 00:00:03 ;
; Assembler ; 00:00:01 ; 1.0 ; 13055 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13055 MB ; 00:00:01 ;
; Total ; 00:00:29 ; -- ; -- ; 00:00:47 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
@ -112,7 +108,6 @@ https://fpgasoftware.intel.com/eula.
; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
+----------------------+------------------+------------+------------+----------------+
@ -123,7 +118,6 @@ quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
quartus_sta GR8RAM -c GR8RAM
quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM

2
cpld/output_files/GR8RAM.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="e669c88e609b9ce1c5b6"/>
<hash md5_digest_80b="d50e59ac0621234423dc"/>
</project>
<file_info>
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>

175
cpld/output_files/GR8RAM.map.rpt
View File

@ -1,6 +1,6 @@
Analysis & Synthesis report for GR8RAM
Tue Feb 28 11:21:16 2023
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Sat Apr 15 08:20:39 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -26,7 +26,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
----------------
; Legal Notice ;
----------------
Copyright (C) 2022 Intel Corporation. All rights reserved.
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Feb 28 11:21:16 2023 ;
; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Total logic elements ; 253 ;
; Total pins ; 80 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------------+------------------------------------------------+
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Apr 15 08:20:39 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Total logic elements ; 241 ;
; Total pins ; 80 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
@ -145,13 +145,13 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+
; gr8ram.v ; yes ; Auto-Found Verilog HDL File ; //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v ; ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+
+-----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+-------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------+-------------------------------+---------+
; GR8RAM.v ; yes ; User Verilog HDL File ; Y:/Repos/GR8RAM/cpld/GR8RAM.v ; ;
+----------------------------------+-----------------+------------------------+-------------------------------+---------+
+-----------------------------------------------------+
@ -159,33 +159,33 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 253 ;
; -- Combinational with no register ; 129 ;
; -- Register only ; 26 ;
; -- Combinational with a register ; 98 ;
; Total logic elements ; 241 ;
; -- Combinational with no register ; 133 ;
; -- Register only ; 13 ;
; -- Combinational with a register ; 95 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 124 ;
; -- 3 input functions ; 30 ;
; -- 2 input functions ; 71 ;
; -- 1 input functions ; 0 ;
; -- 4 input functions ; 123 ;
; -- 3 input functions ; 35 ;
; -- 2 input functions ; 67 ;
; -- 1 input functions ; 1 ;
; -- 0 input functions ; 2 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 220 ;
; -- normal mode ; 208 ;
; -- arithmetic mode ; 33 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 45 ;
; -- asynchronous clear/load mode ; 29 ;
; ; ;
; Total registers ; 124 ;
; Total registers ; 108 ;
; Total logic cells in carry chains ; 37 ;
; I/O pins ; 80 ;
; Maximum fan-out node ; C25M ;
; Maximum fan-out ; 110 ;
; Total fan-out ; 1076 ;
; Average fan-out ; 3.23 ;
; Maximum fan-out ; 100 ;
; Total fan-out ; 1057 ;
; Average fan-out ; 3.29 ;
+---------------------------------------------+-------+
@ -194,7 +194,7 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; |GR8RAM ; 253 (253) ; 124 ; 0 ; 80 ; 0 ; 129 (129) ; 26 (26) ; 98 (98) ; 37 (37) ; 0 (0) ; |GR8RAM ; GR8RAM ; work ;
; |GR8RAM ; 241 (241) ; 108 ; 0 ; 80 ; 0 ; 133 (133) ; 13 (13) ; 95 (95) ; 37 (37) ; 0 (0) ; |GR8RAM ; GR8RAM ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@ -214,16 +214,17 @@ Encoding Type: One-Hot
+--------+--------+--------+--------+--------+--------+--------+
+------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+--------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+--------------------+
; IS~8 ; Lost fanout ;
; IS~9 ; Lost fanout ;
; IS~10 ; Lost fanout ;
; Total Number of Removed Registers = 3 ; ;
+---------------------------------------+--------------------+
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; SA[12]~reg0 ; Stuck at GND due to stuck port data_in ;
; IS~8 ; Lost fanout ;
; IS~9 ; Lost fanout ;
; IS~10 ; Lost fanout ;
; Total Number of Removed Registers = 4 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------+
@ -231,12 +232,12 @@ Encoding Type: One-Hot
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 124 ;
; Total registers ; 108 ;
; Number of registers using Synchronous Clear ; 12 ;
; Number of registers using Synchronous Load ; 33 ;
; Number of registers using Asynchronous Clear ; 29 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 29 ;
; Number of registers using Asynchronous Clear ; 28 ;
; Number of registers using Asynchronous Load ; 1 ;
; Number of registers using Clock Enable ; 38 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
@ -252,8 +253,9 @@ Encoding Type: One-Hot
; nSWE~reg0 ; 1 ;
; DQML~reg0 ; 1 ;
; DQMH~reg0 ; 1 ;
; RCKE~reg0 ; 1 ;
; Total number of inverted registers = 7 ; ;
; RCKE~reg0 ; 4 ;
; nFCS~reg0 ; 1 ;
; Total number of inverted registers = 8 ; ;
+----------------------------------------+---------+
@ -262,14 +264,13 @@ Encoding Type: One-Hot
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ;
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ;
; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[3]~reg0 ;
; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[1]~reg0 ;
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[0] ;
; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[7]~reg0 ;
; 20:1 ; 2 bits ; 26 LEs ; 12 LEs ; 14 LEs ; Yes ; |GR8RAM|SA[1]~reg0 ;
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[7] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ;
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[4] ;
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |GR8RAM|RDD[2] ;
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQML~reg0 ;
; 18:1 ; 3 bits ; 36 LEs ; 6 LEs ; 30 LEs ; Yes ; |GR8RAM|RDD[4] ;
; 7:1 ; 5 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |GR8RAM|IS ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
@ -279,44 +280,44 @@ Encoding Type: One-Hot
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Info: Processing started: Tue Feb 28 11:20:53 2023
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Sat Apr 15 08:20:17 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: GR8RAM File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
Info (12023): Found entity 1: GR8RAM File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 1
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at gr8ram.v(42): truncated value with size 32 to match size of target (4) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 42
Warning (10230): Verilog HDL assignment warning at gr8ram.v(47): truncated value with size 32 to match size of target (14) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 47
Warning (10230): Verilog HDL assignment warning at gr8ram.v(134): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 134
Warning (10230): Verilog HDL assignment warning at gr8ram.v(142): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 142
Warning (10230): Verilog HDL assignment warning at gr8ram.v(149): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 149
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (4) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 33
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(38): truncated value with size 32 to match size of target (14) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 38
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(129): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 129
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(137): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 137
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(144): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 144
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "nNMIout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 563
Warning (13410): Pin "nIRQout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 566
Warning (13410): Pin "nRDYout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 565
Warning (13410): Pin "nINHout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 564
Warning (13410): Pin "RWout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 567
Warning (13410): Pin "nDMAout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 562
Warning (13410): Pin "RAdir" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 561
Warning (13410): Pin "GNDout1" is stuck at GND File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 538
Warning (13410): Pin "GNDout2" is stuck at GND File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 539
Warning (13410): Pin "nIRQout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 534
Warning (13410): Pin "RWout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 535
Warning (13410): Pin "nDMAout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 533
Warning (13410): Pin "RAdir" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 532
Warning (13410): Pin "SA[12]" is stuck at GND File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 414
Info (17049): 3 registers lost all their fanouts during netlist optimizations.
Info (21057): Implemented 333 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 28 input pins
Info (21059): Implemented 35 output pins
Info (21057): Implemented 321 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 29 input pins
Info (21059): Implemented 34 output pins
Info (21060): Implemented 17 bidirectional pins
Info (21061): Implemented 253 logic cells
Info (144001): Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
Info: Peak virtual memory: 13114 megabytes
Info: Processing ended: Tue Feb 28 11:21:16 2023
Info: Elapsed time: 00:00:23
Info: Total CPU time (on all processors): 00:00:48
Info (21061): Implemented 241 logic cells
Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings
Info: Peak virtual memory: 13095 megabytes
Info: Processing ended: Sat Apr 15 08:20:39 2023
Info: Elapsed time: 00:00:22
Info: Total CPU time (on all processors): 00:00:42
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg.
The suppressed messages can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.

4
cpld/output_files/GR8RAM.map.smsg
View File

@ -1,2 +1,2 @@
Warning (10273): Verilog HDL warning at gr8ram.v(110): extended using "x" or "z" File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 110
Warning (10273): Verilog HDL warning at gr8ram.v(286): extended using "x" or "z" File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 286
Warning (10273): Verilog HDL warning at GR8RAM.v(110): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 110
Warning (10273): Verilog HDL warning at GR8RAM.v(250): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 250

6
cpld/output_files/GR8RAM.map.summary
View File

@ -1,9 +1,9 @@
Analysis & Synthesis Status : Successful - Tue Feb 28 11:21:16 2023
Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Analysis & Synthesis Status : Successful - Sat Apr 15 08:20:39 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM
Family : MAX II
Total logic elements : 253
Total logic elements : 241
Total pins : 80
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )

12
cpld/output_files/GR8RAM.pin
View File

@ -1,4 +1,4 @@
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Copyright (C) 2019 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
@ -58,12 +58,12 @@
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
RA[4] : 1 : input : 3.3-V LVTTL : : 2 : N
RA[4] : 1 : input : 3.3-V LVTTL : : 2 : Y
RA[5] : 2 : input : 3.3-V LVTTL : : 1 : Y
RA[6] : 3 : input : 3.3-V LVTTL : : 1 : Y
RA[3] : 4 : input : 3.3-V LVTTL : : 1 : Y
@ -88,9 +88,9 @@ TMS : 22 : input : :
TDI : 23 : input : : : 1 :
TCK : 24 : input : : : 1 :
TDO : 25 : output : : : 1 :
nNMIout : 26 : output : 3.3-V LVTTL : : 1 : Y
nINHout : 27 : output : 3.3-V LVTTL : : 1 : Y
nRDYout : 28 : output : 3.3-V LVTTL : : 1 : Y
GNDout1 : 26 : output : 3.3-V LVTTL : : 1 : Y
PU : 27 : input : 3.3-V LVTTL : : 1 : Y
GNDout2 : 28 : output : 3.3-V LVTTL : : 1 : Y
nIRQout : 29 : output : 3.3-V LVTTL : : 1 : Y
nRESout : 30 : output : 3.3-V LVTTL : : 1 : Y
VCCIO1 : 31 : power : : 3.3V : 1 :

BIN
cpld/output_files/GR8RAM.pof
View File

Binary file not shown.

720
cpld/output_files/GR8RAM.sta.rpt
View File

@ -1,6 +1,6 @@
Timing Analyzer report for GR8RAM
Tue Feb 28 11:21:29 2023
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Sat Apr 15 08:20:49 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -18,29 +18,33 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
10. Removal Summary
11. Minimum Pulse Width Summary
12. Setup: 'C25M'
13. Hold: 'C25M'
14. Recovery: 'C25M'
15. Removal: 'C25M'
16. Setup Transfers
17. Hold Transfers
18. Recovery Transfers
19. Removal Transfers
20. Report TCCS
21. Report RSKM
22. Unconstrained Paths Summary
23. Clock Status Summary
24. Unconstrained Input Ports
25. Unconstrained Output Ports
26. Unconstrained Input Ports
27. Unconstrained Output Ports
28. Timing Analyzer Messages
13. Setup: 'PHI0'
14. Hold: 'C25M'
15. Hold: 'PHI0'
16. Recovery: 'C25M'
17. Recovery: 'PHI0'
18. Removal: 'PHI0'
19. Removal: 'C25M'
20. Setup Transfers
21. Hold Transfers
22. Recovery Transfers
23. Removal Transfers
24. Report TCCS
25. Report RSKM
26. Unconstrained Paths Summary
27. Clock Status Summary
28. Unconstrained Input Ports
29. Unconstrained Output Ports
30. Unconstrained Input Ports
31. Unconstrained Output Ports
32. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2022 Intel Corporation. All rights reserved.
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
@ -57,18 +61,18 @@ https://fpgasoftware.intel.com/eula.
+--------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+--------------------------------------------------------+
; Quartus Prime Version ; Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; GR8RAM ;
; Device Family ; MAX II ;
; Device Name ; EPM240T100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+--------------------------------------------------------+
+-----------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; GR8RAM ;
; Device Family ; MAX II ;
; Device Name ; EPM240T100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
@ -80,10 +84,11 @@ https://fpgasoftware.intel.com/eula.
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.0% ;
+----------------------------+-------------+
@ -92,7 +97,7 @@ https://fpgasoftware.intel.com/eula.
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+---------------+--------+--------------------------+
; GR8RAM.sdc ; OK ; Tue Feb 28 11:21:29 2023 ;
; GR8RAM.sdc ; OK ; Sat Apr 15 08:20:49 2023 ;
+---------------+--------+--------------------------+
@ -111,18 +116,20 @@ https://fpgasoftware.intel.com/eula.
+-----------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------+------+
; 51.43 MHz ; 51.43 MHz ; C25M ; ;
; 61.84 MHz ; 61.84 MHz ; C25M ; ;
; 86.1 MHz ; 86.1 MHz ; PHI0 ; ;
+-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------+
; Setup Summary ;
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; C25M ; 10.278 ; 0.000 ;
+-------+--------+---------------+
+---------------------------------+
; Setup Summary ;
+-------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+---------+---------------+
; C25M ; 11.915 ; 0.000 ;
; PHI0 ; 483.193 ; 0.000 ;
+-------+---------+---------------+
+-------------------------------+
@ -130,17 +137,19 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; C25M ; 1.376 ; 0.000 ;
; C25M ; 1.411 ; 0.000 ;
; PHI0 ; 2.670 ; 0.000 ;
+-------+-------+---------------+
+--------------------------------+
; Recovery Summary ;
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; C25M ; 33.311 ; 0.000 ;
+-------+--------+---------------+
+---------------------------------+
; Recovery Summary ;
+-------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+---------+---------------+
; C25M ; 33.174 ; 0.000 ;
; PHI0 ; 973.979 ; 0.000 ;
+-------+---------+---------------+
+-------------------------------+
@ -148,7 +157,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; C25M ; 6.135 ; 0.000 ;
; PHI0 ; 3.467 ; 0.000 ;
; C25M ; 6.272 ; 0.000 ;
+-------+-------+---------------+
@ -167,288 +177,324 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+--------+-----------+------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+------------+--------------+-------------+--------------+------------+------------+
; 10.278 ; REGEN ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.389 ;
; 10.285 ; REGEN ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.382 ;
; 10.289 ; REGEN ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.378 ;
; 10.642 ; REGEN ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.025 ;
; 11.085 ; REGEN ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.582 ;
; 11.357 ; REGEN ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.310 ;
; 11.401 ; REGEN ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.266 ;
; 11.402 ; REGEN ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.265 ;
; 12.395 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ;
; 12.395 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ;
; 12.395 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ;
; 12.395 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ;
; 12.440 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ;
; 12.440 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ;
; 12.440 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ;
; 12.440 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ;
; 12.450 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ;
; 12.450 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ;
; 12.450 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ;
; 12.450 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ;
; 12.495 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ;
; 12.495 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ;
; 12.495 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ;
; 12.495 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ;
; 12.804 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ;
; 12.804 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ;
; 12.804 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ;
; 12.804 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ;
; 12.849 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ;
; 12.849 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ;
; 12.849 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ;
; 12.849 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ;
; 13.331 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.336 ;
; 13.753 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ;
; 13.753 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ;
; 13.753 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ;
; 13.753 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ;
; 13.798 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ;
; 13.798 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ;
; 13.798 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ;
; 13.798 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ;
; 13.971 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.696 ;
; 14.103 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.564 ;
; 14.314 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.353 ;
; 14.675 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.992 ;
; 14.748 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.919 ;
; 14.753 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.914 ;
; 14.779 ; SetFWr[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.888 ;
; 14.780 ; SetFWr[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.887 ;
; 14.785 ; SetFWr[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.882 ;
; 14.975 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.692 ;
; 15.251 ; SetFWr[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.416 ;
; 15.322 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.345 ;
; 15.387 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.280 ;
; 15.489 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.178 ;
; 15.612 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.055 ;
; 15.651 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.016 ;
; 15.653 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.014 ;
; 15.700 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.967 ;
; 15.911 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.756 ;
; 16.065 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.602 ;
; 16.103 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.564 ;
; 16.349 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.318 ;
; 16.647 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.020 ;
; 16.656 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.011 ;
; 16.711 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.956 ;
; 16.777 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.890 ;
; 17.105 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.562 ;
; 22.720 ; Addr[23] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 16.947 ;
; 23.632 ; Addr[23] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 16.035 ;
; 23.717 ; REGEN ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 15.950 ;
; 23.986 ; SetFWr[0] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 15.681 ;
; 24.629 ; REGEN ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 15.038 ;
; 24.898 ; SetFWr[0] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.769 ;
; 25.067 ; SetFWr[1] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.600 ;
; 25.201 ; PS[1] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.466 ;
; 25.277 ; Addr[23] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.390 ;
; 25.323 ; PS[1] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.344 ;
; 25.783 ; Addr[23] ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.884 ;
; 25.876 ; Addr[23] ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.791 ;
; 25.979 ; SetFWr[1] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.688 ;
; 26.015 ; Addr[23] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.652 ;
; 26.018 ; Addr[23] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.649 ;
; 26.117 ; Addr[23] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.550 ;
; 26.222 ; PS[1] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.274 ; REGEN ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.393 ;
; 26.312 ; Addr[23] ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.355 ;
; 26.361 ; LS[7] ; IS.000 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.306 ;
; 26.498 ; PS[0] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.169 ;
; 26.543 ; SetFWr[0] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.124 ;
; 26.596 ; Addr[23] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.071 ;
; 26.722 ; PS[0] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.945 ;
; 26.722 ; PS[0] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.945 ;
; 11.915 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.752 ;
; 11.915 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.752 ;
; 11.915 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.752 ;
; 11.933 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.734 ;
; 11.933 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.734 ;
; 11.933 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.734 ;
; 11.933 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.734 ;
; 12.040 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.627 ;
; 12.070 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.597 ;
; 12.070 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.597 ;
; 12.070 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.597 ;
; 12.088 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.579 ;
; 12.088 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.579 ;
; 12.088 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.579 ;
; 12.088 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.579 ;
; 12.195 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.472 ;
; 12.462 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.205 ;
; 12.462 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.205 ;
; 12.462 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.205 ;
; 12.480 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.187 ;
; 12.480 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.187 ;
; 12.480 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.187 ;
; 12.480 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.187 ;
; 12.587 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.080 ;
; 13.056 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.611 ;
; 14.139 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.528 ;
; 14.169 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.498 ;
; 14.169 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.498 ;
; 14.169 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.498 ;
; 14.187 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.480 ;
; 14.187 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.480 ;
; 14.187 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.480 ;
; 14.187 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.480 ;
; 14.286 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.381 ;
; 14.294 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.373 ;
; 14.402 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.265 ;
; 14.556 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.111 ;
; 14.609 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.058 ;
; 14.635 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.032 ;
; 14.925 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.742 ;
; 14.995 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.672 ;
; 15.002 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.665 ;
; 15.027 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.640 ;
; 15.277 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.390 ;
; 15.435 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.232 ;
; 15.556 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.111 ;
; 15.624 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.043 ;
; 15.747 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.920 ;
; 15.802 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.865 ;
; 15.997 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.670 ;
; 16.241 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.426 ;
; 16.291 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.376 ;
; 16.378 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.289 ;
; 16.490 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.177 ;
; 16.667 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.000 ;
; 16.782 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.885 ;
; 25.324 ; IS.110 ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.343 ;
; 26.153 ; PS[3] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.514 ;
; 26.508 ; REGEN ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.159 ;
; 26.508 ; REGEN ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.159 ;
; 26.508 ; REGEN ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.159 ;
; 26.508 ; REGEN ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.159 ;
; 26.508 ; REGEN ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.159 ;
; 26.508 ; REGEN ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.159 ;
; 26.508 ; REGEN ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.159 ;
; 26.508 ; REGEN ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.159 ;
; 27.072 ; REGEN ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.595 ;
; 27.072 ; REGEN ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.595 ;
; 27.072 ; REGEN ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.595 ;
; 27.072 ; REGEN ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.595 ;
; 27.072 ; REGEN ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.595 ;
; 27.072 ; REGEN ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.595 ;
; 27.072 ; REGEN ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.595 ;
; 27.072 ; REGEN ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.595 ;
; 27.098 ; REGEN ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.569 ;
; 27.098 ; REGEN ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.569 ;
; 27.098 ; REGEN ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.569 ;
; 27.098 ; REGEN ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.569 ;
; 27.098 ; REGEN ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.569 ;
; 27.098 ; REGEN ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.569 ;
; 27.098 ; REGEN ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.569 ;
; 27.098 ; REGEN ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.569 ;
; 27.333 ; REGEN ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 12.334 ;
; 27.582 ; LS[7] ; IS.000 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.085 ;
; 27.662 ; PS[0] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.005 ;
; 27.786 ; REGEN ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 11.881 ;
; 28.059 ; PS[1] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.608 ;
; 28.168 ; LS[7] ; IS.110 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.499 ;
; 28.168 ; LS[7] ; IS.101 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.499 ;
; 28.168 ; LS[7] ; IS.001 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.499 ;
; 28.168 ; LS[7] ; IS.100 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.499 ;
; 28.189 ; IS.110 ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.478 ;
; 28.243 ; IS.110 ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.424 ;
; 28.295 ; IS.110 ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.372 ;
; 28.427 ; PS[3] ; IS.000 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.240 ;
; 28.433 ; LS[3] ; IS.000 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.234 ;
; 28.477 ; PS[0] ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.190 ;
; 28.477 ; PS[0] ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.190 ;
; 28.477 ; PS[0] ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.190 ;
; 28.477 ; PS[0] ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.190 ;
+--------+-----------+------------+--------------+-------------+--------------+------------+------------+
+--------------------------------------------------------------------------------------------------------------+
; Setup: 'PHI0' ;
+---------+-------------+----------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-------------+----------------+--------------+-------------+--------------+------------+------------+
; 483.193 ; Slot[0] ; RAMROMSpecSELr ; PHI0 ; PHI0 ; 489.000 ; 0.000 ; 5.474 ;
; 483.614 ; SlotKnown ; RAMROMSpecSELr ; PHI0 ; PHI0 ; 489.000 ; 0.000 ; 5.053 ;
; 483.707 ; Slot[1] ; RAMROMSpecSELr ; PHI0 ; PHI0 ; 489.000 ; 0.000 ; 4.960 ;
; 485.171 ; Slot[2] ; RAMROMSpecSELr ; PHI0 ; PHI0 ; 489.000 ; 0.000 ; 3.496 ;
; 974.776 ; RestoreDone ; RestoreDone ; PHI0 ; PHI0 ; 978.000 ; 0.000 ; 2.891 ;
+---------+-------------+----------------+--------------+-------------+--------------+------------+------------+
+-----------------------------------------------------------------------------------------------------------+
; Hold: 'C25M' ;
+-------+--------------+--------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------+--------------+--------------+-------------+--------------+------------+------------+
; 1.376 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.597 ;
; 1.412 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ;
; 1.412 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ;
; 1.419 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.640 ;
; 1.420 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ;
; 1.426 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.647 ;
; 1.429 ; nRESf[0] ; nRESf[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.650 ;
; 1.646 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.867 ;
; 1.649 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.870 ;
; 1.652 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.873 ;
; 1.653 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.874 ;
; 1.661 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 1.882 ;
; 1.664 ; Addr[19] ; SA[9]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.885 ;
; 1.670 ; IS.000 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 1.891 ;
; 1.675 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.896 ;
; 1.719 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.940 ;
; 1.720 ; PS[2] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 1.941 ;
; 1.793 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.014 ;
; 1.794 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.015 ;
; 1.806 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.027 ;
; 1.809 ; IS.101 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.030 ;
; 1.846 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.067 ;
; 1.942 ; Addr[21] ; SA[11]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.163 ;
; 1.948 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.169 ;
; 2.048 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.269 ;
; 2.063 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.284 ;
; 2.082 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 2.303 ;
; 1.411 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.632 ;
; 1.411 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.632 ;
; 1.421 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.642 ;
; 1.422 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.643 ;
; 1.433 ; PHI0r[1] ; PHI0r[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.654 ;
; 1.644 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.865 ;
; 1.656 ; PHI0r[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.877 ;
; 1.673 ; Addr[19] ; SA[9]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.894 ;
; 1.693 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.914 ;
; 1.789 ; PHI0r[0] ; PHI0r[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.010 ;
; 1.809 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.030 ;
; 1.926 ; IS.110 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.147 ;
; 1.939 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.160 ;
; 1.944 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.165 ;
; 1.946 ; RCKE~reg0 ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.167 ;
; 1.950 ; RCKE~reg0 ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.171 ;
; 1.952 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.173 ;
; 2.013 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.234 ;
; 2.041 ; IS.100 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.262 ;
; 2.048 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.269 ;
; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ;
; 2.115 ; Addr[0] ; DQML~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.336 ;
; 2.116 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.337 ;
; 2.116 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.337 ;
; 2.117 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.108 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.329 ;
; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.125 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ;
; 2.126 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ;
; 2.126 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
; 2.127 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ;
; 2.128 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.349 ;
; 2.137 ; IS.111 ; IS.111 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ;
; 2.144 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
; 2.145 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ;
; 2.149 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.370 ;
; 2.150 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.371 ;
; 2.151 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ;
; 2.153 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.374 ;
; 2.185 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.406 ;
; 2.188 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.409 ;
; 2.128 ; IS.101 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.349 ;
; 2.133 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ;
; 2.143 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.364 ;
; 2.144 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
; 2.145 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ;
; 2.154 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.375 ;
; 2.154 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.375 ;
; 2.160 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.381 ;
; 2.166 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.387 ;
; 2.211 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.432 ;
; 2.212 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ;
; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ;
; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
; 2.232 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
; 2.232 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
; 2.232 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
; 2.239 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ;
; 2.240 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ;
; 2.241 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
; 2.242 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.463 ;
; 2.249 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
; 2.249 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
; 2.250 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ;
; 2.250 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ;
; 2.251 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ;
; 2.252 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ;
; 2.259 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.480 ;
; 2.261 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
; 2.261 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
; 2.263 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.484 ;
; 2.264 ; nRESf[0] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.485 ;
; 2.264 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.485 ;
; 2.267 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.488 ;
; 2.270 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.491 ;
; 2.271 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.492 ;
; 2.272 ; SetFWLoaded ; SetFWr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.493 ;
; 2.272 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.493 ;
; 2.272 ; SetFWLoaded ; SetFWr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.493 ;
; 2.274 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.495 ;
; 2.276 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.497 ;
; 2.287 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.508 ;
; 2.573 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.794 ;
; 2.686 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.907 ;
; 2.690 ; Addr[0] ; DQMH~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.911 ;
; 2.902 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.123 ;
; 2.906 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.127 ;
; 2.237 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.458 ;
; 2.241 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
; 2.241 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
; 2.245 ; PS[3] ; FCKout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.466 ;
; 2.248 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ;
; 2.249 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
; 2.249 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
; 2.249 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
; 2.251 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ;
; 2.258 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.479 ;
; 2.260 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ;
; 2.261 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
; 2.261 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
; 2.262 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ;
; 2.263 ; PHI0r[1] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.484 ;
; 2.268 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.489 ;
; 2.273 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.494 ;
; 2.284 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.505 ;
; 2.285 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.506 ;
; 2.312 ; IS.111 ; IS.111 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.533 ;
; 2.313 ; IS.111 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.534 ;
; 2.319 ; IS.111 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.540 ;
; 2.442 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.663 ;
; 2.482 ; LS[0] ; IS.110 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.703 ;
; 2.485 ; LS[0] ; IS.100 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.706 ;
; 2.492 ; LS[0] ; IS.101 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.713 ;
; 2.493 ; LS[0] ; IS.001 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.714 ;
; 2.561 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.782 ;
; 2.590 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.811 ;
; 2.604 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.825 ;
; 2.660 ; LS[2] ; IS.101 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.881 ;
; 2.672 ; LS[2] ; IS.110 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.893 ;
; 2.754 ; LS[13] ; IS.101 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.975 ;
; 2.768 ; LS[13] ; IS.110 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.989 ;
; 2.784 ; Addr[2] ; SA[1]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.005 ;
; 2.824 ; PS[2] ; SA[2]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.045 ;
; 2.826 ; Addr[21] ; SA[11]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.047 ;
; 2.884 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.105 ;
; 2.886 ; PS[1] ; SA[10]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.107 ;
; 2.939 ; PS[1] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ;
; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ;
; 2.948 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.169 ;
; 2.948 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.169 ;
; 2.940 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.161 ;
; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.957 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ;
; 2.958 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
; 2.959 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ;
; 2.976 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ;
; 2.983 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.204 ;
; 2.985 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.206 ;
; 3.001 ; PHI0r1 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.222 ;
; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ;
; 3.059 ; Addr[16] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.280 ;
; 2.956 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ;
; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ;
; 2.965 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.186 ;
; 2.975 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.196 ;
; 2.976 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ;
+-------+--------------+--------------+--------------+-------------+--------------+------------+------------+
+--------------------------------------------------------------------------------------------------------------+
; Hold: 'PHI0' ;
+---------+-------------+----------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-------------+----------------+--------------+-------------+--------------+------------+------------+
; 2.670 ; RestoreDone ; RestoreDone ; PHI0 ; PHI0 ; 0.000 ; 0.000 ; 2.891 ;
; 492.275 ; Slot[2] ; RAMROMSpecSELr ; PHI0 ; PHI0 ; -489.000 ; 0.000 ; 3.496 ;
; 493.739 ; Slot[1] ; RAMROMSpecSELr ; PHI0 ; PHI0 ; -489.000 ; 0.000 ; 4.960 ;
; 493.832 ; SlotKnown ; RAMROMSpecSELr ; PHI0 ; PHI0 ; -489.000 ; 0.000 ; 5.053 ;
; 494.253 ; Slot[0] ; RAMROMSpecSELr ; PHI0 ; PHI0 ; -489.000 ; 0.000 ; 5.474 ;
+---------+-------------+----------------+--------------+-------------+--------------+------------+------------+
+-----------------------------------------------------------------------------------------------------+
; Recovery: 'C25M' ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
; 33.311 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; REGEN ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.174 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; REGEN ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
; 33.174 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.493 ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
+-------------------------------------------------------------------------------------------------------+
; Recovery: 'PHI0' ;
+---------+-------------+---------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-------------+---------+--------------+-------------+--------------+------------+------------+
; 973.979 ; RestoreDone ; FCS ; PHI0 ; PHI0 ; 978.000 ; 0.000 ; 3.688 ;
+---------+-------------+---------+--------------+-------------+--------------+------------+------------+
+-----------------------------------------------------------------------------------------------------+
; Removal: 'PHI0' ;
+-------+-------------+---------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------+---------+--------------+-------------+--------------+------------+------------+
; 3.467 ; RestoreDone ; FCS ; PHI0 ; PHI0 ; 0.000 ; 0.000 ; 3.688 ;
+-------+-------------+---------+--------------+-------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------+
; Removal: 'C25M' ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
; 6.135 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.272 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
; 6.272 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.493 ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
@ -457,8 +503,10 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------+----------+------------+------------+------------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+------------+------------+------------+----------+
; C25M ; C25M ; 1520 ; 0 ; 88 ; 0 ;
; PHI0 ; C25M ; false path ; false path ; false path ; 0 ;
; C25M ; C25M ; 1309 ; 0 ; 56 ; 0 ;
; PHI0 ; C25M ; false path ; false path ; 0 ; 0 ;
; C25M ; PHI0 ; false path ; 0 ; false path ; 0 ;
; PHI0 ; PHI0 ; 0 ; 4 ; 0 ; 1 ;
+------------+----------+------------+------------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -468,29 +516,35 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------+----------+------------+------------+------------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+------------+------------+------------+----------+
; C25M ; C25M ; 1520 ; 0 ; 88 ; 0 ;
; PHI0 ; C25M ; false path ; false path ; false path ; 0 ;
; C25M ; C25M ; 1309 ; 0 ; 56 ; 0 ;
; PHI0 ; C25M ; false path ; false path ; 0 ; 0 ;
; C25M ; PHI0 ; false path ; 0 ; false path ; 0 ;
; PHI0 ; PHI0 ; 0 ; 4 ; 0 ; 1 ;
+------------+----------+------------+------------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------+
; Recovery Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C25M ; C25M ; 29 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
+---------------------------------------------------------------------+
; Recovery Transfers ;
+------------+----------+----------+----------+------------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+------------+----------+
; C25M ; C25M ; 25 ; 0 ; 0 ; 0 ;
; C25M ; PHI0 ; 0 ; 0 ; false path ; 0 ;
; PHI0 ; PHI0 ; 0 ; 0 ; 0 ; 1 ;
+------------+----------+----------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------+
; Removal Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C25M ; C25M ; 29 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
+---------------------------------------------------------------------+
; Removal Transfers ;
+------------+----------+----------+----------+------------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+------------+----------+
; C25M ; C25M ; 25 ; 0 ; 0 ; 0 ;
; C25M ; PHI0 ; 0 ; 0 ; false path ; 0 ;
; PHI0 ; PHI0 ; 0 ; 0 ; 0 ; 1 ;
+------------+----------+----------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -513,10 +567,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 44 ; 44 ;
; Unconstrained Input Port Paths ; 246 ; 246 ;
; Unconstrained Output Ports ; 45 ; 45 ;
; Unconstrained Output Port Paths ; 217 ; 217 ;
; Unconstrained Input Ports ; 45 ; 45 ;
; Unconstrained Input Port Paths ; 429 ; 429 ;
; Unconstrained Output Ports ; 44 ; 44 ;
; Unconstrained Output Port Paths ; 133 ; 133 ;
+---------------------------------+-------+------+
@ -540,6 +594,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; MISO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MOSI ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PHI0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PU ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
@ -615,7 +670,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; SA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@ -645,6 +699,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; MISO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MOSI ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PHI0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PU ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
@ -720,7 +775,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; SA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@ -745,8 +799,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Info: Processing started: Tue Feb 28 11:21:27 2023
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Sat Apr 15 08:20:47 2023
Info: Command: quartus_sta GR8RAM -c GR8RAM
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@ -758,22 +812,26 @@ Info (334004): Delay annotation completed successfully
Info (332104): Reading SDC File: 'GR8RAM.sdc'
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Info (332146): Worst-case setup slack is 10.278
Info (332146): Worst-case setup slack is 11.915
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 10.278 0.000 C25M
Info (332146): Worst-case hold slack is 1.376
Info (332119): 11.915 0.000 C25M
Info (332119): 483.193 0.000 PHI0
Info (332146): Worst-case hold slack is 1.411
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 1.376 0.000 C25M
Info (332146): Worst-case recovery slack is 33.311
Info (332119): 1.411 0.000 C25M
Info (332119): 2.670 0.000 PHI0
Info (332146): Worst-case recovery slack is 33.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 33.311 0.000 C25M
Info (332146): Worst-case removal slack is 6.135
Info (332119): 33.174 0.000 C25M
Info (332119): 973.979 0.000 PHI0
Info (332146): Worst-case removal slack is 3.467
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 6.135 0.000 C25M
Info (332119): 3.467 0.000 PHI0
Info (332119): 6.272 0.000 C25M
Info (332146): Worst-case minimum pulse width slack is 19.734
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
@ -783,8 +841,8 @@ Info (332001): The selected device family is not supported by the report_metasta
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13081 megabytes
Info: Processing ended: Tue Feb 28 11:21:29 2023
Info: Peak virtual memory: 13055 megabytes
Info: Processing ended: Sat Apr 15 08:20:49 2023
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01

24
cpld/output_files/GR8RAM.sta.summary
View File

@ -3,19 +3,35 @@ Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'C25M'
Slack : 10.278
Slack : 11.915
TNS : 0.000
Type : Setup 'PHI0'
Slack : 483.193
TNS : 0.000
Type : Hold 'C25M'
Slack : 1.376
Slack : 1.411
TNS : 0.000
Type : Hold 'PHI0'
Slack : 2.670
TNS : 0.000
Type : Recovery 'C25M'
Slack : 33.311
Slack : 33.174
TNS : 0.000
Type : Recovery 'PHI0'
Slack : 973.979
TNS : 0.000
Type : Removal 'PHI0'
Slack : 3.467
TNS : 0.000
Type : Removal 'C25M'
Slack : 6.135
Slack : 6.272
TNS : 0.000
Type : Minimum Pulse Width 'C25M'