GR8RAM/cpld/LCMXO2-640HC/GR8RAM_LCMXO2_640HC.ldf

<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="GR8RAM_LCMXO2_640HC" device="LCMXO2-640HC-4TG100C" default_implementation="impl1">
    <Options/>
    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
        <Options def_top="GR8RAM"/>
        <Source name="../GR8RAM.v" type="Verilog" type_short="Verilog">
            <Options top_module="GR8RAM"/>
        </Source>
        <Source name="../SlinkyRegisters.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="../BusInterface.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="../InitController.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="../SDRAMController.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="../GR8RAM-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
            <Options/>
        </Source>
        <Source name="../GR8RAM.sdc" type="Synplify Design Constraints File" type_short="SDC">
            <Options/>
        </Source>
        <Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
            <Options/>
        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="GR8RAM_LCMXO2_640HC1.sty"/>
</BaliProject>