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https://github.com/garrettsworkshop/GR8RAM.git
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487 lines
20 KiB
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487 lines
20 KiB
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<HEAD><TITLE>Project Summary</TITLE>
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<PRE><A name="Mrp"></A>
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Lattice Mapping Report File for Design Module 'GR8RAM'
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<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
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Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
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GR8RAM_LCMXO2_640HC_impl1.ngd -o GR8RAM_LCMXO2_640HC_impl1_map.ncd -pr
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GR8RAM_LCMXO2_640HC_impl1.prf -mp GR8RAM_LCMXO2_640HC_impl1.mrp -lpf //Mac/
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iCloud/Repos/GR8RAM/cpld/LCMXO2-640HC/impl1/GR8RAM_LCMXO2_640HC_impl1_synpl
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ify.lpf -lpf //Mac/iCloud/Repos/GR8RAM/cpld/GR8RAM-LCMXO2.lpf -c 0 -gui
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-msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-640HC/promote.xml
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Target Vendor: LATTICE
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Target Device: LCMXO2-640HCTQFP100
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Target Performance: 4
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Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
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Mapped on: 07/14/24 06:18:48
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<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
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Number of registers: 183 out of 877 (21%)
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PFU registers: 153 out of 640 (24%)
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PIO registers: 30 out of 237 (13%)
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Number of SLICEs: 189 out of 320 (59%)
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SLICEs as Logic/ROM: 189 out of 320 (59%)
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SLICEs as RAM: 0 out of 240 (0%)
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SLICEs as Carry: 29 out of 320 (9%)
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Number of LUT4s: 368 out of 640 (58%)
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Number used as logic LUTs: 310
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Number used as distributed RAM: 0
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Number used as ripple logic: 58
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Number used as shift registers: 0
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Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%)
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Number of IDDR/ODDR/TDDR cells used: 2 out of 237 (1%)
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Number of IDDR cells: 0
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Number of ODDR cells: 2
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Number of TDDR cells: 0
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Number of PIO using at least one IDDR/ODDR/TDDR: 2 (0 differential)
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Number of PIO using IDDR only: 0 (0 differential)
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Number of PIO using ODDR only: 2 (0 differential)
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Number of PIO using TDDR only: 0 (0 differential)
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Number of PIO using IDDR/ODDR: 0 (0 differential)
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Number of PIO using IDDR/TDDR: 0 (0 differential)
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Number of PIO using ODDR/TDDR: 0 (0 differential)
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Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
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Number of block RAMs: 0 out of 2 (0%)
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Number of GSRs: 0 out of 1 (0%)
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EFB used : No
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JTAG used : No
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Readback used : No
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Oscillator used : Yes
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Startup used : No
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POR : On
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Bandgap : On
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Number of Power Controller: 0 out of 1 (0%)
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Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
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Number of DCCA: 0 out of 8 (0%)
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Number of DCMA: 0 out of 2 (0%)
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Notes:-
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1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
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distributed RAMs) + 2*(Number of ripple logic)
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2. Number of logic LUT4s does not include count of distributed RAM and
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ripple logic.
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Number of clocks: 2
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Net CLK: 127 loads, 117 rising, 10 falling (Driver: OSCH_inst )
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Net PHI0_c: 5 loads, 0 rising, 5 falling (Driver: PIO PHI0 )
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Number of Clock Enables: 12
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Net ram.un1_RS22_4_i: 1 loads, 0 LSLICEs
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Net ram.un1_RS22_7_i: 7 loads, 6 LSLICEs
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Net ram/RS_1_sqmuxa_2_i: 2 loads, 2 LSLICEs
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Net ram.RDDLE: 7 loads, 1 LSLICEs
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Net ram.un1_RS22_3_i: 2 loads, 0 LSLICEs
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Net ram.un1_RS23_1_i: 1 loads, 0 LSLICEs
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Net ic/CSTC: 8 loads, 8 LSLICEs
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Net ic/SetSize12: 3 loads, 3 LSLICEs
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Net ic/IS20: 2 loads, 2 LSLICEs
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Net bi/un1_ROMRD_1: 1 loads, 1 LSLICEs
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Net bi/un4_BankWRpre: 4 loads, 4 LSLICEs
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Net bi.BDoutLE: 8 loads, 0 LSLICEs
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Number of LSRs: 13
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Net ram.RA_0_sqmuxa: 13 loads, 6 LSLICEs
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Net ram.RS[2]: 1 loads, 1 LSLICEs
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Net ram/RS22: 1 loads, 1 LSLICEs
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Net ram.RCKEs_i: 1 loads, 0 LSLICEs
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Net ic/IS15: 1 loads, 1 LSLICEs
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Net ic.FOE12: 2 loads, 2 LSLICEs
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Net ic/SetRestoreEN: 5 loads, 3 LSLICEs
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Net ic/IS20: 4 loads, 4 LSLICEs
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Net N_32_i: 1 loads, 0 LSLICEs
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Net RegReset: 12 loads, 12 LSLICEs
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Net registers/Addr_0_sqmuxa: 8 loads, 8 LSLICEs
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Net bi/fb: 1 loads, 1 LSLICEs
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Net bi/S[1]: 8 loads, 8 LSLICEs
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Number of nets driven by tri-state buffers: 0
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Top 10 highest fanout non-clock nets:
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Net ic/IS[1]: 41 loads
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Net ic/IS[2]: 40 loads
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Net ic/IS[0]: 39 loads
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Net RegReset: 24 loads
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Net nDEVSEL_c: 17 loads
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Net bi/S[1]: 16 loads
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Net ram.RS[2]: 14 loads
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Net ram/CS[0]: 14 loads
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Net ram/RA_1_sqmuxa: 14 loads
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Net ram/RS22: 14 loads
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Number of warnings: 1
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Number of errors: 0
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<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
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WARNING - map: OSCH 'OSCH_inst' has FREQUENCY preference value set to 44.30 MHZ,
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which is different from the actual value 44.33 MHZ. The FREQUENCY
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preference is still within the 5.5% tolerence of the actual value.
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<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
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+---------------------+-----------+-----------+------------+
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| IO Name | Direction | Levelmode | IO |
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| | | IO_TYPE | Register |
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+---------------------+-----------+-----------+------------+
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| BD[0] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| LED | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| PHI0 | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| FCK | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nFCS | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| MOSI | BIDIR | LVCMOS33 | TRI |
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+---------------------+-----------+-----------+------------+
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| MISO | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| RD[7] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[6] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[5] | BIDIR | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| RD[4] | BIDIR | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| RD[3] | BIDIR | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| RD[2] | BIDIR | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| RD[1] | BIDIR | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| RD[0] | BIDIR | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| DQMH | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| DQML | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| nRWE | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| nCAS | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| nRAS | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RCKE | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| nRCS | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[12] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[11] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[10] | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RA[9] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[8] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[7] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[6] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[5] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[4] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[3] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[2] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[1] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[0] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RBA[1] | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RBA[0] | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RCLK | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nIOSTRB | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nDEVSEL | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nIOSEL | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nDinOE | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nDoutOE | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| BD[7] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| BD[6] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| BD[5] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| BD[4] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| BD[3] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| BD[2] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| BD[1] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| nWE | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| BA[10] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| BA[9] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| BA[8] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| BA[7] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| BA[6] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| BA[5] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| BA[4] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| BA[3] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| BA[2] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| BA[1] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| BA[0] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| SW[2] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| SW[1] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nIRQout | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nRESout | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nRESin | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
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Block GSR_INST undriven or does not drive anything - clipped.
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Block CLKin_pad undriven or does not drive anything - clipped.
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Block BA_pad[11] undriven or does not drive anything - clipped.
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Block BA_pad[12] undriven or does not drive anything - clipped.
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Block BA_pad[13] undriven or does not drive anything - clipped.
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Block BA_pad[14] undriven or does not drive anything - clipped.
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Block BA_pad[15] undriven or does not drive anything - clipped.
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Block bi/VCC undriven or does not drive anything - clipped.
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Block bi/GND undriven or does not drive anything - clipped.
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Block registers/VCC undriven or does not drive anything - clipped.
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Signal ic.MISOr.CN was merged into signal CLK
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Signal bi/S_i[1] was merged into signal bi/S[1]
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Signal bi.nRESr.CN was merged into signal PHI0_c
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Signal ic.SetRestoreEN_i was merged into signal ic/SetRestoreEN
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Signal RDOE_i was merged into signal ram/RDOE
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Signal registers/GND undriven or does not drive anything - clipped.
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Signal CLKin_c undriven or does not drive anything - clipped.
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Signal CLKin undriven or does not drive anything - clipped.
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Signal BA_c[11] undriven or does not drive anything - clipped.
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Signal BA[11] undriven or does not drive anything - clipped.
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Signal BA_c[12] undriven or does not drive anything - clipped.
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Signal BA[12] undriven or does not drive anything - clipped.
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Signal BA_c[13] undriven or does not drive anything - clipped.
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Signal BA[13] undriven or does not drive anything - clipped.
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Signal BA_c[14] undriven or does not drive anything - clipped.
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Signal BA[14] undriven or does not drive anything - clipped.
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Signal BA_c[15] undriven or does not drive anything - clipped.
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Signal BA[15] undriven or does not drive anything - clipped.
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Signal registers/un1_Addr_2_s_7_0_S1 undriven or does not drive anything -
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clipped.
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Signal registers/un1_Addr_2_s_7_0_COUT undriven or does not drive anything -
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clipped.
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Signal registers/un1_Addr_1_cry_0_0_S0 undriven or does not drive anything -
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clipped.
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Signal registers/N_3 undriven or does not drive anything - clipped.
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Signal registers/un1_Addr_1_s_7_0_S1 undriven or does not drive anything -
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clipped.
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Signal registers/un1_Addr_1_s_7_0_COUT undriven or does not drive anything -
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clipped.
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Signal registers/un1_Addr_cry_0_0_S0 undriven or does not drive anything -
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clipped.
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Signal registers/N_4 undriven or does not drive anything - clipped.
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Signal registers/un1_Addr_s_7_0_S1 undriven or does not drive anything -
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clipped.
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Signal registers/un1_Addr_s_7_0_COUT undriven or does not drive anything -
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clipped.
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Signal registers/un1_Addr_2_cry_0_0_S0 undriven or does not drive anything -
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clipped.
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Signal registers/N_2 undriven or does not drive anything - clipped.
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Signal ic/un2_LS_1_cry_0_0_S1 undriven or does not drive anything - clipped.
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Signal ic/un2_LS_1_cry_0_0_S0 undriven or does not drive anything - clipped.
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Signal ic/N_1 undriven or does not drive anything - clipped.
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Signal ic/un2_LS_1_cry_11_0_COUT undriven or does not drive anything - clipped.
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Signal ic/un2_CS_cry_0_0_S1 undriven or does not drive anything - clipped.
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Signal ic/un2_CS_cry_0_0_S0 undriven or does not drive anything - clipped.
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Signal ic/N_2 undriven or does not drive anything - clipped.
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Signal ic/un2_CS_cry_11_0_COUT undriven or does not drive anything - clipped.
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Signal OSCH_inst_SEDSTDBY undriven or does not drive anything - clipped.
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Block bi/PHI0r_0_.CN was optimized away.
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Block bi/S_RNIL2O[1] was optimized away.
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Block bi/WRD_2_.CN was optimized away.
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Block ic/SetRestoreEN_RNITQI was optimized away.
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Block ram/RDOE_RNIOU95 was optimized away.
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Block registers/GND was optimized away.
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OSC Summary
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-----------
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OSC 1: Pin/Node Value
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OSC Instance Name: OSCH_inst
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OSC Type: OSCH
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STDBY Input: NONE
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OSC Output: NODE CLK
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OSC Nominal Frequency (MHz): 44.33
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<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
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---------------
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Instance Name: OSCH_inst
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Type: OSCH
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<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
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-------------------------
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Total CPU Time: 0 secs
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Total REAL Time: 0 secs
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Peak Memory Usage: 60 MB
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
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reserved.
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