mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2026-03-13 14:16:25 +00:00
56 lines
2.6 KiB
Plaintext
56 lines
2.6 KiB
Plaintext
|
|
Copyright (C) 1994-2018 Synopsys, Inc.
|
|
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
|
Synopsys software or the associated documentation is strictly prohibited.
|
|
Tool: Synplify Pro (R)
|
|
Build: N-2018.03L-SP1-1
|
|
Install: C:\lscc\diamond\3.11_x64\synpbase
|
|
OS: Windows 6.2
|
|
|
|
Hostname: ZANEMACWIN11
|
|
|
|
Implementation : impl1
|
|
|
|
# Written on Sun Jul 14 06:18:42 2024
|
|
|
|
##### FILES SYNTAX CHECKED ##############################################
|
|
Constraint File(s): "\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.sdc"
|
|
|
|
#Run constraint checker to find more issues with constraints.
|
|
#########################################################################
|
|
|
|
|
|
|
|
No issues found in constraint syntax.
|
|
|
|
|
|
|
|
Clock Summary
|
|
*************
|
|
|
|
Start Requested Requested Clock Clock Clock
|
|
Level Clock Frequency Period Type Group Load
|
|
----------------------------------------------------------------------------------------
|
|
0 - CLK 44.3 MHz 22.558 declared default_clkgroup 174
|
|
|
|
0 - PHI0 1.0 MHz 977.000 declared default_clkgroup 10
|
|
|
|
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
|
========================================================================================
|
|
|
|
|
|
Clock Load Summary
|
|
******************
|
|
|
|
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
|
Clock Load Pin Seq Example Seq Example Comb Example
|
|
-------------------------------------------------------------------------------------------------------
|
|
CLK 174 OSCH_inst.OSC(OSCH) ram.RDDLE.C - ram.un1_CLK.I[0](inv)
|
|
|
|
PHI0 10 PHI0(port) bi.nRESr.C bi.PHI0r[0].D[0] bi.un1_PHI0.I[0](inv)
|
|
|
|
System 0 - - - -
|
|
=======================================================================================================
|