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GR8RAM/cpld/LCMXO2-640HC/impl1/backup/GR8RAM_LCMXO2_640HC_impl1.srr
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#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Mon Jul 8 22:52:33 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v" (library work)
@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\SlinkyRegisters.v" (library work)
@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\BusInterface.v" (library work)
@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\InitController.v" (library work)
@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\SDRAMController.v" (library work)
Verilog syntax check successful!
Selecting top level module GR8RAM
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1793:7:1793:10|Synthesizing module OSCH in library work.
Running optimization stage 1 on OSCH .......
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\BusInterface.v":1:8:1:19|Synthesizing module BusInterface in library work.
Running optimization stage 1 on BusInterface .......
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\SlinkyRegisters.v":1:7:1:21|Synthesizing module SlinkyRegisters in library work.
Running optimization stage 1 on SlinkyRegisters .......
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\InitController.v":1:7:1:20|Synthesizing module InitController in library work.
Running optimization stage 1 on InitController .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
Running optimization stage 1 on ODDRXE .......
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\SDRAMController.v":1:7:1:21|Synthesizing module SDRAMController in library work.
Running optimization stage 1 on SDRAMController .......
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":1:7:1:12|Synthesizing module GR8RAM in library work.
Running optimization stage 1 on GR8RAM .......
Running optimization stage 2 on GR8RAM .......
Running optimization stage 2 on SDRAMController .......
Running optimization stage 2 on ODDRXE .......
Running optimization stage 2 on InitController .......
Running optimization stage 2 on SlinkyRegisters .......
Running optimization stage 2 on BusInterface .......
@W: CL246 :"\\Mac\iCloud\Repos\GR8RAM\cpld\BusInterface.v":12:15:12:16|Input port bits 15 to 11 of BA[15:0] are unused. Assign logic for all port bits or change the input port size.
Running optimization stage 2 on OSCH .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Mon Jul 8 22:52:34 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Mon Jul 8 22:52:34 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-640HC\impl1\synwork\GR8RAM_LCMXO2_640HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Mon Jul 8 22:52:34 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-640HC\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Mon Jul 8 22:52:35 2024
###########################################################]
Premap Report
# Mon Jul 8 22:52:35 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
Reading constraint file: \\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.sdc
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-640HC\impl1\GR8RAM_LCMXO2_640HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-640HC\impl1\GR8RAM_LCMXO2_640HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\businterface.v":139:1:139:6|Removing sequential instance ROMRD (in view: work.BusInterface(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\slinkyregisters.v":65:1:65:6|Removing sequential instance Bank (in view: work.SlinkyRegisters(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.
@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":73:1:73:6|Removing sequential instance SetROM[1:0] (in view: work.InitController(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":73:1:73:6|Removing sequential instance RestoreEN (in view: work.InitController(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":80:1:80:6|Removing sequential instance SWOE (in view: work.InitController(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\businterface.v":106:1:106:6|Removing sequential instance BankWR (in view: work.BusInterface(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\businterface.v":53:1:53:6|Removing sequential instance nIOSTRBr[1] (in view: work.BusInterface(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\businterface.v":106:1:106:6|Removing sequential instance BankWRpre (in view: work.BusInterface(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\businterface.v":52:1:52:6|Removing sequential instance nIOSTRBr[0] (in view: work.BusInterface(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
syn_allowed_resources : blockrams=2 set on top level netlist GR8RAM
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
----------------------------------------------------------------------------------------
0 - CLK 47.6 MHz 21.000 declared default_clkgroup 179
0 - PHI0 1.0 MHz 977.000 declared default_clkgroup 10
0 - System 100.0 MHz 10.000 system system_clkgroup 0
========================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
------------------------------------------------------------------------------------------------------------
CLK 179 OSCH_inst.OSC(OSCH) bi.nDEVSELr[1].C - bi.un1_CLK.I[0](inv)
PHI0 10 PHI0(port) bi.nRESr.C bi.PHI0r[0].D[0] bi.un1_PHI0.I[0](inv)
System 0 - - - -
============================================================================================================
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 188 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 OSCH_inst.OSC OSCH 179 bi.BDout[7:0]
@KP:ckid0_1 PHI0 port 9 bi.WRD[7:0]
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Jul 8 22:52:36 2024
###########################################################]
Map & Optimize Report
# Mon Jul 8 22:52:36 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":98:13:98:16|ROM RAMPC_2 (in view: work.InitController(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":98:13:98:16|ROM FCKEN_2 (in view: work.InitController(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":98:13:98:16|ROM MOSIOE_2[3:0] (in view: work.InitController(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":98:13:98:16|Found ROM MOSIOE_2[3:0] (in view: work.InitController(verilog)) with 70 words by 4 bits.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":98:13:98:16|ROM RAMPC_2 (in view: work.InitController(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":98:13:98:16|Found ROM RAMPC_2 (in view: work.InitController(verilog)) with 70 words by 1 bit.
@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":98:13:98:16|ROM FCKEN_2 (in view: work.InitController(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":98:13:98:16|Found ROM FCKEN_2 (in view: work.InitController(verilog)) with 70 words by 1 bit.
@N: FX493 |Applying initial value "000" on instance ram.RS[2:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 147MB peak: 148MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 148MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 162MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:02s -1.04ns 309 / 188
@N: FX271 :"\\mac\icloud\repos\gr8ram\cpld\businterface.v":59:1:59:6|Replicating instance bi.WRD[7] (in view: work.GR8RAM(verilog)) with 5 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 162MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RBA_1_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RBA_0_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.DQMH.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.DQML.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_12_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_11_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_10_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_9_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_8_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_7_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_6_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_5_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_4_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_3_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_2_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_1_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":53:2:53:7|Boundary register ram.RA_0_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 162MB)
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 126MB peak: 162MB)
Writing Analyst data base \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-640HC\impl1\synwork\GR8RAM_LCMXO2_640HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 159MB peak: 162MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-640HC\impl1\GR8RAM_LCMXO2_640HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 163MB peak: 165MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 163MB peak: 165MB)
@W: MT246 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":198:11:198:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock CLK with period 21.00ns
@N: MT615 |Found clock PHI0 with period 977.00ns
##### START OF TIMING REPORT #####[
# Timing Report written on Mon Jul 8 22:52:40 2024
#
Top view: GR8RAM
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): \\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.sdc
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: -1.145
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------
CLK 47.6 MHz 14.5 MHz 21.000 69.107 7.743 declared default_clkgroup
PHI0 1.0 MHz 0.3 MHz 977.000 3215.112 -1.145 declared default_clkgroup
System 100.0 MHz NA 10.000 NA NA system system_clkgroup
===================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
@W: MT118 |Paths from clock (PHI0:f) to clock (CLK:r) are overconstrained because the required time of 0.50 ns is too small.
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------
CLK System | 21.000 20.028 | No paths - | No paths - | No paths -
CLK CLK | 21.000 12.994 | No paths - | 10.500 8.809 | 10.500 7.743
PHI0 CLK | No paths - | No paths - | No paths - | 0.500 -1.145
==========================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: CLK
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------
ram_RDDio[0] CLK IFS1P3DX Q RDD[0] 0.972 7.743
ram_RDDio[1] CLK IFS1P3DX Q RDD[1] 0.972 7.743
ram_RDDio[2] CLK IFS1P3DX Q RDD[2] 0.972 7.743
ram_RDDio[3] CLK IFS1P3DX Q RDD[3] 0.972 7.743
ram_RDDio[4] CLK IFS1P3DX Q RDD[4] 0.972 7.743
ram_RDDio[5] CLK IFS1P3DX Q RDD[5] 0.972 7.743
ram_RDDio[6] CLK IFS1P3DX Q RDD[6] 0.972 7.743
ram_RDDio[7] CLK IFS1P3DX Q RDD[7] 0.972 7.743
ram.RDDLE CLK FD1S3IX Q RDDLE 1.220 8.809
ic.MOSIr CLK FD1S3AX Q MOSIr 0.972 9.423
================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------
bi_BDoutio[0] CLK OFS1P3DX D bi.BDout_8[0] 10.394 7.743
bi_BDoutio[1] CLK OFS1P3DX D bi.BDout_8[1] 10.394 7.743
bi_BDoutio[2] CLK OFS1P3DX D bi.BDout_8[2] 10.394 7.743
bi_BDoutio[3] CLK OFS1P3DX D bi.BDout_8[3] 10.394 7.743
bi_BDoutio[4] CLK OFS1P3DX D bi.BDout_8[4] 10.394 7.743
bi_BDoutio[5] CLK OFS1P3DX D bi.BDout_8[5] 10.394 7.743
bi_BDoutio[6] CLK OFS1P3DX D bi.BDout_8[6] 10.394 7.743
bi_BDoutio[7] CLK OFS1P3DX D bi.BDout_8[7] 10.394 7.743
ram_RDDio[0] CLK IFS1P3DX SP ram.RDDLE 10.028 8.809
ram_RDDio[1] CLK IFS1P3DX SP ram.RDDLE 10.028 8.809
=========================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.500
- Setup time: 0.106
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 10.394
- Propagation time: 2.652
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 7.743
Number of logic level(s): 3
Starting point: ram_RDDio[0] / Q
Ending point: bi_BDoutio[0] / D
The start point is clocked by CLK [falling] on pin SCLK
The end point is clocked by CLK [rising] on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
ram_RDDio[0] IFS1P3DX Q Out 0.972 0.972 -
RDD[0] Net - - - - 1
bi.BDout_8_2_bm[0] ORCALUT4 B In 0.000 0.972 -
bi.BDout_8_2_bm[0] ORCALUT4 Z Out 1.017 1.989 -
BDout_8_2_bm[0] Net - - - - 1
bi.BDout_8_2[0] PFUMX ALUT In 0.000 1.989 -
bi.BDout_8_2[0] PFUMX Z Out 0.214 2.203 -
N_66 Net - - - - 1
bi.BDout_8[0] ORCALUT4 C In 0.000 2.203 -
bi.BDout_8[0] ORCALUT4 Z Out 0.449 2.652 -
BDout_8[0] Net - - - - 1
bi_BDoutio[0] OFS1P3DX D In 0.000 2.652 -
=====================================================================================
====================================
Detailed Report for Clock: PHI0
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
bi_nRESrio PHI0 IFS1P3DX Q bi.nRESr 0.972 -1.145
bi.WRD[0] PHI0 FD1S3AX Q BI_WRD[0] 1.108 -1.136
bi.WRD[1] PHI0 FD1S3AX Q BI_WRD[1] 1.108 -1.136
bi.WRD[2] PHI0 FD1S3AX Q BI_WRD[2] 1.108 -1.136
bi.WRD[3] PHI0 FD1S3AX Q BI_WRD[3] 1.108 -1.136
bi.WRD[4] PHI0 FD1S3AX Q BI_WRD[4] 1.108 -1.136
bi.WRD[5] PHI0 FD1S3AX Q BI_WRD[5] 1.108 -1.136
bi.WRD[6] PHI0 FD1S3AX Q BI_WRD[6] 1.108 -1.136
bi.WRD[7] PHI0 FD1S3AX Q BI_WRD[7] 1.108 -1.136
bi.WRD_fast[7] PHI0 FD1S3AX Q WRD_fast[7] 1.044 -1.072
========================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------
bi.RegReset PHI0 FD1P3IX D nRESr_i 0.394 -1.145
registers.Addr_1[0] PHI0 FD1S3IX D Addr_28[0] 0.589 -1.136
registers.Addr_1[1] PHI0 FD1S3IX D Addr_28[1] 0.589 -1.136
registers.Addr_1[2] PHI0 FD1S3IX D Addr_28[2] 0.589 -1.136
registers.Addr_1[3] PHI0 FD1S3IX D Addr_28[3] 0.589 -1.136
registers.Addr_1[4] PHI0 FD1S3IX D Addr_28[4] 0.589 -1.136
registers.Addr_1[5] PHI0 FD1S3IX D Addr_28[5] 0.589 -1.136
registers.Addr_1[6] PHI0 FD1S3IX D Addr_28[6] 0.589 -1.136
registers.Addr_1[7] PHI0 FD1S3IX D Addr_28[7] 0.589 -1.136
registers.Addr_1[8] PHI0 FD1S3IX D Addr_20[8] 0.589 -1.136
============================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 0.500
- Setup time: 0.106
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.394
- Propagation time: 1.540
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -1.145
Number of logic level(s): 1
Starting point: bi_nRESrio / Q
Ending point: bi.RegReset / D
The start point is clocked by PHI0 [falling] on pin SCLK
The end point is clocked by CLK [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
bi_nRESrio IFS1P3DX Q Out 0.972 0.972 -
bi.nRESr Net - - - - 1
bi.RegReset_RNO INV A In 0.000 0.972 -
bi.RegReset_RNO INV Z Out 0.568 1.540 -
nRESr_i Net - - - - 1
bi.RegReset FD1P3IX D In 0.000 1.540 -
==================================================================================
Path information for path number 2:
Requested Period: 0.500
- Setup time: -0.089
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.589
- Propagation time: 1.725
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.136
Number of logic level(s): 1
Starting point: bi.WRD[0] / Q
Ending point: registers.Addr_1[16] / D
The start point is clocked by PHI0 [falling] on pin CK
The end point is clocked by CLK [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------
bi.WRD[0] FD1S3AX Q Out 1.108 1.108 -
BI_WRD[0] Net - - - - 3
registers.Addr_12[16] ORCALUT4 B In 0.000 1.108 -
registers.Addr_12[16] ORCALUT4 Z Out 0.617 1.725 -
Addr_12[16] Net - - - - 1
registers.Addr_1[16] FD1S3IX D In 0.000 1.725 -
========================================================================================
Path information for path number 3:
Requested Period: 0.500
- Setup time: -0.089
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.589
- Propagation time: 1.725
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.136
Number of logic level(s): 1
Starting point: bi.WRD[1] / Q
Ending point: registers.Addr_1[17] / D
The start point is clocked by PHI0 [falling] on pin CK
The end point is clocked by CLK [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------
bi.WRD[1] FD1S3AX Q Out 1.108 1.108 -
BI_WRD[1] Net - - - - 3
registers.Addr_12[17] ORCALUT4 B In 0.000 1.108 -
registers.Addr_12[17] ORCALUT4 Z Out 0.617 1.725 -
Addr_12[17] Net - - - - 1
registers.Addr_1[17] FD1S3IX D In 0.000 1.725 -
========================================================================================
Path information for path number 4:
Requested Period: 0.500
- Setup time: -0.089
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.589
- Propagation time: 1.725
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.136
Number of logic level(s): 1
Starting point: bi.WRD[2] / Q
Ending point: registers.Addr_1[18] / D
The start point is clocked by PHI0 [falling] on pin CK
The end point is clocked by CLK [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------
bi.WRD[2] FD1S3AX Q Out 1.108 1.108 -
BI_WRD[2] Net - - - - 3
registers.Addr_12[18] ORCALUT4 B In 0.000 1.108 -
registers.Addr_12[18] ORCALUT4 Z Out 0.617 1.725 -
Addr_12[18] Net - - - - 1
registers.Addr_1[18] FD1S3IX D In 0.000 1.725 -
========================================================================================
Path information for path number 5:
Requested Period: 0.500
- Setup time: -0.089
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 0.589
- Propagation time: 1.725
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.136
Number of logic level(s): 1
Starting point: bi.WRD[3] / Q
Ending point: registers.Addr_1[19] / D
The start point is clocked by PHI0 [falling] on pin CK
The end point is clocked by CLK [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------
bi.WRD[3] FD1S3AX Q Out 1.108 1.108 -
BI_WRD[3] Net - - - - 3
registers.Addr_12[19] ORCALUT4 B In 0.000 1.108 -
registers.Addr_12[19] ORCALUT4 Z Out 0.617 1.725 -
Addr_12[19] Net - - - - 1
registers.Addr_1[19] FD1S3IX D In 0.000 1.725 -
========================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 163MB peak: 165MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 163MB peak: 165MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_640hc-4
Register bits: 189 of 640 (30%)
PIC Latch: 0
I/O cells: 66
Details:
BB: 17
CCU2D: 29
FD1P3AX: 9
FD1P3IX: 27
FD1P3JX: 2
FD1S3AX: 68
FD1S3IX: 41
FD1S3JX: 10
GSR: 1
IB: 20
IFS1P3DX: 13
INV: 7
OB: 29
ODDRXE: 2
OFS1P3DX: 9
OFS1P3IX: 6
OFS1P3JX: 4
ORCALUT4: 298
OSCH: 1
PFUMX: 9
PUR: 1
VHI: 5
VLO: 5
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 33MB peak: 165MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Mon Jul 8 22:52:40 2024
###########################################################]
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