mirror of
https://github.com/garrettsworkshop/GR8RAM.git
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129 lines
6.8 KiB
Plaintext
129 lines
6.8 KiB
Plaintext
# Sun Jul 14 06:18:42 2024
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Copyright (C) 1994-2018 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: N-2018.03L-SP1-1
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Install: C:\lscc\diamond\3.11_x64\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Reading constraint file: \\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.sdc
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@N: MF284 |Setting synthesis effort to medium for the design
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@L: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-640HC\impl1\GR8RAM_LCMXO2_640HC_impl1_scck.rpt
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Printing clock summary report in "\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-640HC\impl1\GR8RAM_LCMXO2_640HC_impl1_scck.rpt" file
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@N: MF916 |Option synthesis_strategy=base is enabled.
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
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@N: MF284 |Setting synthesis effort to medium for the design
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@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
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@N: MH105 |UMR3 is only supported for HAPS-80.
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@N: MH105 |UMR3 is only supported for HAPS-80.
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@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\businterface.v":122:1:122:6|Removing sequential instance ROMRD (in view: work.BusInterface(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
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@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\slinkyregisters.v":65:1:65:6|Removing sequential instance Bank (in view: work.SlinkyRegisters(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.
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@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\businterface.v":97:1:97:6|Removing sequential instance BankWR (in view: work.BusInterface(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
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@N: BN362 :"\\mac\icloud\repos\gr8ram\cpld\businterface.v":97:1:97:6|Removing sequential instance BankWRpre (in view: work.BusInterface(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
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syn_allowed_resources : blockrams=2 set on top level netlist GR8RAM
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
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Clock Summary
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******************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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----------------------------------------------------------------------------------------
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0 - CLK 44.3 MHz 22.558 declared default_clkgroup 174
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0 - PHI0 1.0 MHz 977.000 declared default_clkgroup 10
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0 - System 100.0 MHz 10.000 system system_clkgroup 0
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========================================================================================
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Clock Load Summary
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***********************
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Clock Source Clock Pin Non-clock Pin Non-clock Pin
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Clock Load Pin Seq Example Seq Example Comb Example
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-------------------------------------------------------------------------------------------------------
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CLK 174 OSCH_inst.OSC(OSCH) ram.RDDLE.C - ram.un1_CLK.I[0](inv)
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PHI0 10 PHI0(port) bi.nRESr.C bi.PHI0r[0].D[0] bi.un1_PHI0.I[0](inv)
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System 0 - - - -
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=======================================================================================================
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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@S |Clock Optimization Summary
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#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
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2 non-gated/non-generated clock tree(s) driving 183 clock pin(s) of sequential element(s)
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0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
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0 instances converted, 0 sequential instances remain driven by gated/generated clocks
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=========================== Non-Gated/Non-Generated Clocks ============================
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Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
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---------------------------------------------------------------------------------------
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@KP:ckid0_0 OSCH_inst.OSC OSCH 174 ram.RDOE
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@KP:ckid0_1 PHI0 port 9 bi.WRD[7:0]
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=======================================================================================
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##### END OF CLOCK OPTIMIZATION REPORT ######
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@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
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Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
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None
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Sun Jul 14 06:18:43 2024
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###########################################################]
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