mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2026-03-13 14:16:25 +00:00
32 lines
2.3 KiB
Plaintext
32 lines
2.3 KiB
Plaintext
Selecting top level module GR8RAM
|
|
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1793:7:1793:10|Synthesizing module OSCH in library work.
|
|
Running optimization stage 1 on OSCH .......
|
|
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\BusInterface.v":1:8:1:19|Synthesizing module BusInterface in library work.
|
|
Running optimization stage 1 on BusInterface .......
|
|
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\SlinkyRegisters.v":1:7:1:21|Synthesizing module SlinkyRegisters in library work.
|
|
Running optimization stage 1 on SlinkyRegisters .......
|
|
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":82:7:82:8|Synthesizing module BB in library work.
|
|
Running optimization stage 1 on BB .......
|
|
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
|
|
Running optimization stage 1 on ODDRXE .......
|
|
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":868:7:868:9|Synthesizing module OBZ in library work.
|
|
Running optimization stage 1 on OBZ .......
|
|
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\InitController.v":1:7:1:20|Synthesizing module InitController in library work.
|
|
Running optimization stage 1 on InitController .......
|
|
@N: CL189 :"\\Mac\iCloud\Repos\GR8RAM\cpld\InitController.v":82:1:82:6|Register bit InitDone is always 0.
|
|
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\SDRAMController.v":1:7:1:21|Synthesizing module SDRAMController in library work.
|
|
Running optimization stage 1 on SDRAMController .......
|
|
@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":1:7:1:12|Synthesizing module GR8RAM in library work.
|
|
Running optimization stage 1 on GR8RAM .......
|
|
Running optimization stage 2 on GR8RAM .......
|
|
@W: CL246 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":15:14:15:15|Input port bits 15 to 11 of BA[15:0] are unused. Assign logic for all port bits or change the input port size.
|
|
@N: CL159 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":5:7:5:11|Input CLKin is unused.
|
|
Running optimization stage 2 on SDRAMController .......
|
|
Running optimization stage 2 on InitController .......
|
|
Running optimization stage 2 on OBZ .......
|
|
Running optimization stage 2 on ODDRXE .......
|
|
Running optimization stage 2 on BB .......
|
|
Running optimization stage 2 on SlinkyRegisters .......
|
|
Running optimization stage 2 on BusInterface .......
|
|
Running optimization stage 2 on OSCH .......
|