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GR8RAM/cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.par
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Zane Kaminski d40c6cf8bf Lots?
2025-03-30 05:03:20 -04:00

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PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Jun 13 00:38:53 2024
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f GR8RAM_LCMXO2_1200HC_impl1.p2t
GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir
GR8RAM_LCMXO2_1200HC_impl1.prf -gui -msgset
//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml
Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 - - - - 10 Completed
* : Design saved.
Total (real) run time for 1-seed: 10 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Lattice Place and Route Report for Design "GR8RAM_LCMXO2_1200HC_impl1_map.ncd"
Thu Jun 13 00:38:53 2024
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd GR8RAM_LCMXO2_1200HC_impl1.prf
Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file GR8RAM_LCMXO2_1200HC_impl1_map.ncd.
Design name: GR8RAM
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 73+4(JTAG)/108 71% used
73+4(JTAG)/80 96% bonded
IOLOGIC 51/108 47% used
SLICE 136/640 21% used
GSR 1/1 100% used
Number of Signals: 430
Number of Connections: 1211
Pin Constraint Summary:
73 out of 73 pins locked (100% locked).
The following 2 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 80)
PHI0_c (driver: PHI0, clk load #: 14)
WARNING - par: Signal "PHI0_c" is selected to use Primary clock resources. However, its driver comp "PHI0" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 1 signal is selected to use the secondary clock routing resources:
FCKout120 (driver: SLICE_54, clk load #: 0, sr load #: 13, ce load #: 0)
Signal nRESr is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
....................
Placer score = 87858.
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
.
Placer score = 86903
Finished Placer Phase 2. REAL time: 4 secs
------------------ Clock Report ------------------
Global Clock Resources:
CLK_PIN : 1 out of 8 (12%)
General PIO: 1 out of 108 (0%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "38 (PB11A)", clk load = 80
PRIMARY "PHI0_c" from comp "PHI0" on PIO site "17 (PL8B)", clk load = 14
SECONDARY "FCKout120" from F0 on comp "SLICE_54" on site "R7C12B", clk load = 0, ce load = 0, sr load = 13
PRIMARY : 2 out of 8 (25%)
SECONDARY: 1 out of 8 (12%)
Edge Clocks:
No edge clock selected.
--------------- End of Clock Report ---------------
I/O Usage Summary (final):
73 + 4(JTAG) out of 108 (71.3%) PIO sites used.
73 + 4(JTAG) out of 80 (96.3%) bonded PIO sites used.
Number of PIO comps: 73; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 13 / 19 ( 68%) | 3.3V | - |
| 1 | 20 / 21 ( 95%) | 3.3V | - |
| 2 | 20 / 20 (100%) | 3.3V | - |
| 3 | 20 / 20 (100%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 3 secs
Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
-----------------------------------------------------------------
INFO - par: ASE feature is off due to non timing-driven settings.
-----------------------------------------------------------------
0 connections routed; 1211 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 9 secs
Start NBR router at 00:39:02 06/13/24
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 00:39:02 06/13/24
Start NBR section for initial routing at 00:39:02 06/13/24
Level 4, iteration 1
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 00:39:02 06/13/24
Level 4, iteration 1
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Start NBR section for re-routing at 00:39:02 06/13/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
Start NBR section for post-routing at 00:39:02 06/13/24
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : <n/a>
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 8 secs
Total REAL time: 9 secs
Completely routed.
End of route. 1211 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a>
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a>
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 9 secs
Total REAL time to completion: 10 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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