mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2026-04-21 02:17:39 +00:00
Zane Kaminski
162 lines
3.5 KiB
Plaintext
162 lines
3.5 KiB
Plaintext
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Copyright (C) 1994-2018 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: N-2018.03L-SP1-1
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Install: C:\lscc\diamond\3.11_x64\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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# Written on Thu Jun 13 00:38:48 2024
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##### DESIGN INFO #######################################################
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Top View: "GR8RAM"
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Constraint File(s): (none)
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##### SUMMARY ############################################################
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Found 0 issues in 0 out of 0 constraints
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##### DETAILS ############################################################
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Clock Relationships
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*******************
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Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
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-------------------------------------------------------------------------------------------------------------------------------------------
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GR8RAM|PHI0 GR8RAM|RCLK | Diff grp | No paths | Diff grp | No paths
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GR8RAM|RCLK GR8RAM|RCLK | 10.000 | No paths | 5.000 | No paths
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===========================================================================================================================================
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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Unconstrained Start/End Points
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******************************
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p:DQMH
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p:DQML
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p:FCK
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p:LED
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p:MISO
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p:MOSI (bidir end point)
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p:MOSI (bidir start point)
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p:RA[0]
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p:RA[1]
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p:RA[2]
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p:RA[3]
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p:RA[4]
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p:RA[5]
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p:RA[6]
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p:RA[7]
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p:RA[8]
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p:RA[9]
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p:RA[10]
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p:RA[11]
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p:RA[12]
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p:RA[13]
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p:RA[14]
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p:RA[15]
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p:RCKE
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p:RCLKout
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p:RD[0] (bidir end point)
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p:RD[0] (bidir start point)
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p:RD[1] (bidir end point)
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p:RD[1] (bidir start point)
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p:RD[2] (bidir end point)
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p:RD[2] (bidir start point)
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p:RD[3] (bidir end point)
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p:RD[3] (bidir start point)
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p:RD[4] (bidir end point)
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p:RD[4] (bidir start point)
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p:RD[5] (bidir end point)
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p:RD[5] (bidir start point)
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p:RD[6] (bidir end point)
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p:RD[6] (bidir start point)
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p:RD[7] (bidir end point)
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p:RD[7] (bidir start point)
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p:SA[0]
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p:SA[1]
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p:SA[2]
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p:SA[3]
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p:SA[4]
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p:SA[5]
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p:SA[6]
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p:SA[7]
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p:SA[8]
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p:SA[9]
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p:SA[10]
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p:SA[11]
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p:SA[12]
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p:SBA[0]
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p:SBA[1]
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p:SD[0] (bidir end point)
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p:SD[0] (bidir start point)
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p:SD[1] (bidir end point)
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p:SD[1] (bidir start point)
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p:SD[2] (bidir end point)
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p:SD[2] (bidir start point)
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p:SD[3] (bidir end point)
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p:SD[3] (bidir start point)
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p:SD[4] (bidir end point)
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p:SD[4] (bidir start point)
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p:SD[5] (bidir end point)
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p:SD[5] (bidir start point)
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p:SD[6] (bidir end point)
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p:SD[6] (bidir start point)
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p:SD[7] (bidir end point)
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p:SD[7] (bidir start point)
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p:SetFW[0]
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p:SetFW[1]
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p:nCAS
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p:nDEVSEL
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p:nDinOE
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p:nFCS
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p:nIOSEL
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p:nIOSTRB
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p:nIRQout
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p:nRAS
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p:nRCS
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p:nRES
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p:nRESout
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p:nSWE
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p:nWE
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Inapplicable constraints
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************************
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(none)
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Applicable constraints with issues
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**********************************
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(none)
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Constraints with matching wildcard expressions
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**********************************************
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(none)
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Library Report
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**************
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# End of Constraint Checker Report
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