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Zane Kaminski
302 lines
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HTML
302 lines
11 KiB
HTML
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<HEAD><TITLE>Place & Route Report</TITLE>
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p {
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font-size:78%;
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}
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P.Table {
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}
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border-collapse: collapse;
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{
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background-color: #00ff00;
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}
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{
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.11.3.469.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Thu Jun 13 00:38:53 2024
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C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f GR8RAM_LCMXO2_1200HC_impl1.p2t
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GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir
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GR8RAM_LCMXO2_1200HC_impl1.prf -gui -msgset
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//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml
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Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
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<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
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Level/ Number Worst Timing Worst Timing Run NCD
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Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
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---------- -------- ----- ------ ----------- ----------- ---- ------
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5_1 * 0 - - - - 10 Completed
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* : Design saved.
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Total (real) run time for 1-seed: 10 secs
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par done!
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Note: user must run 'Trace' for timing closure signoff.
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Lattice Place and Route Report for Design "GR8RAM_LCMXO2_1200HC_impl1_map.ncd"
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Thu Jun 13 00:38:53 2024
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<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
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PAR: Place And Route Diamond (64-bit) 3.11.3.469.
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd GR8RAM_LCMXO2_1200HC_impl1.prf
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Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
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Placement level-cost: 5-1.
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Routing Iterations: 6
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Loading design for application par from file GR8RAM_LCMXO2_1200HC_impl1_map.ncd.
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Design name: GR8RAM
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-1200HC
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Package: TQFP100
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Performance: 4
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Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
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Package Status: Final Version 1.42.
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Performance Hardware Data Status: Final Version 34.4.
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License checked out.
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Ignore Preference Error(s): True
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<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
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PIO (prelim) 73+4(JTAG)/108 71% used
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73+4(JTAG)/80 96% bonded
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IOLOGIC 51/108 47% used
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SLICE 136/640 21% used
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GSR 1/1 100% used
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Number of Signals: 430
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Number of Connections: 1211
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Pin Constraint Summary:
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73 out of 73 pins locked (100% locked).
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The following 2 signals are selected to use the primary clock routing resources:
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RCLK_c (driver: RCLK, clk load #: 80)
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PHI0_c (driver: PHI0, clk load #: 14)
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WARNING - par: Signal "PHI0_c" is selected to use Primary clock resources. However, its driver comp "PHI0" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
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The following 1 signal is selected to use the secondary clock routing resources:
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FCKout120 (driver: SLICE_54, clk load #: 0, sr load #: 13, ce load #: 0)
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Signal nRESr is selected as Global Set/Reset.
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Starting Placer Phase 0.
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.........
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Finished Placer Phase 0. REAL time: 2 secs
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Starting Placer Phase 1.
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....................
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Placer score = 87858.
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Finished Placer Phase 1. REAL time: 4 secs
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Starting Placer Phase 2.
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.
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Placer score = 86903
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Finished Placer Phase 2. REAL time: 4 secs
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<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
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Global Clock Resources:
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CLK_PIN : 1 out of 8 (12%)
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General PIO: 1 out of 108 (0%)
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PLL : 0 out of 1 (0%)
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DCM : 0 out of 2 (0%)
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DCC : 0 out of 8 (0%)
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Global Clocks:
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PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "38 (PB11A)", clk load = 80
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PRIMARY "PHI0_c" from comp "PHI0" on PIO site "17 (PL8B)", clk load = 14
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SECONDARY "FCKout120" from F0 on comp "SLICE_54" on site "R7C12B", clk load = 0, ce load = 0, sr load = 13
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PRIMARY : 2 out of 8 (25%)
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SECONDARY: 1 out of 8 (12%)
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Edge Clocks:
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No edge clock selected.
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I/O Usage Summary (final):
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73 + 4(JTAG) out of 108 (71.3%) PIO sites used.
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73 + 4(JTAG) out of 80 (96.3%) bonded PIO sites used.
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Number of PIO comps: 73; differential: 0.
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Number of Vref pins used: 0.
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I/O Bank Usage Summary:
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+----------+----------------+------------+-----------+
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| I/O Bank | Usage | Bank Vccio | Bank Vref |
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+----------+----------------+------------+-----------+
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| 0 | 13 / 19 ( 68%) | 3.3V | - |
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| 1 | 20 / 21 ( 95%) | 3.3V | - |
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| 2 | 20 / 20 (100%) | 3.3V | - |
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| 3 | 20 / 20 (100%) | 3.3V | - |
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+----------+----------------+------------+-----------+
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Total placer CPU time: 3 secs
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Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
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-----------------------------------------------------------------
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INFO - par: ASE feature is off due to non timing-driven settings.
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-----------------------------------------------------------------
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0 connections routed; 1211 unrouted.
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Starting router resource preassignment
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Completed router resource preassignment. Real time: 9 secs
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Start NBR router at 00:39:02 06/13/24
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*****************************************************************
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Info: NBR allows conflicts(one node used by more than one signal)
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in the earlier iterations. In each iteration, it tries to
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solve the conflicts while keeping the critical connections
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routed as short as possible. The routing process is said to
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be completed when no conflicts exist and all connections
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are routed.
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Note: NBR uses a different method to calculate timing slacks. The
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worst slack and total negative slack may not be the same as
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that in TRCE report. You should always run TRCE to verify
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your design.
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*****************************************************************
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Start NBR special constraint process at 00:39:02 06/13/24
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Start NBR section for initial routing at 00:39:02 06/13/24
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Level 4, iteration 1
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19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
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Info: Initial congestion level at 75% usage is 0
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Info: Initial congestion area at 75% usage is 0 (0.00%)
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Start NBR section for normal routing at 00:39:02 06/13/24
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Level 4, iteration 1
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4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
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Level 4, iteration 2
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1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
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Level 4, iteration 3
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0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
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Start NBR section for re-routing at 00:39:02 06/13/24
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Level 4, iteration 1
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0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs
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Start NBR section for post-routing at 00:39:02 06/13/24
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End NBR router with 0 unrouted connection
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NBR Summary
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-----------
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Number of unrouted connections : 0 (0.00%)
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Number of connections with timing violations : 0 (0.00%)
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Estimated worst slack<setup> : <n/a>
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Timing score<setup> : 0
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-----------
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Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
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Total CPU time 8 secs
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Total REAL time: 9 secs
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Completely routed.
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End of route. 1211 routed (100.00%); 0 unrouted.
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Hold time timing score: 0, hold timing errors: 0
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Timing score: 0
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Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
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All signals are completely routed.
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PAR_SUMMARY::Run status = Completed
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PAR_SUMMARY::Number of unrouted conns = 0
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PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a>
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PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
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PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a>
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PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
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PAR_SUMMARY::Number of errors = 0
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Total CPU time to completion: 9 secs
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Total REAL time to completion: 10 secs
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par done!
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Note: user must run 'Trace' for timing closure signoff.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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