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https://github.com/garrettsworkshop/GR8RAM.git
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79dd794f45
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
164 lines
7.6 KiB
Plaintext
164 lines
7.6 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 32-bit
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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# Date created = 02:27:57 August 06, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# GR8RAM_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY MAX7000S
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set_global_assignment -name DEVICE "EPM7128SLC84-15"
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set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "02:27:57 AUGUST 06, 2019"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name VERILOG_FILE GR8RAM.v
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set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
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set_location_assignment PIN_1 -to nRES
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set_location_assignment PIN_75 -to A[0]
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set_location_assignment PIN_77 -to A[2]
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set_location_assignment PIN_79 -to A[3]
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set_location_assignment PIN_80 -to A[4]
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set_location_assignment PIN_81 -to A[5]
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set_location_assignment PIN_83 -to C7M
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set_location_assignment PIN_84 -to C7M_2
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set_location_assignment PIN_4 -to A[6]
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set_location_assignment PIN_5 -to A[7]
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set_location_assignment PIN_9 -to A[8]
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set_location_assignment PIN_10 -to A[9]
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set_location_assignment PIN_11 -to A[10]
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set_location_assignment PIN_12 -to A[11]
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set_location_assignment PIN_15 -to A[12]
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set_location_assignment PIN_6 -to Q3
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set_location_assignment PIN_16 -to A[13]
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set_location_assignment PIN_17 -to A[14]
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set_location_assignment PIN_18 -to A[15]
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set_location_assignment PIN_20 -to nWE
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set_location_assignment PIN_21 -to nDEVSEL
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set_location_assignment PIN_22 -to nINH
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set_location_assignment PIN_24 -to nIOSTRB
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set_location_assignment PIN_25 -to D[7]
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set_location_assignment PIN_27 -to D[6]
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set_location_assignment PIN_28 -to D[5]
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set_location_assignment PIN_29 -to D[4]
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set_location_assignment PIN_33 -to D[3]
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set_location_assignment PIN_34 -to D[2]
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set_location_assignment PIN_35 -to D[1]
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set_location_assignment PIN_36 -to D[0]
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set_location_assignment PIN_39 -to nCAS0
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set_location_assignment PIN_40 -to nCAS1
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set_location_assignment PIN_41 -to nRCS
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set_location_assignment PIN_45 -to nROE
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set_location_assignment PIN_46 -to RA[9]
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set_location_assignment PIN_48 -to RA[10]
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set_location_assignment PIN_49 -to RA[3]
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set_location_assignment PIN_50 -to RA[2]
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set_location_assignment PIN_51 -to RA[5]
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set_location_assignment PIN_52 -to RA[0]
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set_location_assignment PIN_54 -to RA[1]
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set_location_assignment PIN_55 -to RA[4]
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set_location_assignment PIN_56 -to RA[7]
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set_location_assignment PIN_57 -to RA[6]
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set_location_assignment PIN_58 -to RA[8]
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set_location_assignment PIN_60 -to nRAS
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set_location_assignment PIN_61 -to RD[7]
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set_location_assignment PIN_63 -to RD[5]
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set_location_assignment PIN_64 -to RD[6]
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set_location_assignment PIN_65 -to RD[4]
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set_location_assignment PIN_67 -to nRWE
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set_location_assignment PIN_68 -to RD[3]
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set_location_assignment PIN_69 -to RD[2]
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set_location_assignment PIN_70 -to RD[1]
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set_location_assignment PIN_73 -to RD[0]
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set_location_assignment PIN_74 -to nIOSEL
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set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name AUTO_LCELL_INSERTION OFF
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set_global_assignment -name AUTO_PARALLEL_EXPANDERS OFF
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set_global_assignment -name AUTO_RESOURCE_SHARING OFF
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set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
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set_global_assignment -name SLOW_SLEW_RATE ON
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set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
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set_global_assignment -name ECO_OPTIMIZE_TIMING ON
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set_global_assignment -name ECO_REGENERATE_REPORT ON
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set_location_assignment LC1 -to Addr[0]
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set_location_assignment LC2 -to Addr[1]
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set_location_assignment LC3 -to Addr[2]
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set_location_assignment LC4 -to Addr[3]
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set_location_assignment LC5 -to Addr[4]
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set_location_assignment LC6 -to Addr[5]
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set_location_assignment LC7 -to Addr[6]
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set_location_assignment LC8 -to Addr[7]
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set_location_assignment LC9 -to Addr[8]
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set_location_assignment LC10 -to Addr[9]
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set_location_assignment LC11 -to Addr[10]
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set_location_assignment LC12 -to Addr[11]
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set_location_assignment LC13 -to Addr[12]
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set_location_assignment LC14 -to Addr[13]
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set_location_assignment LC15 -to Addr[14]
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set_location_assignment LC16 -to Addr[15]
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set_global_assignment -name PARALLEL_SYNTHESIS OFF
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set_global_assignment -name STATE_MACHINE_PROCESSING "USER-ENCODED"
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set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS OFF
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set_location_assignment PIN_76 -to A[1]
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set_location_assignment PIN_8 -to PHI0in
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set_location_assignment PIN_2 -to PHI1in
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set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES OFF
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set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES OFF
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set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
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set_global_assignment -name AUTO_TURBO_BIT OFF
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b1_MC
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b2_MC
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b3_MC
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b4_MC
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b5_MC
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b6_MC
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b7_MC
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b8_MC
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b9_MC
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI0seen
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1reg
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b0_MC
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set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to IOROMEN
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set_location_assignment PIN_44 -to nMode |