Apple-2-HW/GR8RAM
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GR8RAM/cpld/db/GR8RAM.cmp0.ddb
Zane Kaminski 79dd794f45 New PLD revision 
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 15:07:38 -04:00

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