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For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
4 lines
151 B
Plaintext
Executable File
4 lines
151 B
Plaintext
Executable File
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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Version_Index = 302049280
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Creation_Time = Fri Oct 18 15:01:17 2019
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